refactor: update to rust 1.60.0

Cargo.lock

@@ -22,9 +22,9 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
 
 [[package]]
 name = "cortex-a"
-version = "6.1.0"
+version = "7.0.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "509fc35485a2b4ddbacabe0bf2212cdfff88da93658608e5cc651afcb75b7733"
+checksum = "5bd95fd055d118f77d4e4d527201b6ceccd13586b19b4dac1270f7081fef0f98"
 dependencies = [
  "tock-registers",
 ]

fs/memfs/src/lib.rs

@@ -1,7 +1,6 @@
 #![feature(
     const_fn_trait_bound,
     const_mut_refs,
-    maybe_uninit_extra,
     maybe_uninit_uninit_array
 )]
 #![no_std]

fs/vfs/src/lib.rs

@@ -1,6 +1,6 @@
 //! Virtual filesystem API and facilities
 #![warn(missing_docs)]
-#![feature(destructuring_assignment, const_fn_trait_bound)]
+#![feature(const_fn_trait_bound)]
 #![no_std]
 
 #[cfg(test)]

kernel/Cargo.toml

@@ -21,7 +21,7 @@ kernel-macros = { path = "macros" }
 fs-macros = { path = "../fs/macros" }
 
 [target.'cfg(target_arch = "aarch64")'.dependencies]
-cortex-a = { version = "6.x.x" }
+cortex-a = { version = "7.0.x" }
 
 [features]
 default = ["aggressive_syscall"]

kernel/src/arch/aarch64/boot/macros.S

@@ -1,16 +0,0 @@
-.macro MOV_L reg, value
-    mov \reg, #((\value) & 0xFFFF)
-    movk \reg, #((\value) >> 16), lsl #16
-.endm
-
-.macro ADR_REL reg, sym
-    adrp \reg, \sym
-    add \reg, \reg, #:lo12:\sym
-.endm
-
-.macro ADR_ABS reg, sym
-    movz \reg, #:abs_g3:\sym
-    movk \reg, #:abs_g2_nc:\sym
-    movk \reg, #:abs_g1_nc:\sym
-    movk \reg, #:abs_g0_nc:\sym
-.endm

kernel/src/arch/aarch64/boot/mod.rs

@@ -4,6 +4,7 @@ use crate::arch::{
     aarch64::reg::{CNTKCTL_EL1, CPACR_EL1},
     machine,
 };
+use core::arch::global_asm;
 use crate::config::{ConfigKey, CONFIG};
 use crate::dev::{
     fdt::{find_prop, DeviceTree},
@@ -120,6 +121,4 @@ extern "C" fn __aa64_bsp_main(fdt_base: usize) -> ! {
     }
 }
 
-global_asm!(include_str!("macros.S"));
 global_asm!(include_str!("uboot.S"));
-global_asm!(include_str!("upper.S"));

kernel/src/arch/aarch64/boot/uboot.S

@@ -1,5 +1,54 @@
 // vi:ft=a64asm.asm:
 
+.macro MOV_L reg, value
+    mov \reg, #((\value) & 0xFFFF)
+    movk \reg, #((\value) >> 16), lsl #16
+.endm
+
+.macro ADR_REL reg, sym
+    adrp \reg, \sym
+    add \reg, \reg, #:lo12:\sym
+.endm
+
+.macro ADR_ABS reg, sym
+    movz \reg, #:abs_g3:\sym
+    movk \reg, #:abs_g2_nc:\sym
+    movk \reg, #:abs_g1_nc:\sym
+    movk \reg, #:abs_g0_nc:\sym
+.endm
+
+.set PTE_BLOCK_AF,      1 << 10
+.set PTE_BLOCK_ISH,     3 << 8
+.set PTE_PRESENT,       1 << 0
+
+.set MAIR_EL1_Attr0_Normal_Inner_NC,    (4 << 0)
+.set MAIR_EL1_Attr0_Normal_Outer_NC,    (4 << 4)
+.set MAIR_EL1_Attr1_Device,             (0 << 12)
+.set MAIR_EL1_Attr1_Device_nGnRE,       (1 << 8)
+
+.set ID_AA64MMFR0_EL1_TGran4,           (0xF << 28)
+
+.set TCR_EL1_IPS_SHIFT,                 32
+
+.set TCR_EL1_TG1_4K,                    (2 << 30)
+.set TCR_EL1_SH1_Outer,                 (2 << 28)
+.set TCR_EL1_ORGN1_NC,                  (0 << 26)
+.set TCR_EL1_IRGN1_NC,                  (0 << 24)
+.set TCR_EL1_T1SZ_SHIFT,                16
+
+.set TCR_EL1_TG0_4K,                    (0 << 14)
+.set TCR_EL1_SH0_Outer,                 (2 << 12)
+.set TCR_EL1_ORGN0_NC,                  (0 << 10)
+.set TCR_EL1_IRGN0_NC,                  (0 << 8)
+.set TCR_EL1_T0SZ_SHIFT,                0
+
+.set TCR_EL1_ATTRS,                     (TCR_EL1_TG1_4K | TCR_EL1_SH1_Outer | TCR_EL1_TG0_4K | TCR_EL1_SH0_Outer | (25 << TCR_EL1_T1SZ_SHIFT) | (25 << TCR_EL1_T0SZ_SHIFT))
+
+.set SCTLR_EL1_I,                       (1 << 12)
+.set SCTLR_EL1_C,                       (1 << 2)
+.set SCTLR_EL1_M,                       (1 << 0)
+
+
 .set SCTLR_EL2_RES1,        0x30C50830
 
 .set SPSR_EL2_EL1h,         0x5
@@ -61,6 +110,68 @@ _entry:
     ADR_ABS x9, __aa64_entry_upper
     b __aa64_enter_upper
 
+.global __aa64_enter_upper
+.type __aa64_enter_upper, %function
+__aa64_enter_upper:
+    // x8 -- FDT base
+    // x9 -- upper entry point
+
+    // Setup TTBR1_EL1
+    // TODO fix macros
+    ADR_ABS x5, KERNEL_TTBR1
+    ADR_ABS x6, KERNEL_OFFSET
+
+    // x5 = KERNEL_TTBR1 physical address
+    sub x5, x5, x6
+
+    // Fill KERNEL_TTBR1 table with upper-mapped Normal memory
+.fill_ttbr1:
+    mov x2, #256
+1:
+    sub x2, x2, #1
+
+    // x0 = (x2 << 30) | attrs...
+    lsl x1, x2, #30
+    mov x0, #(PTE_BLOCK_ISH | PTE_BLOCK_AF | PTE_PRESENT)
+    orr x0, x0, x1
+
+    str x0, [x5, x2, lsl #3]
+
+    cbnz x2, 1b
+
+.init_mmu_regs:
+    mov x0, #(MAIR_EL1_Attr0_Normal_Outer_NC | MAIR_EL1_Attr0_Normal_Inner_NC | MAIR_EL1_Attr1_Device | MAIR_EL1_Attr1_Device_nGnRE)
+    msr mair_el1, x0
+
+    // Test for 4KiB page support
+    mrs x0, ID_AA64MMFR0_EL1
+    mov x1, ID_AA64MMFR0_EL1_TGran4
+    tst x0, x1
+    bne .no_4k_gran
+
+    // x0 = PARange
+    and x0, x0, #0xF
+    lsl x0, x0, #TCR_EL1_IPS_SHIFT
+    MOV_L x1, TCR_EL1_ATTRS
+    orr x0, x0, x1
+    msr tcr_el1, x0
+
+    msr ttbr0_el1, x5
+    msr ttbr1_el1, x5
+
+    dsb ish
+    isb
+
+    mrs x0, sctlr_el1
+    orr x0, x0, #SCTLR_EL1_M
+    msr sctlr_el1, x0
+
+    mov x0, x8
+    br x9
+.no_4k_gran:
+    b .
+.size __aa64_enter_upper, . - __aa64_enter_upper
+
 .section .text._entry_upper
 __aa64_entry_upper:
     // x0 -- fdt address

kernel/src/arch/aarch64/boot/upper.S

@@ -1,95 +0,0 @@
-// vi:ft=a64asm:
-
-.set PTE_BLOCK_AF,      1 << 10
-.set PTE_BLOCK_ISH,     3 << 8
-.set PTE_PRESENT,       1 << 0
-
-.set MAIR_EL1_Attr0_Normal_Inner_NC,    (4 << 0)
-.set MAIR_EL1_Attr0_Normal_Outer_NC,    (4 << 4)
-.set MAIR_EL1_Attr1_Device,             (0 << 12)
-.set MAIR_EL1_Attr1_Device_nGnRE,       (1 << 8)
-
-.set ID_AA64MMFR0_EL1_TGran4,           (0xF << 28)
-
-.set TCR_EL1_IPS_SHIFT,                 32
-
-.set TCR_EL1_TG1_4K,                    (2 << 30)
-.set TCR_EL1_SH1_Outer,                 (2 << 28)
-.set TCR_EL1_ORGN1_NC,                  (0 << 26)
-.set TCR_EL1_IRGN1_NC,                  (0 << 24)
-.set TCR_EL1_T1SZ_SHIFT,                16
-
-.set TCR_EL1_TG0_4K,                    (0 << 14)
-.set TCR_EL1_SH0_Outer,                 (2 << 12)
-.set TCR_EL1_ORGN0_NC,                  (0 << 10)
-.set TCR_EL1_IRGN0_NC,                  (0 << 8)
-.set TCR_EL1_T0SZ_SHIFT,                0
-
-.set TCR_EL1_ATTRS,                     (TCR_EL1_TG1_4K | TCR_EL1_SH1_Outer | TCR_EL1_TG0_4K | TCR_EL1_SH0_Outer | (25 << TCR_EL1_T1SZ_SHIFT) | (25 << TCR_EL1_T0SZ_SHIFT))
-
-.set SCTLR_EL1_I,                       (1 << 12)
-.set SCTLR_EL1_C,                       (1 << 2)
-.set SCTLR_EL1_M,                       (1 << 0)
-
-.section .text._entry
-.global __aa64_enter_upper
-.type __aa64_enter_upper, %function
-__aa64_enter_upper:
-    // x8 -- FDT base
-    // x9 -- upper entry point
-
-    // Setup TTBR1_EL1
-    // TODO fix macros
-    ADR_ABS x5, KERNEL_TTBR1
-    ADR_ABS x6, KERNEL_OFFSET
-
-    // x5 = KERNEL_TTBR1 physical address
-    sub x5, x5, x6
-
-    // Fill KERNEL_TTBR1 table with upper-mapped Normal memory
-.fill_ttbr1:
-    mov x2, #256
-1:
-    sub x2, x2, #1
-
-    // x0 = (x2 << 30) | attrs...
-    lsl x1, x2, #30
-    mov x0, #(PTE_BLOCK_ISH | PTE_BLOCK_AF | PTE_PRESENT)
-    orr x0, x0, x1
-
-    str x0, [x5, x2, lsl #3]
-
-    cbnz x2, 1b
-
-.init_mmu_regs:
-    mov x0, #(MAIR_EL1_Attr0_Normal_Outer_NC | MAIR_EL1_Attr0_Normal_Inner_NC | MAIR_EL1_Attr1_Device | MAIR_EL1_Attr1_Device_nGnRE)
-    msr mair_el1, x0
-
-    // Test for 4KiB page support
-    mrs x0, ID_AA64MMFR0_EL1
-    mov x1, ID_AA64MMFR0_EL1_TGran4
-    tst x0, x1
-    bne .no_4k_gran
-
-    // x0 = PARange
-    and x0, x0, #0xF
-    lsl x0, x0, #TCR_EL1_IPS_SHIFT
-    MOV_L x1, TCR_EL1_ATTRS
-    orr x0, x0, x1
-    msr tcr_el1, x0
-
-    msr ttbr0_el1, x5
-    msr ttbr1_el1, x5
-
-    dsb ish
-    isb
-
-    mrs x0, sctlr_el1
-    orr x0, x0, #SCTLR_EL1_M
-    msr sctlr_el1, x0
-
-    mov x0, x8
-    br x9
-.no_4k_gran:
-    b .
-.size __aa64_enter_upper, . - __aa64_enter_upper

kernel/src/arch/aarch64/context.rs

@@ -6,6 +6,7 @@ use crate::mem::{
     phys::{self, PageUsage},
 };
 use core::mem::size_of;
+use core::arch::global_asm;
 
 struct Stack {
     bp: usize,

kernel/src/arch/aarch64/exception.rs

@@ -9,6 +9,7 @@ use crate::syscall;
 use cortex_a::registers::{ESR_EL1, FAR_EL1};
 use libsys::{abi::SystemCall, signal::Signal, error::Errno};
 use tock_registers::interfaces::Readable;
+use core::arch::global_asm;
 
 /// Trapped SIMD/FP functionality
 pub const EC_FP_TRAP: u64 = 0b000111;

kernel/src/arch/aarch64/mod.rs

@@ -2,6 +2,7 @@
 
 use cortex_a::registers::DAIF;
 use tock_registers::interfaces::{Readable, Writeable};
+use core::arch::asm;
 
 pub mod boot;
 pub mod context;

kernel/src/arch/aarch64/reg/cntkctl_el1.rs

@@ -1,6 +1,8 @@
 //! CNTKCTL_EL1 register
 #![allow(missing_docs)]
 
+use core::arch::asm;
+
 use tock_registers::{
     interfaces::{Readable, Writeable},
     register_bitfields,

kernel/src/arch/aarch64/reg/cpacr_el1.rs

@@ -1,6 +1,7 @@
 //! CPACR_EL1 register
 #![allow(missing_docs)]
 
+use core::arch::asm;
 use tock_registers::{
     interfaces::{Readable, Writeable},
     register_bitfields,

kernel/src/main.rs

@@ -1,19 +1,15 @@
 //! osdve5 crate (lol)
 #![feature(
-    asm,
-    global_asm,
     const_for,
     const_mut_refs,
-    const_raw_ptr_deref,
     const_fn_fn_ptr_basics,
     const_fn_trait_bound,
     const_trait_impl,
-    const_panic,
     panic_info_message,
     alloc_error_handler,
     linked_list_cursors,
     const_btree_new,
-    const_generics_defaults,
+    asm_const,
 )]
 #![no_std]
 #![no_main]
@@ -41,6 +37,8 @@ pub mod sync;
 pub mod syscall;
 pub mod util;
 
+use core::arch::asm;
+
 #[panic_handler]
 fn panic_handler(pi: &core::panic::PanicInfo) -> ! {
     unsafe {

kernel/src/mem/virt/table.rs

@@ -6,6 +6,7 @@ use crate::mem::{
 };
 use core::ops::{Index, IndexMut};
 use libsys::{error::Errno, mem::memset};
+use core::arch::asm;
 
 /// Transparent wrapper structure representing a single
 /// translation table entry

kernel/src/proc/process.rs

@@ -18,6 +18,7 @@ use libsys::{
     signal::Signal,
     ProgramArgs,
 };
+use core::arch::asm;
 
 /// Wrapper type for a process struct reference
 pub type ProcessRef = Rc<Process>;

kernel/src/proc/sched.rs

@@ -4,6 +4,7 @@ use crate::sync::IrqSafeSpinLock;
 use crate::util::InitOnce;
 use libsys::proc::Tid;
 use alloc::{collections::VecDeque, rc::Rc};
+use core::arch::asm;
 
 struct SchedulerInner {
     queue: VecDeque<Tid>,

kernel/src/syscall/arg.rs

@@ -4,6 +4,7 @@ use crate::mem;
 use core::alloc::Layout;
 use libsys::error::Errno;
 use crate::proc::Process;
+use core::arch::asm;
 
 // TODO _mut() versions checking whether pages are actually writable
 

libsys/src/calls.rs

@@ -1,4 +1,5 @@
 use crate::abi::SystemCall;
+use core::arch::asm;
 use crate::{
     debug::TraceLevel,
     error::Errno,

libsys/src/lib.rs

@@ -1,4 +1,3 @@
-#![feature(asm, const_panic)]
 #![no_std]
 
 #[macro_use]

libusr/src/lib.rs

@@ -1,4 +1,4 @@
-#![feature(asm, alloc_error_handler)]
+#![feature(alloc_error_handler)]
 #![no_std]
 
 #[macro_use]

libusr/src/thread.rs

@@ -8,6 +8,7 @@ use libsys::{
     calls::{sys_ex_clone, sys_ex_gettid, sys_ex_signal, sys_ex_thread_exit, sys_ex_thread_wait},
     proc::{ExitCode, Tid},
 };
+use core::arch::asm;
 
 struct NativeData<F, T>
 where

user/src/bin/fuzzy.rs

@@ -1,4 +1,3 @@
-#![feature(asm)]
 #![no_std]
 #![no_main]
 
@@ -9,6 +8,7 @@
 extern crate libusr;
 
 use libusr::sys::{abi::SystemCall, stat::Stat};
+use core::arch::asm;
 
 static mut STATE: u64 = 0;
 

user/src/init/main.rs

@@ -1,10 +1,11 @@
-#![feature(asm)]
 #![no_std]
 #![no_main]
 
 #[macro_use]
 extern crate libusr;
 
+use core::arch::asm;
+
 use libusr::sys::{stat::MountOptions, sys_execve, sys_fork, sys_mount, sys_waitpid};
 
 #[no_mangle]