fix: unify boot code

Makefile

@@ -26,7 +26,7 @@ $(error TODO)
 else
 ifeq ($(MACH),qemu)
 QEMU_OPTS+=-kernel $(O)/kernel \
-		   -M virt,virtualization=off \
+		   -M virt,virtualization=on \
 		   -cpu cortex-a72 \
 		   -m 512 \
 		   -serial chardev:serial0 \

etc/aarch64-qemu.ld

@@ -31,18 +31,14 @@ SECTIONS {
     }
 
     . = ALIGN(4K);
-    .tables : AT(. - KERNEL_OFFSET) {
+    PROVIDE(__bss_start_phys = . - KERNEL_OFFSET);
-        *(.tables)
+    PROVIDE(__bss_start = .);
-    }
-
-    . = ALIGN(4K);
     .bss : AT(. - KERNEL_OFFSET) {
-        PROVIDE(__bss_start = .);
         *(COMMON)
         *(.bss*)
         . = ALIGN(4K);
-        PROVIDE(__bss_end = .);
     }
+    PROVIDE(__bss_end_phys = . - KERNEL_OFFSET);
 
     PROVIDE(__kernel_end = .);
 }

kernel/src/arch/aarch64/boot/entry.S

@@ -13,7 +13,13 @@ _entry:
     b 1b
 
 2:
-    // TODO leave EL2 if running in it
+    mrs x0, currentel
+    cmp x0, #8
+    bne 1f
+
+    b .
+
+1:
 
     // TODO zero .bss
 

kernel/src/arch/aarch64/boot/mod.rs

@@ -4,8 +4,8 @@ use crate::arch::{aarch64::asm::CPACR_EL1, machine};
 use crate::dev::{Device, fdt::DeviceTree};
 use crate::mem::virt;
 use cortex_a::asm::barrier::{self, dsb, isb};
-use cortex_a::registers::{DAIF, SCTLR_EL1, VBAR_EL1, CurrentEL};
+use cortex_a::registers::{DAIF, SCTLR_EL1, VBAR_EL1};
-use tock_registers::interfaces::{ReadWriteable, Writeable, Readable};
+use tock_registers::interfaces::{ReadWriteable, Writeable};
 
 #[no_mangle]
 extern "C" fn __aa64_bsp_main(fdt_base: usize) {
@@ -57,13 +57,5 @@ extern "C" fn __aa64_bsp_main(fdt_base: usize) {
 }
 
 global_asm!(include_str!("macros.S"));
-
+global_asm!(include_str!("uboot.S"));
-cfg_if! {
-    if #[cfg(feature = "mach_orangepi3")] {
-        global_asm!(include_str!("uboot.S"));
-    } else {
-        global_asm!(include_str!("entry.S"));
-    }
-}
-
 global_asm!(include_str!("upper.S"));

kernel/src/arch/aarch64/boot/uboot.S

@@ -77,8 +77,3 @@ __aa64_entry_upper:
 bsp_stack_bottom:
     .skip 32768
 bsp_stack_top:
-
-.section .data
-.p2align 4
-fdt_base_phys:
-    .skip 8

kernel/src/arch/aarch64/exception.rs

@@ -67,7 +67,6 @@ extern "C" fn __aa64_exc_irq_handler() {
 
 #[no_mangle]
 extern "C" fn __aa64_exc_sync_handler(exc: &mut ExceptionFrame) {
-    loop {}
     let err_code = exc.esr >> 26;
     let iss = exc.esr & 0x1FFFFFF;
 

kernel/src/arch/aarch64/irq/gic/mod.rs

@@ -57,8 +57,8 @@ impl Device for Gic {
         let gicd_mmio_banked = DeviceMemoryIo::new(gicd_mmio);
         let gicc_mmio = DeviceMemoryIo::map("GICv2 CPU registers", self.gicc_base, 1)?;
 
-        let mut gicd = Gicd::new(gicd_mmio_shared, gicd_mmio_banked);
+        let gicd = Gicd::new(gicd_mmio_shared, gicd_mmio_banked);
-        let mut gicc = Gicc::new(gicc_mmio);
+        let gicc = Gicc::new(gicc_mmio);
 
         gicd.enable();
         gicc.enable();

kernel/src/dev/fdt.rs

@@ -14,6 +14,7 @@ static mut INDEX_BUFFER: Wrap = Wrap { data: [0; 65536] };
 
 type INode<'a> = DevTreeIndexNode<'a, 'a, 'a>;
 
+#[allow(dead_code)]
 pub struct DeviceTree {
     tree: DevTree<'static>,
     index: DevTreeIndex<'static, 'static>,

kernel/src/dev/rtc/pl031.rs

@@ -80,7 +80,7 @@ impl Device for Pl031 {
     }
 
     unsafe fn enable(&self) -> Result<(), Errno> {
-        let mut inner = Pl031Inner {
+        let inner = Pl031Inner {
             regs: DeviceMemoryIo::map(self.name(), self.base, 1)?,
         };