63 lines
1.5 KiB
Rust
63 lines
1.5 KiB
Rust
//! aarch64 common boot logic
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use crate::arch::{aarch64::asm::CPACR_EL1, machine};
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use crate::dev::{Device, fdt::DeviceTree};
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use crate::mem::virt;
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use cortex_a::asm::barrier::{self, dsb, isb};
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use cortex_a::registers::{DAIF, SCTLR_EL1, VBAR_EL1, CurrentEL};
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use tock_registers::interfaces::{ReadWriteable, Writeable, Readable};
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#[no_mangle]
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fn __aa64_bsp_main(fdt_base: usize) {
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// Disable FP instruction trapping
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CPACR_EL1.modify(CPACR_EL1::FPEN::TrapNone);
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extern "C" {
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static aa64_el1_vectors: u8;
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}
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unsafe {
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VBAR_EL1.set(&aa64_el1_vectors as *const _ as u64);
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// Setup caching in SCTLR_EL1
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dsb(barrier::SY);
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isb(barrier::SY);
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SCTLR_EL1
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.modify(SCTLR_EL1::I::SET + SCTLR_EL1::SA::SET + SCTLR_EL1::C::SET + SCTLR_EL1::A::SET);
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dsb(barrier::SY);
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isb(barrier::SY);
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}
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// Enable MMU
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virt::enable().expect("Failed to initialize virtual memory");
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machine::init_board().unwrap();
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// let fdt = DeviceTree::from_phys(fdt_base + 0xFFFFFF8000000000).expect("Failed to obtain a device tree");
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// fdt.dump();
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debugln!("Machine init finished");
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unsafe {
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machine::local_timer().enable().unwrap();
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}
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loop {
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DAIF.modify(DAIF::I::CLEAR);
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cortex_a::asm::wfi();
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}
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}
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global_asm!(include_str!("macros.S"));
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cfg_if! {
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if #[cfg(feature = "mach_orangepi3")] {
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global_asm!(include_str!("uboot.S"));
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} else {
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global_asm!(include_str!("entry.S"));
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}
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}
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global_asm!(include_str!("upper.S"));
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