From 71ec54c8d38097c93746d9102a97df4eb695967f Mon Sep 17 00:00:00 2001
From: Mark Poliakov <mark@alnyan.me>
Date: Fri, 5 Sep 2025 09:00:58 +0300
Subject: [PATCH] Zicsr: implement immediate operand instructions

---
 src/core/rvx0_core.sv  |  1 +
 src/core/rvx0_zicsr.sv | 31 +++++++++++++++++++++++++++----
 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/src/core/rvx0_core.sv b/src/core/rvx0_core.sv
index 4e16f9f..7eaa639 100644
--- a/src/core/rvx0_core.sv
+++ b/src/core/rvx0_core.sv
@@ -268,6 +268,7 @@ module rvx0_core #(
         .funct3_i                   (funct3),
         .rs1_value_i                (rs1_value),
         .rd_i                       (rd),
+        .rs1_i                      (rs1),
         .imm_i                      (imm),
 
         .exec_ready_o               (zicsr_exec_ready),
diff --git a/src/core/rvx0_zicsr.sv b/src/core/rvx0_zicsr.sv
index c060d26..9eb8ac1 100644
--- a/src/core/rvx0_zicsr.sv
+++ b/src/core/rvx0_zicsr.sv
@@ -5,6 +5,7 @@ module rvx0_zicsr (
     input wire [2:0]    funct3_i,
     input wire [31:0]   rs1_value_i,
     input wire [4:0]    rd_i,
+    input wire [4:0]    rs1_i,
     input wire [31:0]   imm_i,
     input wire [31:0]   csr_value_i,
     input wire          undefined_csr_i,
@@ -18,9 +19,11 @@ module rvx0_zicsr (
     output logic [31:0] csr_read_output_o,
     output logic [31:0] csr_write_output_o,
     output logic [11:0] csr_index_o,
-    output logic        csr_write_o,
-    output logic        csr_clk_o
+    output logic        csr_write_o
 );
+    wire [31:0]     uimm;
+    wire            value2_immediate;
+
     logic           need_csr_read;
     logic           need_csr_write;
     logic           single_cycle;
@@ -36,20 +39,25 @@ module rvx0_zicsr (
 
     assign csr_index_o = imm_i[11:0];
 
+    assign value2_immediate = funct3_i[2] == 1;
+
+    assign uimm = { 27'b0, rs1_i };
+
     assign csrrs_output = value1 | value2;
     assign csrrc_output = value1 & ~value2;
 
     assign exec_ready_o = single_cycle || latch_state == 2;
     assign csr_write_o = single_cycle ? need_csr_write : latch_state == 2;
-    assign regfile_clk_o = single_cycle ? need_csr_read : latch_state == 2;
+    assign regfile_clk_o = (single_cycle || value2_immediate) ? need_csr_read : latch_state == 2;
 
     assign value1 = single_cycle ? csr_value_i : csr_value_latch;
-    assign value2 = single_cycle ? rs1_value_i : rs1_value_latch;
+    assign value2 = value2_immediate ? uimm : (single_cycle ? rs1_value_i : rs1_value_latch);
     assign csr_read_output_o = single_cycle ? csr_value_i : csr_value_latch;
 
     always_comb begin
         instruction_fault_o = undefined_csr_i;
         need_csr_read = 0;
+        need_csr_write = 0;
         single_cycle = 0;
 
         csr_write_output_o = 0;
@@ -70,6 +78,21 @@ module rvx0_zicsr (
             need_csr_write = rs1_value_i != 0;
             csr_write_output_o = csrrc_output;
         end
+        3'b101: begin // csrrwi
+            need_csr_read = rd_i != 0;
+            need_csr_write = 1;
+            csr_write_output_o = uimm;
+        end
+        3'b110: begin // csrrsi
+            need_csr_read = 1;
+            need_csr_write = uimm != 0;
+            csr_write_output_o = csrrs_output;
+        end
+        3'b111: begin
+            need_csr_read = 1;
+            need_csr_write = uimm != 0;
+            csr_write_output_o = csrrc_output;
+        end
         // TODO csrrwi, csrrsi, csrrci
         default: instruction_fault_o = 1;
         endcase