/* verilator lint_off UNOPTFLAT */

interface rvx0_apb ();
    logic pclk;
    logic prstn;
    logic [31:0] paddr;
    logic pwrite;
    logic penable;
    logic [31:0] pwdata;
    logic psel;

    logic pready;
    logic [31:0] prdata;
    logic pslverr;

    modport master (
        input pready, prdata, pslverr,
        output pclk, prstn, paddr, penable, pwrite, pwdata
    );

    modport slave (
        input pclk, prstn, paddr, pwrite, penable, pwdata, psel,
        output pready, prdata, pslverr
    );
endinterface