// TODO Zicsr
module rvx0_csr (
    input wire clk_i,
    input wire rst_i,

    input wire [31:0]   mepc_i,
    input wire [31:0]   mcause_i,
    input wire [31:0]   mtval_i,

    input wire          mepc_write_i,
    input wire          mcause_write_i,
    input wire          mtval_write_i,

    output wire [31:0]  misa_o,         // Hardwired
    output wire [31:0]  mvendorid_o,    // Hardwired
    output wire [31:0]  marchid_o,      // Hardwired
    output wire [31:0]  mimpid_o,       // Hardwired
    output wire [31:0]  mhartid_o,      // Hardwired
    output reg [31:0]   mstatus_o,      // TODO
    output reg [31:0]   mstatush_o,     // TODO
    output reg [31:0]   mtvec_o,
    output reg [31:0]   mepc_o,
    output reg [31:0]   mcause_o,
    output reg [31:0]   mtval_o         // TODO
);
    // Add extensions here :)
    assign misa_o       = MISA_MXLEN_32;
    assign mvendorid_o  = 0;
    assign marchid_o    = 0;
    assign mimpid_o     = 0;
    assign mhartid_o    = 0;

    always @(posedge clk_i) begin
        if (rst_i) begin
            // TODO set from CPU
            mtvec_o = 'h00020000;
            mepc_o = 0;
            mstatus_o = 0;
            mstatush_o = 0;
        end

        if (mepc_write_i) begin
            mepc_o <= mepc_i;
        end
        if (mcause_write_i) begin
            mcause_o <= mcause_i;
        end
        if (mtval_write_i) begin
            mtval_o <= mtval_i;
        end
    end
endmodule