/dts-v1/;

/ {
	#address-cells = <0x02>;
	model = "StarFive VisionFive 2 v1.3B";
	serial-number = "VF7110B1-2318-D008E000-18003903";
	#size-cells = <0x02>;
	compatible = "starfive,visionfive-2-v1.3b\0starfive,jh7110";

	dsi-output {
		compatible = "starfive,jh7110-display-encoder\0verisilicon,dsi-encoder";
		status = "okay";
		phandle = <0x6a>;

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				reg = <0x00>;

				endpoint {
					remote-endpoint = <0x0b>;
					phandle = <0x52>;
				};
			};

			port@1 {
				reg = <0x01>;

				endpoint {
					remote-endpoint = <0x0c>;
					phandle = <0x5a>;
				};
			};
		};
	};

	&clk_osc: oscillator {
		clock-output-names = "osc";
		#clock-cells = <0x00>;
		clock-frequency = <0x16e3600>;
		compatible = "fixed-clock";
		phandle = <0x29>;
	};

	i2stx-lrck-ext-clock {
		clock-output-names = "i2stx_lrck_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0x2ee00>;
		compatible = "fixed-clock";
		phandle = <0x32>;
	};

	stmmac-axi-config {
		snps,lpi_en;
		snps,wr_osr_lmt = <0x0f>;
		phandle = <0x3f>;
		snps,blen = <0x100 0x80 0x40 0x20 0x00 0x00 0x00>;
		snps,rd_osr_lmt = <0x0f>;
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x00 0x40000000 0x02 0x00>;
	};

	gmac1-rmii-refin-clock {
		clock-output-names = "gmac1_rmii_refin";
		#clock-cells = <0x00>;
		clock-frequency = <0x2faf080>;
		compatible = "fixed-clock";
		phandle = <0x35>;
	};

	display-subsystem {
		ports = <0x0a>;
		compatible = "starfive,jh7110-display\0verisilicon,display-subsystem";
		status = "okay";
		phandle = <0x69>;
	};

	rgb-output {
		compatible = "starfive,jh7110-rgb_output\0verisilicon,rgb-encoder";
		status = "disabled";
		phandle = <0x6c>;

		ports {
			#address-cells = <0x01>;
			#size-cells = <0x00>;

			port@0 {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				reg = <0x00>;

				endpoint@0 {
					remote-endpoint = <0x0a>;
					reg = <0x00>;
					phandle = <0x50>;
				};
			};
		};
	};

	rtc-oscillator {
		clock-output-names = "rtc_osc";
		#clock-cells = <0x00>;
		clock-frequency = <0x8000>;
		compatible = "fixed-clock";
		phandle = <0x45>;
	};

	snd-card3 {
		simple-audio-card,name = "Starfive-PWMDAC-Sound-Card";
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		compatible = "simple-audio-card";
		phandle = <0xac>;

		simple-audio-card,dai-link@0 {
			format = "left_j";
			frame-master = <0x63>;
			bitclock-master = <0x63>;
			reg = <0x00>;

			cpu {
				phandle = <0x63>;
				sound-dai = <0x64>;
			};

			codec {
				sound-dai = <0x65>;
			};
		};
	};

	thermal-zones {

		cpu-thermal {
			polling-delay = <0x3a98>;
			polling-delay-passive = <0xfa>;
			thermal-sensors = <0x0e>;

			trips {

				cpu_crit {
					temperature = <0x186a0>;
					hysteresis = <0x7d0>;
					type = "critical";
				};

				cpu_alert0 {
					temperature = <0x14c08>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x0f>;
				};
			};

			cooling-maps {

				map0 {
					trip = <0x0f>;
					cooling-device = <0x06 0xffffffff 0xffffffff 0x07 0xffffffff 0xffffffff 0x08 0xffffffff 0xffffffff 0x09 0xffffffff 0xffffffff>;
				};
			};
		};
	};

	gmac1-rgmii-rxin-clock {
		clock-output-names = "gmac1_rgmii_rxin";
		#clock-cells = <0x00>;
		clock-frequency = <0x7735940>;
		compatible = "fixed-clock";
		phandle = <0x36>;
	};

	soc {
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		interrupt-parent = <0x10>;
		compatible = "simple-bus";
		ranges;

		e24@6e210000 {
			#address-cells = <0x01>;
			dma-coherent;
			clock-names = "clk_rtc\0clk_core\0clk_dbg";
			reg-names = "ecmd\0espace";
			irq-mode = <0x01>;
			firmware-name = "e24_elf";
			starfive,stg-syscon = <0x26>;
			resets = <0x27 0x04>;
			memory-region = <0x5b>;
			clocks = <0x27 0x18 0x27 0x19 0x27 0x1a>;
			#size-cells = <0x01>;
			interrupt-parent = <0x10>;
			compatible = "starfive,e24";
			ranges = <0x6ce00000 0x00 0x6ce00000 0x1600000>;
			status = "okay";
			reg = <0x00 0x6e210000 0x00 0x1000 0x00 0x6e211000 0x00 0x3f000>;
			phandle = <0xa8>;
			mboxes = <0x0d 0x00 0x02 0x0d 0x02 0x00>;
			reset-names = "e24_core";
			mbox-names = "tx\0rx";

			dsp@0 {
			};
		};

		spi@12070000 {
			arm,primecell-periphid = <0x41022>;
			#address-cells = <0x01>;
			num-cs = <0x01>;
			clock-names = "sspclk\0apb_pclk";
			resets = <0x03 0x48>;
			interrupts = <0x34>;
			clocks = <0x03 0x86 0x03 0x86>;
			#size-cells = <0x00>;
			compatible = "arm,pl022\0arm,primecell";
			status = "disabled";
			reg = <0x00 0x12070000 0x00 0x10000>;
			phandle = <0x8d>;
		};

		phy@10220000 {
			#phy-cells = <0x00>;
			compatible = "starfive,jh7110-pcie-phy";
			reg = <0x00 0x10220000 0x00 0x10000>;
			phandle = <0x60>;
		};

		hdmi@29590000 {
			pinctrl-names = "default";
			hdmi_0p9-supply = <0x54>;
			pinctrl-0 = <0x53>;
			clock-names = "sysclk\0mclk\0bclk\0pclk";
			hdmi_1p8-supply = <0x55>;
			resets = <0x4e 0x09>;
			interrupts = <0x63>;
			clocks = <0x4e 0x11 0x4e 0x0f 0x4e 0x10 0x4f>;
			hpd-gpio = <0x1a 0x0f 0x00>;
			#sound-dai-cells = <0x00>;
			compatible = "starfive,jh7110-hdmi\0inno,hdmi";
			status = "okay";
			reg = <0x00 0x29590000 0x00 0x4000>;
			phandle = <0x68>;
			reset-names = "hdmi_tx";

			port {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				phandle = <0xa6>;

				endpoint@0 {
					remote-endpoint = <0x56>;
					reg = <0x00>;
					phandle = <0x51>;
				};
			};
		};

        /* Verisilicon DC8200 Display Controller */
		&dc8200: dc8200@29400000 {
			verisilicon,dss-syscon = <0x4d>;
			compatible = "starfive,jh7110-dc8200", "verisilicon,dc8200";
			clock-names =
                "noc_disp",
                "vout_src",
                "top_vout_axi",
                "top_vout_ahb",
                "pix_clk",
                "vout_pix1",
                "axi_clk",
                "core_clk",
                "vout_ahb",
                "vout_top_axi",
                "vout_top_lcd",
                "hdmitx0_pixelclk",
                "dc8200_pix0";
			clocks = <
                &syscrg     0x3c    /* NOC DISP */
                &syscrg     0x3a    /* VOUT SRC */
                &syscrg     0x3e    /* TOP VOUT AXI */
                &syscrg     0x3d    /* TOP VOUT AHB */
                &voutcrg    0x07    /* PIX CLK */
                &voutcrg    0x08    /* VOUT PIX1 */
                &voutcrg    0x04    /* AXI CLK */
                &voutcrg    0x05    /* CORE CLK */
                &voutcrg    0x06    /* VOUT AHB */
                &syscrg     0x3e    /* VOUT TOP AXI */
                &voutcrg    0x09    /* VOUT TOP LCD */
                &hdmitx0_pixelclk   /* HDMITX0 PIXELCLK */ /* Fixed @ 297MHz */
                &voutcrg    0x01    /* DC8200 PIX0 */
            >;
			reset-names =
                "rst_vout_src",
                "rst_axi",
                "rst_ahb",
                "rst_core",
                "rst_noc_disp";
			resets = <
                &syscrg     0x2b    /* rst_vout_src */
                &voutcrg    0x00    /* rst_axi */
                &voutcrg    0x01    /* rst_ahb */
                &voutcrg    0x02    /* rst_core */
                &syscrg     0x1a    /* rst_noc_disp */
            >;
			interrupts = <0x5f>;
			status = "okay";
			reg =
                <0x00 0x29400000 0x00 0x100>,
                <0x00 0x29400800 0x00 0x2000>,
                <0x00 0x17030000 0x00 0x1000>;
			// phandle = <0xa4>;

			port {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				phandle = <0xa5>;

				endpoint@1 {
					remote-endpoint = <0x51>;
					reg = <0x01>;
					phandle = <0x56>;
				};

				endpoint@2 {
					remote-endpoint = <0x52>;
					reg = <0x02>;
					phandle = <0x0b>;
				};

				endpoint@0 {
					remote-endpoint = <0x50>;
					reg = <0x00>;
					phandle = <0x0a>;
				};
			};
		};

		spdif@100a0000 {
			clock-names = "apb\0core\0audroot\0mclk_inner\0mclk_ext\0mclk";
			resets = <0x03 0x5f>;
			interrupts = <0x54>;
			clocks = <0x03 0x9f 0x03 0xa0 0x03 0x10 0x03 0x11 0x20 0x03 0x12>;
			#sound-dai-cells = <0x00>;
			compatible = "starfive,jh7110-spdif";
			status = "disabled";
			interrupt-names = "tx";
			reg = <0x00 0x100a0000 0x00 0x1000>;
			phandle = <0x7b>;
			reset-names = "apb";
		};

		serial@10020000 {
			reg-io-width = <0x04>;
			clock-names = "baudclk\0apb_pclk";
			resets = <0x03 0x57 0x03 0x58>;
			interrupts = <0x22>;
			clocks = <0x03 0x96 0x03 0x95>;
			compatible = "snps,dw-apb-uart";
			status = "disabled";
			reg = <0x00 0x10020000 0x00 0x10000>;
			phandle = <0x71>;
			reg-shift = <0x02>;
		};

		vin_sysctl@19800000 {
			power-domains = <0x38 0x05>;
			mipi_0p9-supply = <0x48>;
			clock-names = "clk_apb_func\0clk_pclk\0clk_sys_clk\0clk_wrapper_clk_c\0clk_dvp_inv\0clk_axiwr\0clk_mipi_rx0_pxl\0clk_pixel_clk_if0\0clk_pixel_clk_if1\0clk_pixel_clk_if2\0clk_pixel_clk_if3\0clk_m31dphy_cfgclk_in\0clk_m31dphy_refclk_in\0clk_m31dphy_txclkesc_lan0\0clk_ispcore_2x\0clk_isp_axi";
			reg-names = "csi2rx\0vclk\0vrst\0sctrl\0isp\0trst\0pmu\0syscrg";
			resets = <0x46 0x00 0x46 0x01 0x46 0x04 0x46 0x09 0x46 0x0a 0x46 0x0b 0x46 0x05 0x46 0x06 0x46 0x07 0x46 0x08 0x46 0x02 0x46 0x03 0x03 0x29 0x03 0x2a>;
			interrupts = <0x5c 0x57 0x58 0x59 0x5a>;
			clocks = <0x46 0x00 0x46 0x06 0x46 0x07 0x46 0x0d 0x46 0x02 0x46 0x0c 0x46 0x01 0x46 0x08 0x46 0x09 0x46 0x0a 0x46 0x0b 0x46 0x03 0x46 0x04 0x46 0x05 0x03 0x33 0x03 0x34>;
			starfive,aon-syscon = <0x40 0x00>;
			compatible = "starfive,jh7110-vin";
			status = "okay";
			reg = <0x00 0x19800000 0x00 0x10000 0x00 0x19810000 0x00 0x10000 0x00 0x19820000 0x00 0x10000 0x00 0x19840000 0x00 0x10000 0x00 0x19870000 0x00 0x30000 0x00 0x11840000 0x00 0x10000 0x00 0x17030000 0x00 0x10000 0x00 0x13020000 0x00 0x10000>;
			phandle = <0xa3>;
			reset-names = "rst_wrapper_p\0rst_wrapper_c\0rst_pclk\0rst_sys_clk\0rst_axird\0rst_axiwr\0rst_pixel_clk_if0\0rst_pixel_clk_if1\0rst_pixel_clk_if2\0rst_pixel_clk_if3\0rst_m31dphy_hw\0rst_m31dphy_b09_always_on\0rst_isp_top_n\0rst_isp_top_axi";

			ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				port@1 {
					#address-cells = <0x01>;
					#size-cells = <0x00>;
					reg = <0x01>;

					endpoint@1 {
						data-lanes = <0x00 0x01>;
						clock-lanes = <0x04>;
						remote-endpoint = <0x4a>;
						bus-type = <0x04>;
						status = "okay";
						lane-polarities = <0x00 0x00 0x00>;
						reg = <0x01>;
						phandle = <0x2e>;
					};

					endpoint@2 {
						data-lanes = <0x00 0x01>;
						clock-lanes = <0x04>;
						remote-endpoint = <0x4b>;
						bus-type = <0x04>;
						status = "okay";
						reg = <0x02>;
						phandle = <0x2f>;
					};

					endpoint@0 {
						data-lanes = <0x00 0x01>;
						clock-lanes = <0x04>;
						remote-endpoint = <0x49>;
						bus-type = <0x04>;
						status = "okay";
						lane-polarities = <0x00 0x00 0x00>;
						reg = <0x00>;
						phandle = <0x2d>;
					};
				};
			};
		};

		syscon@13030000 {
			compatible = "starfive,jh7110-sys-syscon\0syscon\0simple-mfd";
			reg = <0x00 0x13030000 0x00 0x1000>;
			phandle = <0x22>;

			clock-controller {
				clocks = <0x29>;
				#clock-cells = <0x01>;
				compatible = "starfive,jh7110-pll";
				phandle = <0x37>;
			};
		};

		i2c@10050000 {
			pinctrl-names = "default";
			#address-cells = <0x01>;
			i2c-sda-hold-time-ns = <0x12c>;
			pinctrl-0 = <0x18>;
			clock-names = "ref";
			i2c-scl-falling-time-ns = <0x1fe>;
			i2c-sda-falling-time-ns = <0x1fe>;
			resets = <0x03 0x4e>;
			interrupts = <0x25>;
			clocks = <0x03 0x8c>;
			#size-cells = <0x00>;
			clock-frequency = <0x186a0>;
			compatible = "snps,designware-i2c";
			status = "okay";
			reg = <0x00 0x10050000 0x00 0x10000>;
			phandle = <0x74>;

			tinker_ft5406@38 {
				compatible = "tinker_ft5406";
				reg = <0x38>;
				phandle = <0x75>;
			};

			touchscreen@14 {
				irq-gpios = <0x1a 0x1e 0x00>;
				reset-gpios = <0x1a 0x1f 0x00>;
				compatible = "goodix,gt911";
				reg = <0x14>;
			};

			panel_radxa@19 {
				enable-gpio = <0x1a 0x16 0x00>;
				reset-gpio = <0x1a 0x17 0x00>;
				compatible = "starfive_jadard";
				reg = <0x19>;

				port {

					endpoint {
						remote-endpoint = <0x1b>;
						phandle = <0x59>;
					};
				};
			};

			seeed_plane_i2c@45 {
				compatible = "seeed_panel";
				reg = <0x45>;

				port {

					endpoint {
						remote-endpoint = <0x19>;
						phandle = <0x58>;
					};
				};
			};
		};

		serial@12000000 {
			reg-io-width = <0x04>;
			clock-names = "baudclk\0apb_pclk";
			resets = <0x03 0x59 0x03 0x5a>;
			interrupts = <0x2d>;
			clocks = <0x03 0x98 0x03 0x97>;
			compatible = "snps,dw-apb-uart";
			status = "disabled";
			reg = <0x00 0x12000000 0x00 0x10000>;
			phandle = <0x82>;
			reg-shift = <0x02>;
		};

		csi-bridge@19800000 {
			phy-names = "dphy";
			clock-names = "sys_clk\0p_clk\0pixel_if0_clk\0pixel_if1_clk\0pixel_if2_clk\0pixel_if3_clk";
			resets = <0x46 0x09 0x46 0x04 0x46 0x05 0x46 0x06 0x46 0x07 0x46 0x08>;
			clocks = <0x46 0x07 0x46 0x06 0x46 0x08 0x46 0x09 0x46 0x0a 0x46 0x0b>;
			compatible = "starfive,jh7110-csi2rx";
			status = "disabled";
			phys = <0x47>;
			reg = <0x00 0x19800000 0x00 0x10000>;
			phandle = <0xa2>;
			reset-names = "sys\0reg_bank\0pixel_if0\0pixel_if1\0pixel_if2\0pixel_if3";
		};

		jpu@13090000 {
			power-domains = <0x38 0x03>;
			dma-coherent;
			clock-names = "axi_clk\0core_clk\0apb_clk\0noc_bus\0main_clk\0dec_clk";
			resets = <0x03 0x2c 0x03 0x2d 0x03 0x2e>;
			interrupts = <0x0e>;
			clocks = <0x03 0x42 0x03 0x43 0x03 0x44 0x03 0x4c 0x03 0x4b 0x03 0x4a>;
			compatible = "starfive,jpu";
			status = "okay";
			reg = <0x00 0x13090000 0x00 0x300>;
			phandle = <0x95>;
			reset-names = "rst_axi\0rst_core\0rst_apb";
		};

		dma-controller@16008000 {
			memcpy-bus-width = <0x20>;
			arm,primecell-periphid = <0x41080>;
			lli-bus-interface-ahb1;
			clock-names = "apb_pclk";
			resets = <0x27 0x03>;
			interrupts = <0x1d>;
			clocks = <0x27 0x0f>;
			memcpy-burst-size = <0x100>;
			compatible = "arm,pl080\0arm,primecell";
			mem-bus-interface-ahb1;
			reg = <0x00 0x16008000 0x00 0x4000>;
			phandle = <0x39>;
			#dma-cells = <0x02>;
		};

		i2c@12030000 {
			#address-cells = <0x01>;
			clock-names = "ref";
			resets = <0x03 0x4f>;
			interrupts = <0x30>;
			clocks = <0x03 0x8d>;
			#size-cells = <0x00>;
			compatible = "snps,designware-i2c";
			status = "disabled";
			reg = <0x00 0x12030000 0x00 0x10000>;
			phandle = <0x85>;
		};

		dma-controller@16050000 {
			snps,data-width = <0x03>;
			snps,priority = <0x00 0x01 0x02 0x03>;
			clock-names = "core-clk\0cfgr-clk";
			resets = <0x27 0x05 0x27 0x06>;
			interrupts = <0x49>;
			clocks = <0x27 0x1b 0x27 0x1c>;
			snps,axi-max-burst-len = <0x10>;
			snps,dma-masters = <0x01>;
			compatible = "starfive,jh7110-axi-dma";
			snps,block-size = <0x10000 0x10000 0x10000 0x10000>;
			reg = <0x00 0x16050000 0x00 0x10000>;
			phandle = <0x1e>;
			dma-channels = <0x04>;
			#dma-cells = <0x01>;
		};

		pwm@120d0000 {
			pinctrl-names = "default";
			pinctrl-0 = <0x34>;
			resets = <0x03 0x6c>;
			clocks = <0x03 0x79>;
			#pwm-cells = <0x03>;
			compatible = "starfive,jh7110-pwm\0opencores,pwm-v1";
			status = "okay";
			reg = <0x00 0x120d0000 0x00 0x10000>;
			phandle = <0x92>;
		};

		syscon@10240000 {
			compatible = "starfive,jh7110-stg-syscon\0syscon";
			reg = <0x00 0x10240000 0x00 0x1000>;
			phandle = <0x26>;
		};

		timer@13050000 {
			clock-names = "apb\0ch0\0ch1\0ch2\0ch3";
			resets = <0x03 0x75 0x03 0x76 0x03 0x77 0x03 0x78 0x03 0x79>;
			interrupts = <0x45 0x46 0x47 0x48>;
			clocks = <0x03 0x7c 0x03 0x7d 0x03 0x7e 0x03 0x7f 0x03 0x80>;
			compatible = "starfive,jh7110-timer";
			reg = <0x00 0x13050000 0x00 0x10000>;
			reset-names = "apb\0ch0\0ch1\0ch2\0ch3";
		};

		spi@10060000 {
			arm,primecell-periphid = <0x41022>;
			pinctrl-names = "default";
			#address-cells = <0x01>;
			num-cs = <0x01>;
			pinctrl-0 = <0x1c>;
			clock-names = "sspclk\0apb_pclk";
			resets = <0x03 0x45>;
			interrupts = <0x26>;
			clocks = <0x03 0x83 0x03 0x83>;
			#size-cells = <0x00>;
			compatible = "arm,pl022\0arm,primecell";
			status = "okay";
			reg = <0x00 0x10060000 0x00 0x10000>;
			phandle = <0x76>;

			spi@0 {
				spi-max-frequency = <0x989680>;
				compatible = "rohm,dh2228fv";
				reg = <0x00>;
				phandle = <0x77>;
			};
		};

		pdm@100d0000 {
			clock-names = "pdm_mclk\0pdm_apb\0clk_mclk\0mclk_ext";
			reg-names = "pdm";
			resets = <0x03 0x61 0x03 0x62>;
			clocks = <0x03 0xb6 0x03 0xb7 0x03 0x12 0x20>;
			#sound-dai-cells = <0x00>;
			compatible = "starfive,jh7110-pdm";
			status = "disabled";
			reg = <0x00 0x100d0000 0x00 0x1000>;
			phandle = <0x7c>;
			reset-names = "pdm_dmic\0pdm_apb";
		};

		pwmdac@100b0000 {
			pinctrl-names = "default";
			pinctrl-0 = <0x21>;
			clock-names = "apb\0core";
			resets = <0x03 0x60>;
			clocks = <0x03 0x9d 0x03 0x9e>;
			dma-names = "tx";
			#sound-dai-cells = <0x00>;
			compatible = "starfive,jh7110-pwmdac";
			status = "okay";
			reg = <0x00 0x100b0000 0x00 0x1000>;
			phandle = <0x64>;
			dmas = <0x1e 0x16>;
		};

		can@130d0000 {
			syscon,can_or_canfd = <0x00>;
			clock-names = "apb_clk\0core_clk\0timer_clk";
			starfive,sys-syscon = <0x22 0x10 0x03 0x08>;
			resets = <0x03 0x6f 0x03 0x70 0x03 0x71>;
			interrupts = <0x70>;
			clocks = <0x03 0x73 0x03 0x75 0x03 0x74>;
			compatible = "starfive,jh7110-can\0ipms,can";
			status = "disabled";
			frequency = <0x2625a00>;
			reg = <0x00 0x130d0000 0x00 0x1000>;
			phandle = <0x98>;
			reset-names = "rst_apb\0rst_core\0rst_timer";
		};

		pinctrl@13040000 {
			gpio-controller;
			resets = <0x03 0x02>;
			interrupts = <0x56>;
			clocks = <0x03 0x70>;
			compatible = "starfive,jh7110-sys-pinctrl";
			#interrupt-cells = <0x02>;
			reg = <0x00 0x13040000 0x00 0x10000>;
			phandle = <0x1a>;
			#gpio-cells = <0x02>;
			interrupt-controller;

			&pinctrl_mmc1_0: mmc1-0 {
				phandle = <0x3d>;

				clk-pins {
					input-schmitt-disable;
					input-disable;
					drive-strength = <0x0c>;
					pinmux = <0xff37000a>;
					slew-rate = <0x00>;
					bias-pull-up;
				};

				mmc-pins {
					drive-strength = <0x0c>;
					pinmux = <0x2c394c09 0x2d3a500b 0x2e3b540c 0x2f3c5807 0x303d5c08>;
					input-schmitt-enable;
					slew-rate = <0x00>;
					bias-pull-up;
					input-enable;
				};
			};

			i2c2-0 {
				phandle = <0x18>;

				i2c-pins {
					bias-disable;
					pinmux = <0x3b007803 0x3c007c02>;
					input-schmitt-enable;
					input-enable;
				};
			};

			i2c5-0 {
				phandle = <0x2a>;

				i2c-pins {
					bias-disable;
					pinmux = <0x4f00a813 0x5000ac14>;
					input-schmitt-enable;
					input-enable;
				};
			};

			spi0-0 {
				phandle = <0x1c>;

				miso-pins {
					pinmux = <0x1c000435>;
					input-schmitt-enable;
					bias-pull-up;
					input-enable;
				};

				mosi-pins {
					input-schmitt-disable;
					input-disable;
					bias-disable;
					pinmux = <0xff200034>;
				};

				ss-pins {
					input-schmitt-disable;
					input-disable;
					bias-disable;
					pinmux = <0x1b1f0031>;
				};

				sck-pins {
					input-schmitt-disable;
					input-disable;
					bias-disable;
					pinmux = <0x1a1e0030>;
				};
			};

			&pinctrl_mmc0_0: mmc0-0 {
				phandle = <0x3a>;

				mmc-pins {
					drive-strength = <0x0c>;
					pinmux = <0x440 0x441 0x442 0x443 0x444 0x445 0x446 0x447 0x448 0x449>;
					bias-pull-up;
					input-enable;
				};

				rst-pins {
					input-schmitt-disable;
					input-disable;
					drive-strength = <0x0c>;
					pinmux = <0xff13003e>;
					slew-rate = <0x00>;
					bias-pull-up;
				};
			};

			i2srx-0 {
				phandle = <0x25>;

				clk-sd-pins {
					pinmux = <0x1f000426 0x2000043f 0x21000426 0x2200043f 0x1700043d>;
					input-enable;
				};
			};

			hdmi-0 {
				phandle = <0x53>;

				cec-pins {
					pinmux = <0x50a080e>;
					bias-pull-up;
					input-enable;
				};

				hpd-pins {
					bias-disable;
					pinmux = <0x800040f>;
					input-enable;
				};

				scl-pins {
					pinmux = <0x60b0c00>;
					bias-pull-up;
					input-enable;
				};

				sda-pins {
					pinmux = <0x70c1001>;
					bias-pull-up;
					input-enable;
				};
			};

			pwmdac-0 {
				phandle = <0x21>;

				pwmdac-pins {
					input-schmitt-disable;
					input-disable;
					drive-strength = <0x02>;
					bias-disable;
					pinmux = <0xff1c0021 0xff1d0022>;
					slew-rate = <0x00>;
				};
			};

			uart0-0 {
				phandle = <0x16>;

				tx-pins {
					input-schmitt-disable;
					input-disable;
					drive-strength = <0x0c>;
					bias-disable;
					pinmux = <0xff140005>;
					slew-rate = <0x00>;
				};

				rx-pins {
					drive-strength = <0x02>;
					bias-disable;
					pinmux = <0xe000406>;
					input-schmitt-enable;
					slew-rate = <0x00>;
					input-enable;
				};
			};

			pcie1-0 {
				phandle = <0x61>;

				clkreq-pins {
					input-schmitt-disable;
					drive-strength = <0x02>;
					pinmux = <0xff00041d>;
					bias-pull-down;
					slew-rate = <0x00>;
					input-enable;
				};

				wake-pins {
					input-schmitt-disable;
					drive-strength = <0x02>;
					pinmux = <0xff000415>;
					slew-rate = <0x00>;
					bias-pull-up;
					input-enable;
				};
			};

			i2c0-0 {
				phandle = <0x17>;

				i2c-pins {
					bias-disable;
					pinmux = <0x9001439 0xa00183a>;
					input-schmitt-enable;
					input-enable;
				};
			};

			tdm-0 {
				phandle = <0x1f>;

				pcmclk-pins {
					pinmux = <0x23010426>;
					input-enable;
				};

				sync-pins {
					pinmux = <0x2501043f>;
					input-enable;
				};

				tx-pins {
					input-schmitt-disable;
					input-disable;
					drive-strength = <0x02>;
					pinmux = <0xff29002c>;
					slew-rate = <0x00>;
					bias-pull-up;
				};

				rx-pins {
					pinmux = <0x2401043d>;
					input-enable;
				};
			};

			i2stx1-0 {
				phandle = <0x33>;

				sd-pins {
					input-disable;
					bias-disable;
					pinmux = <0xff45002c>;
				};
			};

			i2c6-0 {
				phandle = <0x2b>;

				i2c-pins {
					bias-disable;
					pinmux = <0x5600b810 0x5700bc11>;
					input-schmitt-enable;
					input-enable;
				};
			};

			pwm-0 {
				phandle = <0x34>;

				pwm-pins {
					input-schmitt-disable;
					input-disable;
					drive-strength = <0x0c>;
					bias-disable;
					pinmux = <0xff18242e 0xff19283b>;
					slew-rate = <0x00>;
				};
			};

			pcie0-0 {
				phandle = <0x5e>;

				clkreq-pins {
					input-schmitt-disable;
					drive-strength = <0x02>;
					pinmux = <0xff00041b>;
					bias-pull-down;
					slew-rate = <0x00>;
					input-enable;
				};

				wake-pins {
					input-schmitt-disable;
					drive-strength = <0x02>;
					pinmux = <0xff000420>;
					slew-rate = <0x00>;
					bias-pull-up;
					input-enable;
				};
			};

			mclk-ext-0 {
				phandle = <0x30>;

				mclk-ext-pins {
					pinmux = <0x1e000404>;
					input-enable;
				};
			};
		};

		crypto@16000000 {
			clock-names = "hclk\0ahb";
			resets = <0x27 0x03>;
			interrupts = <0x1c>;
			clocks = <0x27 0x0f 0x27 0x10>;
			dma-names = "tx\0rx";
			compatible = "starfive,jh7110-crypto";
			reg = <0x00 0x16000000 0x00 0x4000>;
			phandle = <0x9a>;
			dmas = <0x39 0x01 0x02 0x39 0x00 0x02>;
		};

		vpu_dec@130a0000 {
			power-domains = <0x38 0x03>;
			dma-coherent;
			clock-names = "axi_clk\0bpu_clk\0vce_clk\0apb_clk\0noc_bus\0main_clk";
			resets = <0x03 0x2f 0x03 0x30 0x03 0x31 0x03 0x32 0x03 0x35>;
			interrupts = <0x0d>;
			clocks = <0x03 0x46 0x03 0x47 0x03 0x48 0x03 0x49 0x03 0x4c 0x03 0x4b>;
			compatible = "starfive,vdec";
			status = "okay";
			reg = <0x00 0x130a0000 0x00 0x10000>;
			phandle = <0x96>;
			starfive,vdec_noc_ctrl;
			reset-names = "rst_axi\0rst_bpu\0rst_vce\0rst_apb\0rst_sram";
		};

		spi@12080000 {
			arm,primecell-periphid = <0x41022>;
			#address-cells = <0x01>;
			num-cs = <0x01>;
			clock-names = "sspclk\0apb_pclk";
			resets = <0x03 0x49>;
			interrupts = <0x35>;
			clocks = <0x03 0x87 0x03 0x87>;
			#size-cells = <0x00>;
			compatible = "arm,pl022\0arm,primecell";
			status = "disabled";
			reg = <0x00 0x12080000 0x00 0x10000>;
			phandle = <0x8e>;
		};

		pcie@9c0000000 {
			pinctrl-names = "default";
			#address-cells = <0x03>;
			bus-range = <0x00 0xff>;
			pinctrl-0 = <0x61>;
			clock-names = "noc\0tl\0axi_mst0\0apb";
			reg-names = "cfg\0apb";
			starfive,stg-syscon = <0x26>;
			resets = <0x27 0x11 0x27 0x12 0x27 0x13 0x27 0x14 0x27 0x15 0x27 0x16>;
			interrupts = <0x39>;
			clocks = <0x03 0x60 0x27 0x0d 0x27 0x0b 0x27 0x0c>;
			interrupt-map = <0x00 0x00 0x00 0x01 0x5f 0x01 0x00 0x00 0x00 0x02 0x5f 0x02 0x00 0x00 0x00 0x03 0x5f 0x03 0x00 0x00 0x00 0x04 0x5f 0x04>;
			#size-cells = <0x02>;
			perst-gpios = <0x1a 0x1c 0x01>;
			msi-controller;
			device_type = "pci";
			interrupt-map-mask = <0x00 0x00 0x00 0x07>;
			compatible = "starfive,jh7110-pcie";
			ranges = <0x82000000 0x00 0x38000000 0x00 0x38000000 0x00 0x8000000 0xc3000000 0x09 0x80000000 0x09 0x80000000 0x00 0x40000000>;
			#interrupt-cells = <0x01>;
			status = "okay";
			phys = <0x60>;
			reg = <0x09 0xc0000000 0x00 0x1000000 0x00 0x2c000000 0x00 0x100000>;
			linux,pci-domain = <0x01>;
			phandle = <0xaa>;
			reset-names = "mst0\0slv0\0slv\0brg\0core\0apb";

			interrupt-controller {
				#address-cells = <0x00>;
				#interrupt-cells = <0x01>;
				phandle = <0x5f>;
				interrupt-controller;
			};
		};

		&mmc0: mmc@16010000 {
			compatible = "starfive,jh7110-mmc";
			reg = <0x00 0x16010000 0x00 0x10000>;
			phandle = <0x9c>;

			clock-names = "biu", "ciu";
			clocks = <&syscrg 0x5b>, <&syscrg 0x5d>;

			assigned-clocks = <&syscrg 0x5d>;
			assigned-clock-rates = <0x2faf080>; // 50MHz

			reset-names = "reset";
			resets = <&syscrg 0x40>;

			interrupts = <0x4a>;

			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_mmc0_0>;

			fifo-depth = <0x20>;
			data-addr = <0x00>;
			vqmmc-supply = <0x3c>;
			mmc-hs200-1_8v;
			bus-width = <0x08>;
			non-removable;
			vmmc-supply = <0x3b>;
			cap-mmc-hw-reset;
			mmc-ddr-1_8v;
			post-power-on-delay-ms = <0xc8>;
			status = "okay";
			fifo-watermark-aligned;
			max-frequency = <0x5f5e100>; // 100MHz
			cap-mmc-highspeed;
			starfive,sysreg = <0x22 0x14 0x1a 0x7c000000>;
		};

		&aoncrg: clock-controller@17000000 {
			#reset-cells = <0x01>;
			clock-names =
                "osc",
                "gmac0_rmii_refin",
                "gmac0_rgmii_rxin",
                "stg_axiahb",
                "apb_bus",
                "gmac0_gtxclk",
                "rtc_osc";
			clocks = <0x29 0x43 0x44 0x03 0x08 0x03 0x0b 0x03 0x6c 0x45>;
			#clock-cells = <0x01>;
			compatible = "starfive,jh7110-aoncrg";
			reg = <0x00 0x17000000 0x00 0x10000>;
			phandle = <0x3e>;
		};

		serial@12010000 {
			reg-io-width = <0x04>;
			clock-names = "baudclk\0apb_pclk";
			resets = <0x03 0x5b 0x03 0x5c>;
			interrupts = <0x2e>;
			clocks = <0x03 0x9a 0x03 0x99>;
			compatible = "snps,dw-apb-uart";
			status = "disabled";
			reg = <0x00 0x12010000 0x00 0x10000>;
			phandle = <0x83>;
			reg-shift = <0x02>;
		};

		pcie@940000000 {
			pinctrl-names = "default";
			#address-cells = <0x03>;
			bus-range = <0x00 0xff>;
			pinctrl-0 = <0x5e>;
			clock-names = "noc\0tl\0axi_mst0\0apb";
			reg-names = "cfg\0apb";
			starfive,stg-syscon = <0x26>;
			resets = <0x27 0x0b 0x27 0x0c 0x27 0x0d 0x27 0x0e 0x27 0x0f 0x27 0x10>;
			interrupts = <0x38>;
			clocks = <0x03 0x60 0x27 0x0a 0x27 0x08 0x27 0x09>;
			interrupt-map = <0x00 0x00 0x00 0x01 0x5c 0x01 0x00 0x00 0x00 0x02 0x5c 0x02 0x00 0x00 0x00 0x03 0x5c 0x03 0x00 0x00 0x00 0x04 0x5c 0x04>;
			#size-cells = <0x02>;
			perst-gpios = <0x1a 0x1a 0x01>;
			msi-controller;
			device_type = "pci";
			interrupt-map-mask = <0x00 0x00 0x00 0x07>;
			compatible = "starfive,jh7110-pcie";
			ranges = <0x82000000 0x00 0x30000000 0x00 0x30000000 0x00 0x8000000 0xc3000000 0x09 0x00 0x09 0x00 0x00 0x40000000>;
			#interrupt-cells = <0x01>;
			status = "okay";
			phys = <0x5d>;
			reg = <0x09 0x40000000 0x00 0x1000000 0x00 0x2b000000 0x00 0x100000>;
			linux,pci-domain = <0x00>;
			phandle = <0xa9>;
			reset-names = "mst0\0slv0\0slv\0brg\0core\0apb";

			interrupt-controller {
				#address-cells = <0x00>;
				#interrupt-cells = <0x01>;
				phandle = <0x5c>;
				interrupt-controller;
			};
		};

		xrp@10230000 {
			#address-cells = <0x01>;
			dma-coherent;
			clock-names = "core_clk";
			firmware-name = "hifi4_elf";
			starfive,stg-syscon = <0x26>;
			resets = <0x27 0x01 0x27 0x02>;
			clocks = <0x27 0x00>;
			#size-cells = <0x01>;
			compatible = "cdns,xrp";
			ranges = <0x40000000 0x00 0x20000000 0x40000 0x69c00000 0x00 0x69c00000 0x3000000>;
			status = "disabled";
			reg = <0x00 0x10230000 0x00 0x10000 0x00 0x10240000 0x00 0x10000>;
			phandle = <0x81>;
			reset-names = "rst_core\0rst_axi";

			dsp@0 {
			};
		};

		timer@2000000 {
			interrupts-extended = <0x11 0x03 0x11 0x07 0x12 0x03 0x12 0x07 0x13 0x03 0x13 0x07 0x14 0x03 0x14 0x07 0x15 0x03 0x15 0x07>;
			compatible = "starfive,jh7110-clint\0sifive,clint0";
			reg = <0x00 0x2000000 0x00 0x10000>;
			phandle = <0x6e>;
		};

		i2c@12040000 {
			#address-cells = <0x01>;
			clock-names = "ref";
			resets = <0x03 0x50>;
			interrupts = <0x31>;
			clocks = <0x03 0x8e>;
			#size-cells = <0x00>;
			compatible = "snps,designware-i2c";
			status = "disabled";
			reg = <0x00 0x12040000 0x00 0x10000>;
			phandle = <0x86>;
		};

		&voutcrg: clock-controller@295c0000 {
			power-domains = <0x38 0x04>;
			#reset-cells = <0x01>;
			clock-names = "vout_src\0vout_top_ahb\0vout_top_axi\0vout_top_hdmitx0_mclk\0i2stx0_bclk\0hdmitx0_pixelclk";
			resets = <0x03 0x2b>;
			clocks = <0x03 0x3a 0x03 0x3d 0x03 0x3e 0x03 0x3f 0x03 0xa5 0x4f>;
			#clock-cells = <0x01>;
			compatible = "starfive,jh7110-voutcrg";
			reg = <0x00 0x295c0000 0x00 0x10000>;
			phandle = <0x4e>;
		};

		mipi-dphy@295e0000 {
			clock-names = "dphy_txesc";
			resets = <0x4e 0x0a 0x4e 0x0b>;
			clocks = <0x4e 0x0e>;
			#phy-cells = <0x00>;
			compatible = "starfive,jh7110-mipi-dphy-tx\0m31,mipi-dphy-tx";
			status = "okay";
			reg = <0x00 0x295e0000 0x00 0x10000>;
			phandle = <0x57>;
			reset-names = "dphy_sys\0dphy_txbytehs";
		};

		spi@10070000 {
			arm,primecell-periphid = <0x41022>;
			#address-cells = <0x01>;
			num-cs = <0x01>;
			clock-names = "sspclk\0apb_pclk";
			resets = <0x03 0x46>;
			interrupts = <0x27>;
			clocks = <0x03 0x84 0x03 0x84>;
			#size-cells = <0x00>;
			compatible = "arm,pl022\0arm,primecell";
			status = "disabled";
			reg = <0x00 0x10070000 0x00 0x10000>;
			phandle = <0x78>;
		};

		i2srx_mst@100e0000 {
			clock-names = "i2sclk\0apb\0mclk\0mclk_inner\0mclk_ext";
			resets = <0x03 0x63 0x03 0x64>;
			clocks = <0x03 0xb0 0x03 0xaf 0x03 0x12 0x03 0x11 0x20>;
			dma-names = "rx";
			#sound-dai-cells = <0x00>;
			starfive,syscon = <0x22 0x18 0x02 0x34 0x3fc00 0x24400>;
			compatible = "starfive,jh7110-i2srx-master";
			status = "disabled";
			reg = <0x00 0x100e0000 0x00 0x1000>;
			phandle = <0x7d>;
			dmas = <0x1e 0x18>;
		};

		can@130e0000 {
			syscon,can_or_canfd = <0x00>;
			clock-names = "apb_clk\0core_clk\0timer_clk";
			starfive,sys-syscon = <0x22 0x88 0x12 0x40000>;
			resets = <0x03 0x72 0x03 0x73 0x03 0x74>;
			interrupts = <0x71>;
			clocks = <0x03 0x76 0x03 0x78 0x03 0x77>;
			compatible = "starfive,jh7110-can\0ipms,can";
			status = "disabled";
			frequency = <0x2625a00>;
			reg = <0x00 0x130e0000 0x00 0x1000>;
			phandle = <0x99>;
			reset-names = "rst_apb\0rst_core\0rst_timer";
		};

		rtc@17040000 {
			clock-names = "pclk", "cal_clk";
			clocks = <&aoncrg 0x0a>, <&aoncrg 0x0d>;
			reset-names = "rst_osc", "rst_apb", "rst_cal";
			resets = <&aoncrg 0x07>, <&aoncrg 0x05>, <&aoncrg 0x06>;
			interrupts = <0x0a 0x0b 0x0c>;
			compatible = "starfive,jh7110-rtc";
			interrupt-names = "rtc_ms_pulse\0rtc_sec_pulse\0rtc";
			reg = <0x00 0x17040000 0x00 0x10000>;
			phandle = <0xa0>;
			rtc,cal-clock-freq = <0xf4240>;
		};

		&usbphy0: phy@10200000 {
			clock-names = "125m", "app_125m";
			clocks = <
                &syscrg 0x5f /* 125MHz */
                0x27 0x06
            >;
			#phy-cells = <0x00>;
			compatible = "starfive,jh7110-usb-phy";
			reg = <0x00 0x10200000 0x00 0x10000>;
			phandle = <0x28>;
		};

		spi@12090000 {
			arm,primecell-periphid = <0x41022>;
			#address-cells = <0x01>;
			num-cs = <0x01>;
			clock-names = "sspclk\0apb_pclk";
			resets = <0x03 0x4a>;
			interrupts = <0x36>;
			clocks = <0x03 0x88 0x03 0x88>;
			#size-cells = <0x00>;
			compatible = "arm,pl022\0arm,primecell";
			status = "disabled";
			reg = <0x00 0x12090000 0x00 0x10000>;
			phandle = <0x8f>;
		};

		serial@10000000 {
			reg-io-width = <0x04>;
			pinctrl-names = "default";
			pinctrl-0 = <0x16>;
			clock-names = "baudclk\0apb_pclk";
			resets = <0x03 0x53 0x03 0x54>;
			interrupts = <0x20>;
			clocks = <0x03 0x92 0x03 0x91>;
			compatible = "snps,dw-apb-uart";
			status = "okay";
			reg = <0x00 0x10000000 0x00 0x10000>;
			phandle = <0x6f>;
			reg-shift = <0x02>;
		};

		vpu_enc@130b0000 {
			power-domains = <0x38 0x06>;
			dma-coherent;
			clock-names = "axi_clk\0bpu_clk\0vce_clk\0apb_clk\0noc_bus";
			resets = <0x03 0x36 0x03 0x37 0x03 0x38 0x03 0x39 0x03 0x3a>;
			interrupts = <0x0f>;
			clocks = <0x03 0x4e 0x03 0x4f 0x03 0x50 0x03 0x51 0x03 0x52>;
			compatible = "starfive,venc";
			status = "okay";
			reg = <0x00 0x130b0000 0x00 0x10000>;
			phandle = <0x97>;
			starfive,venc_noc_ctrl;
			reset-names = "rst_axi\0rst_bpu\0rst_vce\0rst_apb\0rst_sram";
		};

		i2c@10030000 {
			pinctrl-names = "default";
			#address-cells = <0x01>;
			i2c-sda-hold-time-ns = <0x12c>;
			pinctrl-0 = <0x17>;
			clock-names = "ref";
			i2c-scl-falling-time-ns = <0x1fe>;
			i2c-sda-falling-time-ns = <0x1fe>;
			resets = <0x03 0x4c>;
			interrupts = <0x23>;
			clocks = <0x03 0x8a>;
			#size-cells = <0x00>;
			clock-frequency = <0x186a0>;
			compatible = "snps,designware-i2c";
			status = "okay";
			reg = <0x00 0x10030000 0x00 0x10000>;
			phandle = <0x72>;
		};

		&mmc1: mmc@16020000 {
			compatible = "starfive,jh7110-mmc";
			phandle = <0x9d>;
			reg = <0x00 0x16020000 0x00 0x10000>;

			clock-names = "biu", "ciu";
			clocks = <&syscrg 0x5c>, <&syscrg 0x5e>;

			assigned-clock-rates = <0x2faf080>; // 50MHz
			assigned-clocks = <&syscrg 0x5e>;

			resets = <&syscrg 0x41>;

			reset-names = "reset";
			interrupts = <0x4b>;

			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_mmc1_0>;

			fifo-depth = <0x20>;
			data-addr = <0x00>;
			cap-sd-highspeed;
			no-mmc;
			bus-width = <0x04>;
			no-sdio;
			broken-cd;
			post-power-on-delay-ms = <0xc8>;
			status = "okay";
			fifo-watermark-aligned;
			max-frequency = <0x5f5e100>; // 100MHz
			starfive,sysreg = <0x22 0x9c 0x01 0x3e>;
		};

		interrupt-controller@c000000 {
			#address-cells = <0x00>;
			interrupts-extended = <0x11 0x0b 0x12 0x0b 0x12 0x09 0x13 0x0b 0x13 0x09 0x14 0x0b 0x14 0x09 0x15 0x0b 0x15 0x09>;
			compatible = "starfive,jh7110-plic\0sifive,plic-1.0.0";
			#interrupt-cells = <0x01>;
			reg = <0x00 0xc000000 0x00 0x4000000>;
			phandle = <0x10>;
			riscv,ndev = <0x88>;
			interrupt-controller;
		};

		phy@19820000 {
			power-domains = <0x40 0x01>;
			clock-names = "cfg\0ref\0tx";
			resets = <0x46 0x02 0x46 0x03>;
			clocks = <0x46 0x03 0x46 0x04 0x46 0x05>;
			#phy-cells = <0x00>;
			compatible = "starfive,jh7110-dphy-rx";
			reg = <0x00 0x19820000 0x00 0x10000>;
			phandle = <0x47>;
		};

		serial@12020000 {
			reg-io-width = <0x04>;
			clock-names = "baudclk\0apb_pclk";
			resets = <0x03 0x5d 0x03 0x5e>;
			interrupts = <0x2f>;
			clocks = <0x03 0x9c 0x03 0x9b>;
			compatible = "snps,dw-apb-uart";
			status = "disabled";
			reg = <0x00 0x12020000 0x00 0x10000>;
			phandle = <0x84>;
			reg-shift = <0x02>;
		};

		dssctrl@295B0000 {
			compatible = "starfive,jh7110-dssctrl\0verisilicon,dss-ctrl\0syscon";
			reg = <0x00 0x295b0000 0x00 0x90>;
			phandle = <0x4d>;
		};

		mipi@295d0000 {
			phy-names = "dphy";
			clock-names = "dpi\0apb\0txesc\0sys";
			reg-names = "dsi";
			resets = <0x4e 0x03 0x4e 0x04 0x4e 0x05 0x4e 0x06 0x4e 0x07 0x4e 0x08>;
			interrupts = <0x62>;
			clocks = <0x4e 0x0b 0x4e 0x0a 0x4e 0x0d 0x4e 0x0c>;
			compatible = "starfive,jh7110-mipi_dsi\0cdns,dsi";
			status = "okay";
			phys = <0x57>;
			reg = <0x00 0x295d0000 0x00 0x10000>;
			phandle = <0xa7>;
			reset-names = "dsi_dpi\0dsi_apb\0dsi_rxesc\0dsi_sys\0dsi_txbytehs\0dsi_txesc";

			ports {
				#address-cells = <0x01>;
				#size-cells = <0x00>;

				port@0 {
					#address-cells = <0x01>;
					#size-cells = <0x00>;
					reg = <0x00>;

					endpoint@1 {
						remote-endpoint = <0x59>;
						reg = <0x01>;
						phandle = <0x1b>;
					};

					endpoint@0 {
						remote-endpoint = <0x58>;
						reg = <0x00>;
						phandle = <0x19>;
					};
				};

				port@1 {
					reg = <0x01>;

					endpoint {
						remote-endpoint = <0x5a>;
						phandle = <0x0c>;
					};
				};
			};
		};

		temperature-sensor@120e0000 {
			clock-names = "sense\0bus";
			resets = <0x03 0x7c 0x03 0x7b>;
			clocks = <0x03 0x82 0x03 0x81>;
			#thermal-sensor-cells = <0x00>;
			compatible = "starfive,jh7110-temp";
			reg = <0x00 0x120e0000 0x00 0x10000>;
			phandle = <0x0e>;
			reset-names = "sense\0bus";
		};

		i2c@12050000 {
			pinctrl-names = "default";
			#address-cells = <0x01>;
			i2c-sda-hold-time-ns = <0x12c>;
			pinctrl-0 = <0x2a>;
			clock-names = "ref";
			i2c-scl-falling-time-ns = <0x1fe>;
			i2c-sda-falling-time-ns = <0x1fe>;
			resets = <0x03 0x51>;
			interrupts = <0x32>;
			clocks = <0x03 0x8f>;
			#size-cells = <0x00>;
			clock-frequency = <0x186a0>;
			compatible = "snps,designware-i2c";
			status = "okay";
			reg = <0x00 0x12050000 0x00 0x10000>;
			phandle = <0x87>;

			pmic@36 {
				interrupts = <0x00>;
				compatible = "x-powers,axp15060";
				#interrupt-cells = <0x01>;
				reg = <0x36>;
				phandle = <0x88>;
				interrupt-controller;

				regulators {

					ALDO5 {
						regulator-max-microvolt = <0xdbba0>;
						regulator-boot-on;
						regulator-min-microvolt = <0xdbba0>;
						regulator-name = "hdmi_0p9";
						phandle = <0x54>;
						regulator-compatible = "aldo5";
					};

					dcdc1 {
						regulator-max-microvolt = <0x325aa0>;
						regulator-boot-on;
						regulator-always-on;
						regulator-min-microvolt = <0x325aa0>;
						regulator-name = "vcc_3v3";
						phandle = <0x3b>;
						regulator-compatible = "dcdc1";
					};

					ALDO3 {
						regulator-max-microvolt = <0x1b7740>;
						regulator-boot-on;
						regulator-min-microvolt = <0x1b7740>;
						regulator-name = "hdmi_1p8";
						phandle = <0x55>;
						regulator-compatible = "aldo3";
					};

					ALDO1 {
						regulator-max-microvolt = <0xdbba0>;
						regulator-boot-on;
						regulator-min-microvolt = <0xdbba0>;
						regulator-name = "mipi_0p9";
						phandle = <0x48>;
						regulator-compatible = "aldo1";
					};

					aldo4 {
						regulator-max-microvolt = <0x1b7740>;
						regulator-boot-on;
						regulator-always-on;
						regulator-min-microvolt = <0x1b7740>;
						regulator-name = "emmc_vdd";
						phandle = <0x3c>;
						regulator-compatible = "aldo4";
					};

					dcdc2 {
						regulator-max-microvolt = <0x177fa0>;
						regulator-always-on;
						regulator-min-microvolt = <0x7a120>;
						regulator-name = "vdd-cpu";
						phandle = <0x04>;
						regulator-compatible = "dcdc2";
					};
				};
			};
		};

		&eth0: ethernet@16030000 {
			snps,multicast-filter-bins = <0x40>;
			phy-mode = "rgmii-id";
			snps,txpbl = <0x10>;
			clocks =
                <&aoncrg CLK_GMAC5_AXI>,            // smmaceth
                <&aoncrg CLK_GMAC5_AHB>,            // pclk
                <&syscrg CLK_GMAC0_PTP>,            // ptp_ref
                <&aoncrg CLK_GMAC5_AXI64_TX_INV>,   // tx
                <&syscrg CLK_GMAC0_GTXC>;           // gtx
			clock-names =
                "stmmaceth",
                "pclk",
                "ptp_ref",
                "tx",
                "gtx";
			assigned-clocks = <0x3e 0x05>;
			assigned-clock-parents = <0x3e 0x04>;
			snps,en-tx-lpi-clockgating;
			local-mac-address = [6c cf 39 00 b1 0c];
			snps,fixed-burst;
			resets = <0x3e 0x00 0x3e 0x01>;
			interrupts = <0x07 0x06 0x05>;
			snps,no-pbl-x8;
			snps,tso;
			starfive,syscon = <0x40 0x0c 0x12>;
			snps,rxpbl = <0x10>;
			compatible = "starfive,jh7110-dwmac\0snps,dwmac-5.20";
			status = "okay";
			tx-fifo-depth = <0x800>;
			interrupt-names = "macirq\0eth_wake_irq\0eth_lpi";
			snps,force_thresh_dma_mode;
			rx-fifo-depth = <0x800>;
			reg = <0x00 0x16030000 0x00 0x10000>;
			phandle = <0x9e>;
			phy-handle = <0x41>;
			reset-names = "stmmaceth\0ahb";
			snps,axi-config = <0x3f>;
			starfive,tx-use-rgmii-clk;
			snps,perfect-filter-entries = <0x100>;

			mdio {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				compatible = "snps,dwmac-mdio";

				ethernet-phy@0 {
					rx-internal-delay-ps = <0x5dc>;
					motorcomm,rx-clk-drv-microamp = <0xf82>;
					motorcomm,rx-data-drv-microamp = <0xb5e>;
					motorcomm,tx-clk-100-inverted;
					reg = <0x00>;
					motorcomm,tx-clk-1000-inverted;
					phandle = <0x41>;
					tx-internal-delay-ps = <0x5dc>;
					motorcomm,tx-clk-adj-enabled;
				};
			};
		};

		syscon@17010000 {
			#power-domain-cells = <0x01>;
			compatible = "starfive,jh7110-aon-syscon\0syscon";
			reg = <0x00 0x17010000 0x00 0x1000>;
			phandle = <0x40>;
		};

		tdm@10090000 {
			pinctrl-names = "default";
			pinctrl-0 = <0x1f>;
			clock-names = "tdm_ahb\0tdm_apb\0tdm_internal\0tdm\0mclk_inner\0tdm_ext";
			resets = <0x03 0x69 0x03 0x6b 0x03 0x6a>;
			clocks = <0x03 0xb8 0x03 0xb9 0x03 0xba 0x03 0xbb 0x03 0x11 0x1d>;
			dma-names = "rx\0tx";
			#sound-dai-cells = <0x00>;
			compatible = "starfive,jh7110-tdm";
			status = "disabled";
			reg = <0x00 0x10090000 0x00 0x1000>;
			phandle = <0x7a>;
			dmas = <0x1e 0x14 0x1e 0x15>;
		};

		power-controller@17030000 {
			interrupts = <0x6f>;
			#power-domain-cells = <0x01>;
			compatible = "starfive,jh7110-pmu";
			reg = <0x00 0x17030000 0x00 0x10000>;
			phandle = <0x38>;
		};

		i2s@120b0000 {
			pinctrl-names = "default";
			pinctrl-0 = <0x30>;
			clock-names = "i2sclk\0apb\0mclk\0mclk_inner\0mclk_ext";
			resets = <0x03 0x65 0x03 0x66>;
			clocks = <0x03 0xa2 0x03 0xa1 0x03 0x12 0x03 0x11 0x20>;
			dma-names = "tx";
			#sound-dai-cells = <0x00>;
			compatible = "starfive,jh7110-i2stx0";
			status = "okay";
			reg = <0x00 0x120b0000 0x00 0x1000>;
			phandle = <0x67>;
			dmas = <0x1e 0x2f>;
		};

		spi@10080000 {
			arm,primecell-periphid = <0x41022>;
			#address-cells = <0x01>;
			num-cs = <0x01>;
			clock-names = "sspclk\0apb_pclk";
			resets = <0x03 0x47>;
			interrupts = <0x28>;
			clocks = <0x03 0x85 0x03 0x85>;
			#size-cells = <0x00>;
			compatible = "arm,pl022\0arm,primecell";
			status = "disabled";
			reg = <0x00 0x10080000 0x00 0x10000>;
			phandle = <0x79>;
		};

		rng@1600c000 {
			clock-names = "hclk\0ahb";
			resets = <0x27 0x03>;
			interrupts = <0x1e>;
			clocks = <0x27 0x0f 0x27 0x10>;
			compatible = "starfive,jh7110-trng";
			reg = <0x00 0x1600c000 0x00 0x4000>;
			phandle = <0x9b>;
		};

		spi@13010000 {
			#address-cells = <0x01>;
			clock-names = "ref\0ahb\0apb";
			resets = <0x03 0x3e 0x03 0x3d 0x03 0x3f>;
			interrupts = <0x19>;
			clocks = <0x03 0x5a 0x03 0x57 0x03 0x58>;
			cdns,fifo-width = <0x04>;
			#size-cells = <0x00>;
			cdns,trigger-address = <0x00>;
			compatible = "starfive,jh7110-qspi\0cdns,qspi-nor";
			status = "okay";
			reg = <0x00 0x13010000 0x00 0x10000 0x00 0x21000000 0x00 0x400000>;
			phandle = <0x93>;
			reset-names = "qspi\0qspi-ocp\0rstc_ref";
			cdns,fifo-depth = <0x100>;

			flash@0 {
				cdns,tshsl-ns = <0x01>;
				spi-max-frequency = <0xb71b00>;
				cdns,tsd2d-ns = <0x01>;
				cdns,read-delay = <0x05>;
				cdns,tslch-ns = <0x01>;
				compatible = "jedec,spi-nor";
				reg = <0x00>;
				phandle = <0x94>;
				cdns,tchsh-ns = <0x01>;

				partitions {
					#address-cells = <0x01>;
					#size-cells = <0x01>;
					compatible = "fixed-partitions";

					reserved-data@600000 {
						reg = <0x600000 0xa00000>;
					};

					uboot-env@f0000 {
						reg = <0xf0000 0x10000>;
					};

					spl@0 {
						reg = <0x00 0x80000>;
					};

					uboot@100000 {
						reg = <0x100000 0x400000>;
					};
				};
			};
		};

		&syscrg: clock-controller@13020000 {
			#reset-cells = <0x01>;
			clock-names =
                "osc",
                "gmac1_rmii_refin",
                "gmac1_rgmii_rxin",
                "i2stx_bclk_ext",
                "i2stx_lrck_ext",
                "i2srx_bclk_ext",
                "i2srx_lrck_ext",
                "tdm_ext",
                "mclk_ext",
                "pll0_out",
                "pll1_out",
                "pll2_out";
			clocks = <
                0x29
                0x35
                0x36
                0x31
                0x32
                0x23
                0x24
                0x1d
                0x20
                0x37 0x00
                0x37 0x01
                0x37 0x02
            >;
			#clock-cells = <0x01>;
			compatible = "starfive,jh7110-syscrg";
			reg = <0x00 0x13020000 0x00 0x10000>;
			phandle = <0x03>;
		};

		cache-controller@2010000 {
			cache-size = <0x200000>;
			cache-level = <0x02>;
			cache-sets = <0x800>;
			interrupts = <0x01 0x03 0x04 0x02>;
			cache-unified;
			compatible = "starfive,jh7110-ccache\0sifive,ccache0\0cache";
			reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x2000000 0x00 0xa000000 0x00 0x2000000>;
			phandle = <0x01>;
			cache-block-size = <0x40>;
		};

		phy@10210000 {
			#phy-cells = <0x00>;
			compatible = "starfive,jh7110-pcie-phy";
			reg = <0x00 0x10210000 0x00 0x10000>;
			phandle = <0x5d>;
		};

		serial@10010000 {
			reg-io-width = <0x04>;
			clock-names = "baudclk\0apb_pclk";
			resets = <0x03 0x55 0x03 0x56>;
			interrupts = <0x21>;
			clocks = <0x03 0x94 0x03 0x93>;
			compatible = "snps,dw-apb-uart";
			status = "disabled";
			reg = <0x00 0x10010000 0x00 0x10000>;
			phandle = <0x70>;
			reg-shift = <0x02>;
		};

		pinctrl@17020000 {
			gpio-controller;
			resets = <0x3e 0x02>;
			interrupts = <0x55>;
			compatible = "starfive,jh7110-aon-pinctrl";
			#interrupt-cells = <0x02>;
			reg = <0x00 0x17020000 0x00 0x10000>;
			phandle = <0x62>;
			#gpio-cells = <0x02>;
			interrupt-controller;
		};

		i2c@10040000 {
			#address-cells = <0x01>;
			clock-names = "ref";
			resets = <0x03 0x4d>;
			interrupts = <0x24>;
			clocks = <0x03 0x8b>;
			#size-cells = <0x00>;
			compatible = "snps,designware-i2c";
			status = "disabled";
			reg = <0x00 0x10040000 0x00 0x10000>;
			phandle = <0x73>;
		};

		&stgcrg: clock-controller@10230000 {
			#reset-cells = <0x01>;
			clock-names =
                "osc",
                "hifi4_core",
                "stg_axiahb",
                "usb_125m",
                "cpu_bus",
                "hifi4_axi",
                "nocstg_bus",
                "apb_bus";
			clocks = <
                &clk_osc
                &syscrg 0x36
                &syscrg 0x08
                &syscrg 0x5f
                &syscrg 0x02
                &syscrg 0x37
                &syscrg 0x06
                &syscrg 0x0b
            >;
			#clock-cells = <0x01>;
			compatible = "starfive,jh7110-stgcrg";
			reg = <0x00 0x10230000 0x00 0x10000>;
			phandle = <0x27>;
		};

		mailbox@13060000 {
			clock-names = "clk_apb";
			resets = <0x03 0x44>;
			interrupts = <0x1a 0x1b>;
			clocks = <0x03 0x71>;
			#mbox-cells = <0x02>;
			compatible = "starfive,mail_box";
			status = "okay";
			reg = <0x00 0x13060000 0x00 0x1000>;
			phandle = <0x0d>;
			reset-names = "mbx_rre";
		};

		clock-controller@19810000 {
			power-domains = <0x38 0x05>;
			#reset-cells = <0x01>;
			clock-names = "isp_top_core\0isp_top_axi\0noc_bus_isp_axi\0dvp_clk";
			resets = <0x03 0x29 0x03 0x2a 0x03 0x1c>;
			clocks = <0x03 0x33 0x03 0x34 0x03 0x35 0x4c>;
			#clock-cells = <0x01>;
			compatible = "starfive,jh7110-ispcrg";
			reg = <0x00 0x19810000 0x00 0x10000>;
			phandle = <0x46>;
		};

		i2c@12060000 {
			pinctrl-names = "default";
			#address-cells = <0x01>;
			i2c-sda-hold-time-ns = <0x12c>;
			pinctrl-0 = <0x2b>;
			clock-names = "ref";
			i2c-scl-falling-time-ns = <0x1fe>;
			i2c-sda-falling-time-ns = <0x1fe>;
			resets = <0x03 0x52>;
			interrupts = <0x33>;
			clocks = <0x03 0x90>;
			#size-cells = <0x00>;
			clock-frequency = <0x186a0>;
			compatible = "snps,designware-i2c";
			status = "okay";
			reg = <0x00 0x12060000 0x00 0x10000>;
			phandle = <0x89>;

			ov4689@36 {
				clock-names = "xclk";
				clocks = <0x2c>;
				rotation = <0xb4>;
				compatible = "ovti,ov4689";
				reg = <0x36>;
				phandle = <0x8c>;

				port {

					endpoint {
						data-lanes = <0x01 0x02>;
						clock-lanes = <0x00>;
						remote-endpoint = <0x2f>;
						bus-type = <0x04>;
						phandle = <0x4b>;
					};
				};
			};

			imx708@1a {
				clocks = <0x2c>;
				reset-gpio = <0x1a 0x12 0x00>;
				compatible = "sony,imx708";
				reg = <0x1a>;
				phandle = <0x8b>;

				port {

					endpoint {
						data-lanes = <0x01 0x02>;
						clock-noncontinuous;
						remote-endpoint = <0x2e>;
						phandle = <0x4a>;
						link-frequencies = <0x00 0x1ad27480>;
					};
				};
			};

			imx219@10 {
				clock-names = "xclk";
				clocks = <0x2c>;
				rotation = <0x00>;
				reset-gpio = <0x1a 0x12 0x00>;
				compatible = "sony,imx219";
				orientation = <0x01>;
				reg = <0x10>;
				phandle = <0x8a>;

				port {

					endpoint {
						data-lanes = <0x00 0x01>;
						clock-lanes = <0x04>;
						remote-endpoint = <0x2d>;
						bus-type = <0x04>;
						lane-polarities = <0x00 0x00 0x00>;
						phandle = <0x49>;
						link-frequencies = <0x00 0x1b2e0200>;
					};
				};
			};
		};

		ethernet@16040000 {
			snps,multicast-filter-bins = <0x40>;
			phy-mode = "rgmii-id";
			snps,txpbl = <0x10>;
			clock-names = "stmmaceth\0pclk\0ptp_ref\0tx\0gtx";
			assigned-clocks = <0x03 0x69>;
			assigned-clock-parents = <0x03 0x65>;
			snps,en-tx-lpi-clockgating;
			local-mac-address = [6c cf 39 00 b1 0d];
			snps,fixed-burst;
			resets = <0x03 0x42 0x03 0x43>;
			interrupts = <0x4e 0x4d 0x4c>;
			clocks = <0x03 0x62 0x03 0x61 0x03 0x66 0x03 0x6a 0x03 0x6b>;
			snps,no-pbl-x8;
			snps,tso;
			starfive,syscon = <0x22 0x90 0x02>;
			snps,rxpbl = <0x10>;
			compatible = "starfive,jh7110-dwmac\0snps,dwmac-5.20";
			status = "okay";
			tx-fifo-depth = <0x800>;
			interrupt-names = "macirq\0eth_wake_irq\0eth_lpi";
			snps,force_thresh_dma_mode;
			rx-fifo-depth = <0x800>;
			reg = <0x00 0x16040000 0x00 0x10000>;
			phandle = <0x9f>;
			phy-handle = <0x42>;
			reset-names = "stmmaceth\0ahb";
			snps,axi-config = <0x3f>;
			starfive,tx-use-rgmii-clk;
			snps,perfect-filter-entries = <0x100>;

			mdio {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				compatible = "snps,dwmac-mdio";

				ethernet-phy@1 {
					rx-internal-delay-ps = <0x12c>;
					motorcomm,rx-clk-drv-microamp = <0xf82>;
					motorcomm,rx-data-drv-microamp = <0xb5e>;
					motorcomm,tx-clk-100-inverted;
					reg = <0x00>;
					phandle = <0x42>;
					tx-internal-delay-ps = <0x00>;
					motorcomm,tx-clk-adj-enabled;
				};
			};
		};

		spi@120a0000 {
			arm,primecell-periphid = <0x41022>;
			#address-cells = <0x01>;
			num-cs = <0x01>;
			clock-names = "sspclk\0apb_pclk";
			resets = <0x03 0x4b>;
			interrupts = <0x37>;
			clocks = <0x03 0x89 0x03 0x89>;
			#size-cells = <0x00>;
			compatible = "arm,pl022\0arm,primecell";
			status = "disabled";
			reg = <0x00 0x120a0000 0x00 0x10000>;
			phandle = <0x90>;
		};

		i2s@100e0000 {
			pinctrl-names = "default";
			pinctrl-0 = <0x25>;
			clock-names = "i2sclk\0apb\0mclk\0mclk_inner\0mclk_ext\0bclk\0lrck\0bclk_ext\0lrck_ext";
			resets = <0x03 0x63 0x03 0x64>;
			clocks = <0x03 0xb0 0x03 0xaf 0x03 0x12 0x03 0x11 0x20 0x03 0xb3 0x03 0xb5 0x23 0x24>;
			dma-names = "tx\0rx";
			#sound-dai-cells = <0x00>;
			starfive,syscon = <0x22 0x18 0x02>;
			compatible = "starfive,jh7110-i2srx";
			status = "disabled";
			reg = <0x00 0x100e0000 0x00 0x1000>;
			phandle = <0x7e>;
			dmas = <0x00 0x1e 0x18>;
		};

		watchdog@13070000 {
			clock-names = "apb\0core";
			resets = <0x03 0x6d 0x03 0x6e>;
			clocks = <0x03 0x7a 0x03 0x7b>;
			compatible = "starfive,jh7110-wdt";
			reg = <0x00 0x13070000 0x00 0x10000>;
		};

		gpu@18000000 {
			power-domains = <0x38 0x02>;
			clock-names = "clk_bv\0clk_apb\0clk_rtc\0clk_core\0clk_sys\0clk_axi";
			current-clock = <0x7a1200>;
			resets = <0x03 0x15 0x03 0x16>;
			interrupts = <0x52>;
			clocks = <0x03 0x2d 0x03 0x30 0x03 0x31 0x03 0x2e 0x03 0x2f 0x03 0x32>;
			compatible = "img-gpu";
			status = "okay";
			reg = <0x00 0x18000000 0x00 0x100000 0x00 0x130c000 0x00 0x10000>;
			phandle = <0xa1>;
			reset-names = "rst_apb\0rst_doma";
		};

		i2s@120c0000 {
			pinctrl-names = "default";
			pinctrl-0 = <0x33>;
			clock-names = "i2sclk\0apb\0mclk\0mclk_inner\0mclk_ext\0bclk\0lrck\0bclk_ext\0lrck_ext";
			resets = <0x03 0x67 0x03 0x68>;
			clocks = <0x03 0xa9 0x03 0xa8 0x03 0x12 0x03 0x11 0x20 0x03 0xac 0x03 0xae 0x31 0x32>;
			dma-names = "tx";
			#sound-dai-cells = <0x00>;
			compatible = "starfive,jh7110-i2stx1";
			status = "disabled";
			reg = <0x00 0x120c0000 0x00 0x1000>;
			phandle = <0x91>;
			dmas = <0x1e 0x30>;
		};

		usb@10100000 {
			#address-cells = <0x01>;
			#size-cells = <0x01>;

			starfive,stg-syscon = <0x26 0x04>;
			reset-names = "pwrup", "apb", "axi", "utmi_apb";
			resets = <
                0x27 0x0a /* PWRUP */
                0x27 0x08 /* APB */
                0x27 0x07 /* AXI */
                0x27 0x09 /* UTMI APB */
            >;
			clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
			clocks = <
                0x27 0x04 /* LPM */
                0x27 0x05 /* STB */
                0x27 0x01 /* APB */
                0x27 0x03 /* AXI */
                0x27 0x02 /* UTMI APB */
            >;
			compatible = "starfive,jh7110-usb";
			ranges = <0x00 0x00 0x10100000 0x100000>;
			status = "okay";
			phandle = <0x7f>;
			dr_mode = "peripheral";

			usb@0 {
				phy-names = "cdns3,usb2-phy";
				reg-names = "otg", "xhci", "dev";
				reg = <
                    0x00000000  0x00010000 /* OTG */
                    0x00010000  0x00010000 /* XHCI */
                    0x00020000  0x00010000 /* DEV */
                >;
				interrupt-names = "host", "peripheral", "otg";
				interrupts = <
                    0x64 /* HOST */
                    0x6c /* PERIPHERAL */
                    0x6e /* OTG */
                >;
				compatible = "cdns,usb3";
				phys = <&usbphy0>;
				phandle = <0x80>;
			};
		};
	};

	leds {
		compatible = "gpio-leds";

		led-ack {
			linux,default-trigger = "heartbeat";
			function = "heartbeat";
			color = <0x02>;
			label = "ack";
			gpios = <0x62 0x03 0x00>;
		};
	};

	snd-card1 {
		simple-audio-card,name = "Starfive-HDMI-Sound-Card";
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		compatible = "simple-audio-card";
		phandle = <0xad>;

		simple-audio-card,dai-link@0 {
			mclk-fs = <0x100>;
			format = "i2s";
			frame-master = <0x66>;
			status = "okay";
			bitclock-master = <0x66>;
			reg = <0x00>;

			cpu {
				phandle = <0x66>;
				sound-dai = <0x67>;
			};

			codec {
				sound-dai = <0x68>;
			};
		};
	};

	dvp-clock {
		clock-output-names = "dvp_clk";
		#clock-cells = <0x00>;
		clock-frequency = <0x46cf710>;
		compatible = "fixed-clock";
		phandle = <0x4c>;
	};

	i2srx-lrck-ext-clock {
		clock-output-names = "i2srx_lrck_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0x2ee00>;
		compatible = "fixed-clock";
		phandle = <0x24>;
	};

	gpio-restart {
		priority = <0xe0>;
		compatible = "gpio-restart";
		gpios = <0x1a 0x23 0x00>;
	};

	pwmdac-codec {
		#sound-dai-cells = <0x00>;
		compatible = "linux,spdif-dit";
		phandle = <0x65>;
	};

	tdm-ext-clock {
		clock-output-names = "tdm_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0x2ee0000>;
		compatible = "fixed-clock";
		phandle = <0x1d>;
	};

	mclk-ext-clock {
		clock-output-names = "mclk_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0xbb8000>;
		compatible = "fixed-clock";
		phandle = <0x20>;
	};

	tda988x_pin {
		compatible = "starfive,tda998x_rgb_pin";
		status = "disabled";
		phandle = <0x6d>;
	};

	opp-table-0 {
		opp-shared;
		compatible = "operating-points-v2";
		phandle = <0x02>;

		opp-500000000 {
			opp-microvolt = <0xdbba0>;
			opp-hz = <0x00 0x1dcd6500>;
		};

		opp-750000000 {
			opp-microvolt = <0xdbba0>;
			opp-hz = <0x00 0x2cb41780>;
			opp-suspend;
		};

		opp-1500000000 {
			opp-microvolt = <0x102ca0>;
			opp-hz = <0x00 0x59682f00>;
		};

		opp-375000000 {
			opp-microvolt = <0xdbba0>;
			opp-hz = <0x00 0x165a0bc0>;
		};
	};

	mailbox_client {
		compatible = "starfive,mailbox-test";
		status = "okay";
		phandle = <0x6b>;
		mboxes = <0x0d 0x00 0x01 0x0d 0x01 0x00>;
		mbox-names = "rx\0tx";
	};

	&hdmitx0_pixelclk: hdmitx0-pixel-clock {
		clock-output-names = "hdmitx0_pixelclk";
		#clock-cells = <0x00>;
		clock-frequency = <0x11b3dc40>; /* 297MHz */
		compatible = "fixed-clock";
		phandle = <0x4f>;
	};

	aliases {
		i2c3 = "/soc/i2c@12030000";
		ethernet0 = "/soc/ethernet@16030000";
		i2c1 = "/soc/i2c@10040000";
		mmc1 = "/soc/mmc@16020000";
		serial3 = "/soc/serial@12000000";
		i2c6 = "/soc/i2c@12060000";
		pcie0 = "/soc/pcie@940000000";
		i2c4 = "/soc/i2c@12040000";
		ethernet1 = "/soc/ethernet@16040000";
		i2c2 = "/soc/i2c@10050000";
		i2c0 = "/soc/i2c@10030000";
		mmc0 = "/soc/mmc@16010000";
		pcie1 = "/soc/pcie@9c0000000";
		i2c5 = "/soc/i2c@12050000";
		serial0 = "/soc/serial@10000000";
	};

	i2stx-bclk-ext-clock {
		clock-output-names = "i2stx_bclk_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0xbb8000>;
		compatible = "fixed-clock";
		phandle = <0x31>;
	};

	ac108_mclk {
		#clock-cells = <0x00>;
		clock-frequency = <0x16e3600>;
		compatible = "fixed-clock";
		phandle = <0xae>;
	};

	clk-ext-camera {
		#clock-cells = <0x00>;
		clock-frequency = <0x16e3600>;
		compatible = "fixed-clock";
		phandle = <0x2c>;
	};

	gmac0-rmii-refin-clock {
		clock-output-names = "gmac0_rmii_refin";
		#clock-cells = <0x00>;
		clock-frequency = <0x2faf080>;
		compatible = "fixed-clock";
		phandle = <0x43>;
	};

	chosen {
		linux,initrd-end = <0x00 0x46eb356a>;
		bootargs = "root=/dev/mmcblk1p4 rw console=tty0 console=ttyS0,115200 earlycon rootwait stmmaceth=chain_mode:1 selinux=0";
		boot-hartid = <0x01>;
		linux,initrd-start = <0x00 0x46100000>;
		stdout-path = "serial0:115200n8";
	};

	wm8960_mclk {
		#clock-cells = <0x00>;
		clock-frequency = <0x1770000>;
		compatible = "fixed-clock";
		phandle = <0xaf>;
	};

	gmac0-rgmii-rxin-clock {
		clock-output-names = "gmac0_rgmii_rxin";
		#clock-cells = <0x00>;
		clock-frequency = <0x7735940>;
		compatible = "fixed-clock";
		phandle = <0x44>;
	};

	cpus {
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		timebase-frequency = "\0=\t";

		cpu@1 {
			i-tlb-sets = <0x01>;
			clock-names = "cpu";
			cpu-supply = <0x04>;
			clocks = <0x03 0x01>;
			d-cache-block-size = <0x40>;
			device_type = "cpu";
			compatible = "sifive,u74-mc\0riscv";
			mmu-type = "riscv,sv39";
			d-cache-size = <0x8000>;
			next-level-cache = <0x01>;
			i-cache-size = <0x8000>;
			reg = <0x01>;
			phandle = <0x06>;
			d-cache-sets = <0x40>;
			i-cache-block-size = <0x40>;
			operating-points-v2 = <0x02>;
			i-cache-sets = <0x40>;
			d-tlb-size = <0x28>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			i-tlb-size = <0x28>;
			d-tlb-sets = <0x01>;
			#cooling-cells = <0x02>;

			interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <0x01>;
				phandle = <0x12>;
				interrupt-controller;
			};
		};

		cpu@4 {
			i-tlb-sets = <0x01>;
			clock-names = "cpu";
			cpu-supply = <0x04>;
			clocks = <0x03 0x01>;
			d-cache-block-size = <0x40>;
			device_type = "cpu";
			compatible = "sifive,u74-mc\0riscv";
			mmu-type = "riscv,sv39";
			d-cache-size = <0x8000>;
			next-level-cache = <0x01>;
			i-cache-size = <0x8000>;
			reg = <0x04>;
			phandle = <0x09>;
			d-cache-sets = <0x40>;
			i-cache-block-size = <0x40>;
			operating-points-v2 = <0x02>;
			i-cache-sets = <0x40>;
			d-tlb-size = <0x28>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			i-tlb-size = <0x28>;
			d-tlb-sets = <0x01>;
			#cooling-cells = <0x02>;

			interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <0x01>;
				phandle = <0x15>;
				interrupt-controller;
			};
		};

		cpu-map {

			cluster0 {

				core3 {
					cpu = <0x08>;
				};

				core1 {
					cpu = <0x06>;
				};

				core4 {
					cpu = <0x09>;
				};

				core2 {
					cpu = <0x07>;
				};

				core0 {
					cpu = <0x05>;
				};
			};
		};

		cpu@2 {
			i-tlb-sets = <0x01>;
			clock-names = "cpu";
			cpu-supply = <0x04>;
			clocks = <0x03 0x01>;
			d-cache-block-size = <0x40>;
			device_type = "cpu";
			compatible = "sifive,u74-mc\0riscv";
			mmu-type = "riscv,sv39";
			d-cache-size = <0x8000>;
			next-level-cache = <0x01>;
			i-cache-size = <0x8000>;
			reg = <0x02>;
			phandle = <0x07>;
			d-cache-sets = <0x40>;
			i-cache-block-size = <0x40>;
			operating-points-v2 = <0x02>;
			i-cache-sets = <0x40>;
			d-tlb-size = <0x28>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			i-tlb-size = <0x28>;
			d-tlb-sets = <0x01>;
			#cooling-cells = <0x02>;

			interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <0x01>;
				phandle = <0x13>;
				interrupt-controller;
			};
		};

		cpu@0 {
			device_type = "cpu";
			compatible = "sifive,s7\0riscv";
			status = "disabled";
			next-level-cache = <0x01>;
			i-cache-size = <0x4000>;
			reg = <0x00>;
			phandle = <0x05>;
			i-cache-block-size = <0x40>;
			i-cache-sets = <0x40>;
			riscv,isa = "rv64imac_zba_zbb";

			interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <0x01>;
				phandle = <0x11>;
				interrupt-controller;
			};
		};

		cpu@3 {
			i-tlb-sets = <0x01>;
			clock-names = "cpu";
			cpu-supply = <0x04>;
			clocks = <0x03 0x01>;
			d-cache-block-size = <0x40>;
			device_type = "cpu";
			compatible = "sifive,u74-mc\0riscv";
			mmu-type = "riscv,sv39";
			d-cache-size = <0x8000>;
			next-level-cache = <0x01>;
			i-cache-size = <0x8000>;
			reg = <0x03>;
			phandle = <0x08>;
			d-cache-sets = <0x40>;
			i-cache-block-size = <0x40>;
			operating-points-v2 = <0x02>;
			i-cache-sets = <0x40>;
			d-tlb-size = <0x28>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			i-tlb-size = <0x28>;
			d-tlb-sets = <0x01>;
			#cooling-cells = <0x02>;

			interrupt-controller {
				compatible = "riscv,cpu-intc";
				#interrupt-cells = <0x01>;
				phandle = <0x14>;
				interrupt-controller;
			};
		};
	};

	__symbols__ {
		i2c3 = "/soc/i2c@12030000";
		pwm = "/soc/pwm@120d0000";
		i2stx1 = "/soc/i2s@120c0000";
		sndi2s0 = "/snd-card1/simple-audio-card,dai-link@0/cpu";
		dsi0_output = "/soc/mipi@295d0000/ports/port@0/endpoint@0";
		i2srx = "/soc/i2s@100e0000";
		sys_syscon = "/soc/syscon@13030000";
		rgb_output = "/rgb-output";
		U74_1 = "/cpus/cpu@1";
		hdmi_in_lcdc = "/soc/hdmi@29590000/port/endpoint@0";
		clint = "/soc/timer@2000000";
		aongpio = "/soc/pinctrl@17020000";
		dc_out_dpi2 = "/soc/dc8200@29400000/port/endpoint@2";
		cpu_opp = "/opp-table-0";
		ispcrg = "/soc/clock-controller@19810000";
		spi2 = "/soc/spi@10080000";
		dsi1_output = "/soc/mipi@295d0000/ports/port@0/endpoint@1";
		crypto = "/soc/crypto@16000000";
		axp15060 = "/soc/i2c@12050000/pmic@36";
		stg_syscon = "/soc/syscon@10240000";
		pdm = "/soc/pdm@100d0000";
		i2c1 = "/soc/i2c@10040000";
		pciephy0 = "/soc/phy@10210000";
		osc = "/oscillator";
		gmac0 = "/soc/ethernet@16030000";
		cpu1_intc = "/cpus/cpu@1/interrupt-controller";
		hdmi_0p9 = "/soc/i2c@12050000/pmic@36/regulators/ALDO5";
		mclk_ext = "/mclk-ext-clock";
		qspi = "/soc/spi@13010000";
		dc_out_dpi0 = "/soc/dc8200@29400000/port/endpoint@0";
		ccache = "/soc/cache-controller@2010000";
		csi2rx0_from_ov4689 = "/soc/vin_sysctl@19800000/ports/port@1/endpoint@2";
		nor_flash = "/soc/spi@13010000/flash@0";
		gpu = "/soc/gpu@18000000";
		spi0 = "/soc/spi@10060000";
		sfctemp = "/soc/temperature-sensor@120e0000";
		syscrg = "/soc/clock-controller@13020000";
		tinker_ft5406 = "/soc/i2c@10050000/tinker_ft5406@38";
		pwmdac_codec = "/pwmdac-codec";
		mmc1 = "/soc/mmc@16020000";
		vpu_dec = "/soc/vpu_dec@130a0000";
		aoncrg = "/soc/clock-controller@17000000";
		i2srx_pins = "/soc/pinctrl@13040000/i2srx-0";
		csi2rx = "/soc/csi-bridge@19800000";
		stmmac_axi_setup = "/stmmac-axi-config";
		uart4 = "/soc/serial@12010000";
		jpu = "/soc/jpu@13090000";
		stgcrg = "/soc/clock-controller@10230000";
		sdma = "/soc/dma-controller@16008000";
		phy1 = "/soc/ethernet@16040000/mdio/ethernet-phy@1";
		cpu_alert0 = "/thermal-zones/cpu-thermal/trips/cpu_alert0";
		aon_syscon = "/soc/syscon@17010000";
		dma = "/soc/dma-controller@16050000";
		i2stx1_pins = "/soc/pinctrl@13040000/i2stx1-0";
		cpu0_intc = "/cpus/cpu@0/interrupt-controller";
		mipi_in = "/dsi-output/ports/port@0/endpoint";
		imx219 = "/soc/i2c@12060000/imx219@10";
		panel_out0 = "/soc/i2c@10050000/seeed_plane_i2c@45/port/endpoint";
		dc8200 = "/soc/dc8200@29400000";
		pcie_intc0 = "/soc/pcie@940000000/interrupt-controller";
		uart2 = "/soc/serial@10020000";
		sndcpu0 = "/snd-card3/simple-audio-card,dai-link@0/cpu";
		imx708_to_csi2rx0 = "/soc/i2c@12060000/imx708@1a/port/endpoint";
		i2c6 = "/soc/i2c@12060000";
		display = "/display-subsystem";
		imx708 = "/soc/i2c@12060000/imx708@1a";
		pcie0 = "/soc/pcie@940000000";
		mailbox_contrl0 = "/soc/mailbox@13060000";
		pwmdac = "/soc/pwmdac@100b0000";
		hdmi_1p8 = "/soc/i2c@12050000/pmic@36/regulators/ALDO3";
		emmc_vdd = "/soc/i2c@12050000/pmic@36/regulators/aldo4";
		U74_4 = "/cpus/cpu@4";
		gmac0_rmii_refin = "/gmac0-rmii-refin-clock";
		mmc1_pins = "/soc/pinctrl@13040000/mmc1-0";
		spi5 = "/soc/spi@12090000";
		mipi_dphy = "/soc/mipi-dphy@295e0000";
		uart0 = "/soc/serial@10000000";
		i2c2_pins = "/soc/pinctrl@13040000/i2c2-0";
		e24_mem = "/reserved-memory/e24@c0000000";
		i2c4 = "/soc/i2c@12040000";
		vdd_cpu = "/soc/i2c@12050000/pmic@36/regulators/dcdc2";
		xrp = "/soc/xrp@10230000";
		pllclk = "/soc/syscon@13030000/clock-controller";
		spdif = "/soc/spdif@100a0000";
		U74_2 = "/cpus/cpu@2";
		mipi_0p9 = "/soc/i2c@12050000/pmic@36/regulators/ALDO1";
		can0 = "/soc/can@130d0000";
		rng = "/soc/rng@1600c000";
		pwrc = "/soc/power-controller@17030000";
		rtc_osc = "/rtc-oscillator";
		spi3 = "/soc/spi@12070000";
		gmac0_rgmii_rxin = "/gmac0-rgmii-rxin-clock";
		ov4689 = "/soc/i2c@12060000/ov4689@36";
		i2c2 = "/soc/i2c@10050000";
		pciephy1 = "/soc/phy@10220000";
		S7_0 = "/cpus/cpu@0";
		i2stx0 = "/soc/i2s@120b0000";
		dc_out = "/soc/dc8200@29400000/port";
		dsi_in_port = "/soc/mipi@295d0000/ports/port@1/endpoint";
		mailbox_client0 = "/mailbox_client";
		mmc0_pins = "/soc/pinctrl@13040000/mmc0-0";
		gmac1 = "/soc/ethernet@16040000";
		tda988x_pin = "/tda988x_pin";
		pwmdac_pins = "/soc/pinctrl@13040000/pwmdac-0";
		dc_out_dpi1 = "/soc/dc8200@29400000/port/endpoint@1";
		spi_dev0 = "/soc/spi@10060000/spi@0";
		i2stx_bclk_ext = "/i2stx-bclk-ext-clock";
		spi1 = "/soc/spi@10070000";
		usbphy0 = "/soc/phy@10200000";
		i2stx_lrck_ext = "/i2stx-lrck-ext-clock";
		i2c0 = "/soc/i2c@10030000";
		vpu_enc = "/soc/vpu_enc@130b0000";
		hdmi_pins = "/soc/pinctrl@13040000/hdmi-0";
		cpu4_intc = "/cpus/cpu@4/interrupt-controller";
		imx219_to_csi2rx0 = "/soc/i2c@12060000/imx219@10/port/endpoint";
		voutcrg = "/soc/clock-controller@295c0000";
		uart5 = "/soc/serial@12020000";
		co_process = "/soc/e24@6e210000";
		ac108_mclk = "/ac108_mclk";
		dssctrl = "/soc/dssctrl@295B0000";
		sf_dpi_output = "/dsi-output/ports/port@1/endpoint";
		vin_sysctl = "/soc/vin_sysctl@19800000";
		dvp_clk = "/dvp-clock";
		mmc0 = "/soc/mmc@16010000";
		usb0 = "/soc/usb@10100000";
		i2c0_pins = "/soc/pinctrl@13040000/i2c0-0";
		dsi_output = "/dsi-output";
		pcie1_pins = "/soc/pinctrl@13040000/pcie1-0";
		panel_out1 = "/soc/i2c@10050000/panel_radxa@19/port/endpoint";
		pcie_intc1 = "/soc/pcie@9c0000000/interrupt-controller";
		uart3 = "/soc/serial@12000000";
		usb_cdns3 = "/soc/usb@10100000/usb@0";
		hdmi_input0 = "/rgb-output/ports/port@0/endpoint@0";
		xrp_reserved = "/reserved-memory/xrpbuffer@f0000000";
		i2srx_bclk_ext = "/i2srx-bclk-ext-clock";
		csi_phy = "/soc/phy@19820000";
		phy0 = "/soc/ethernet@16030000/mdio/ethernet-phy@0";
		sound3 = "/snd-card3";
		gmac1_rmii_refin = "/gmac1-rmii-refin-clock";
		spi0_pins = "/soc/pinctrl@13040000/spi0-0";
		cpu3_intc = "/cpus/cpu@3/interrupt-controller";
		i2c6_pins = "/soc/pinctrl@13040000/i2c6-0";
		clk_ext_camera = "/clk-ext-camera";
		pcie1 = "/soc/pcie@9c0000000";
		ov4689_to_csi2rx0 = "/soc/i2c@12060000/ov4689@36/port/endpoint";
		i2srx_lrck_ext = "/i2srx-lrck-ext-clock";
		wm8960_mclk = "/wm8960_mclk";
		tdm_pins = "/soc/pinctrl@13040000/tdm-0";
		plic = "/soc/interrupt-controller@c000000";
		spi6 = "/soc/spi@120a0000";
		pwm_pins = "/soc/pinctrl@13040000/pwm-0";
		tdm = "/soc/tdm@10090000";
		uart1 = "/soc/serial@10010000";
		hdmi = "/soc/hdmi@29590000";
		i2srx_mst = "/soc/i2srx_mst@100e0000";
		hdmi_in = "/soc/hdmi@29590000/port";
		sound1 = "/snd-card1";
		i2c5 = "/soc/i2c@12050000";
		mipi_dsi = "/soc/mipi@295d0000";
		hdmitx0_pixelclk = "/hdmitx0-pixel-clock";
		sysgpio = "/soc/pinctrl@13040000";
		pcie0_pins = "/soc/pinctrl@13040000/pcie0-0";
		gmac1_rgmii_rxin = "/gmac1-rgmii-rxin-clock";
		csi2rx0_from_imx219 = "/soc/vin_sysctl@19800000/ports/port@1/endpoint@0";
		U74_3 = "/cpus/cpu@3";
		can1 = "/soc/can@130e0000";
		vcc_3v3 = "/soc/i2c@12050000/pmic@36/regulators/dcdc1";
		rtc = "/soc/rtc@17040000";
		tdm_ext = "/tdm-ext-clock";
		spi4 = "/soc/spi@12080000";
		uart0_pins = "/soc/pinctrl@13040000/uart0-0";
		cpu2_intc = "/cpus/cpu@2/interrupt-controller";
		mclk_ext_pins = "/soc/pinctrl@13040000/mclk-ext-0";
		i2c5_pins = "/soc/pinctrl@13040000/i2c5-0";
		csi2rx0_from_imx708 = "/soc/vin_sysctl@19800000/ports/port@1/endpoint@1";
	};

	reserved-memory {
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;

		opensbi@40000000 {
			reg = <0x00 0x40000000 0x00 0x80000>;
			phandle = <0xb0>;
			no-map;
		};

		linux,cma {
			linux,cma-default;
			alignment = <0x00 0x1000>;
			alloc-ranges = <0x00 0x70000000 0x00 0x60000000>;
			compatible = "shared-dma-pool";
			size = <0x00 0x60000000>;
			reusable;
		};

		e24@c0000000 {
			reg = <0x00 0x6ce00000 0x00 0x1600000>;
			phandle = <0x5b>;
		};

		xrpbuffer@f0000000 {
			reg = <0x00 0x69c00000 0x00 0x1ffffff 0x00 0x6bc00000 0x00 0x1000 0x00 0x6bc01000 0x00 0xfff000 0x00 0x6cc00000 0x00 0x1000>;
			phandle = <0xab>;
		};
	};

	i2srx-bclk-ext-clock {
		clock-output-names = "i2srx_bclk_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0xbb8000>;
		compatible = "fixed-clock";
		phandle = <0x23>;
	};
};
