/dts-v1/;

#define CLK_COREPLL     0
#define CLK_DDRPLL      1
#define CLK_GEMGXLPLL   2
#define CLK_DVFSCOREPLL 3
#define CLK_HFPCLKPLL   4
#define CLK_CLTXPLL     5
#define CLK_TLCLK       6
#define CLK_PCLK        7
#define CLK_PCIE_AUX    8

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", "sifive,fu740";
	model = "SiFive HiFive Unmatched";

	aliases {
		serial0 = "/soc/serial@10010000";
		serial1 = "/soc/serial@10011000";
	};

	chosen {
		stdout-path = "serial0";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <1000000>;

		cpu0: cpu@0 {
			compatible = "sifive,bullet0", "riscv";
			device_type = "cpu";
			i-cache-block-size = <64>;
			i-cache-sets = <128>;
			i-cache-size = <16384>;
			next-level-cache = <&ccache>;
			reg = <0>;
			riscv,isa = "rv64imac";
			status = "disabled";

			cpu0_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};

		cpu1: cpu@1 {
			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
			device_type = "cpu";
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			i-cache-block-size = <64>;
			i-cache-sets = <128>;
			i-cache-size = <32768>;
			i-tlb-sets = <1>;
			i-tlb-size = <40>;
			d-tlb-sets = <1>;
			d-tlb-size = <40>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			reg = <1>;
			riscv,isa = "rv64imafdc";
			tlb-split;

			cpu1_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};

		cpu2: cpu@2 {
			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
			device_type = "cpu";
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			i-cache-block-size = <64>;
			i-cache-sets = <128>;
			i-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <40>;
			i-tlb-sets = <1>;
			i-tlb-size = <40>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			reg = <2>;
			riscv,isa = "rv64imafdc";
			tlb-split;

			cpu2_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};

		cpu3: cpu@3 {
			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
			device_type = "cpu";
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			i-cache-block-size = <64>;
			i-cache-sets = <128>;
			i-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <40>;
			i-tlb-sets = <1>;
			i-tlb-size = <40>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			reg = <3>;
			riscv,isa = "rv64imafdc";
			tlb-split;

			cpu3_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};

		cpu4: cpu@4 {
			compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
			device_type = "cpu";
			d-cache-block-size = <64>;
			d-cache-sets = <64>;
			d-cache-size = <32768>;
			i-cache-block-size = <64>;
			i-cache-sets = <128>;
			i-cache-size = <32768>;
			d-tlb-sets = <1>;
			d-tlb-size = <40>;
			i-tlb-sets = <1>;
			i-tlb-size = <40>;
			mmu-type = "riscv,sv39";
			next-level-cache = <&ccache>;
			reg = <4>;
			riscv,isa = "rv64imafdc";
			tlb-split;

			cpu4_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "riscv,cpu-intc";
				interrupt-controller;
			};
		};
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		plic: interrupt-controller@c000000 {
			#interrupt-cells = <1>;
			#address-cells = <0>;
			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
			reg = <0x00 0xc000000 0x00 0x4000000>;
			riscv,ndev = <69>;
			interrupt-controller;
			interrupts-extended = <&cpu0_intc 0xffffffff>,
                                  <&cpu1_intc 0xffffffff>,
                                  <&cpu1_intc 0x09>,
                                  <&cpu2_intc 0xffffffff>,
                                  <&cpu2_intc 0x09>,
                                  <&cpu3_intc 0xffffffff>,
                                  <&cpu3_intc 0x09>,
                                  <&cpu4_intc 0xffffffff>,
                                  <&cpu4_intc 0x09>;
		};

		prci: clock-controller@10000000 {
			compatible = "sifive,fu740-c000-prci";
			reg = <0x00 0x10000000 0x00 0x1000>;
			clocks = <&clk_hfclk>, <&clk_rtcclk>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		uart0: serial@10010000 {
			compatible = "sifive,fu740-c000-uart", "sifive,uart0";
			reg = <0x00 0x10010000 0x00 0x1000>;
			interrupt-parent = <&plic>;
			interrupts = <39>;
			clocks = <&prci CLK_PCLK>;
			status = "okay";
		};

		uart1: serial@10011000 {
			compatible = "sifive,fu740-c000-uart", "sifive,uart0";
			reg = <0x00 0x10011000 0x00 0x1000>;
			interrupt-parent = <&plic>;
			interrupts = <40>;
			clocks = <&prci CLK_PCLK>;
			status = "disabled";
		};

		ccache: cache-controller@2010000 {
			compatible = "sifive,fu740-c000-ccache", "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-sets = <2048>;
			cache-size = <0x200000>;
			cache-unified;
			interrupt-parent = <&plic>;
			interrupts = <0x13>, <0x15>, <0x16>, <0x14>;
			reg = <0x00 0x2010000 0x00 0x1000>;
		};

		pwm0: pwm@10020000 {
			compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
			reg = <0x00 0x10020000 0x00 0x1000>;
			interrupt-parent = <&plic>;
			interrupts = <44>, <45>, <46>, <47>;
			clocks = <&prci CLK_PCLK>;
			#pwm-cells = <3>;
			status = "okay";
		};

		pwm1: pwm@10021000 {
			compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
			reg = <0x00 0x10021000 0x00 0x1000>;
			interrupt-parent = <&plic>;
			interrupts = <48>, <49>, <50>, <51>;
			clocks = <&prci CLK_PCLK>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		i2c0: i2c@10030000 {
			compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
			reg = <0x00 0x10030000 0x00 0x1000>;
			interrupt-parent = <&plic>;
			interrupts = <52>;
			clocks = <&prci CLK_PCLK>;
			reg-shift = <2>;
			reg-io-width = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "okay";
        };

		i2c1: i2c@10031000 {
			compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
			reg = <0x00 0x10031000 0x00 0x1000>;
			interrupt-parent = <&plic>;
			interrupts = <53>;
			clocks = <&prci CLK_PCLK>;
			reg-shift = <2>;
			reg-io-width = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00 0x80000000 0x04 0x00>;
	};

	leds: pwmleds {
		compatible = "pwm-leds";

		green-d12 {
			label = "green:d12";
			pwms = <&pwm0 0 7812500 0x01>;
			active-low = <1>;
			max-brightness = <255>;
			linux,default-trigger = "none";
		};

		green-d2 {
			label = "green:d2";
			pwms = <&pwm0 1 7812500 0x01>;
			active-low = <1>;
			max-brightness = <255>;
			linux,default-trigger = "none";
		};

		red-d2 {
			label = "red:d2";
			pwms = <&pwm0 2 7812500 0x01>;
			active-low = <0x01>;
			max-brightness = <0xff>;
			linux,default-trigger = "none";
		};

		blue-d2 {
			label = "blue:d2";
			pwms = <&pwm0 3 7812500 0x01>;
			active-low = <1>;
			max-brightness = <255>;
			linux,default-trigger = "none";
		};
	};

	clk_hfclk: hfclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		clock-output-names = "hfclk";
	};

	clk_rtcclk: rtcclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <1000000>;
		clock-output-names = "rtcclk";
	};
};
