use tock_registers::{register_bitfields, register_structs, registers::ReadWrite};

register_bitfields! {
    u32,
    pub MTLOMR [
        CNTCLR  OFFSET(9)   NUMBITS(1)  [],
        CNTPRST OFFSET(8)   NUMBITS(1)  [],
        SCHALG  OFFSET(5)   NUMBITS(2)  [
            AlgWeightedRR = 0b00,
            AlgStrictPrio = 0b11,
        ],
        RAA     OFFSET(2)   NUMBITS(1)  [
            AlgStrictPrio   = 0,
            AlgWeightedPrio = 1
        ],
        DTXSTS  OFFSET(1)   NUMBITS(1)  [],
    ],

    pub MTLTXQiOMR [
        TQS     OFFSET(16)  NUMBITS(4)  [],
        TTC     OFFSET(4)   NUMBITS(3)  [],
        TXQEN   OFFSET(2)   NUMBITS(2)  [
            Disable     = 0b00,
            EnableAv    = 0b01,
            Enable      = 0b11,
        ],
        TSF     OFFSET(1)   NUMBITS(1)  [],
        FTQ     OFFSET(0)   NUMBITS(1)  [],
    ],

    pub MTLRXQiOMR [
        RQS         OFFSET(20)  NUMBITS(4)  [],
        /// Threshold for deactivating flow control
        RFD         OFFSET(14)  NUMBITS(3)  [
            FullMinus1K     = 0,
            FullMinus1_5K   = 1,
            FullMinus2K     = 2,
            FullMinus2_5K   = 3,
            FullMinus3K     = 4,
            FullMinus3_5K   = 5
        ],
        /// Threshold for activating flow control. See [RFD].
        RFA         OFFSET(8)   NUMBITS(3)  [],
        /// Enable hardware flow control. When set, the flow control signal operation, based on the
        /// fill-level of the Rx queue, is enabled.
        EHFC        OFFSET(7)   NUMBITS(1)  [],
        /// Disable dropping of TCP/IP checksum error packets
        DIS_TCP_EF  OFFSET(6)   NUMBITS(1)  [],
        /// Receive queue store and forward. When set, the Ethernet peripheral reads a packet from
        /// the Rx queue only after the complete packet has been written to it, ignoring the RTC
        /// field.
        RSF         OFFSET(5)   NUMBITS(1)  [],
        /// Forward error packets. When set, the Rx queue does not drop the packets with CRC
        /// errors, watchdog timeouts, overflows and receive errors.
        FEP         OFFSET(4)   NUMBITS(1)  [],
        /// Forward undersized good packets. When set, the Rx queue does not drop packets with no
        /// errors, but with a length of less than 64 bytes.
        FUP         OFFSET(3)   NUMBITS(1)  [],
        /// Rx threshold level
        RTC         OFFSET(0)   NUMBITS(2)  [
            Threshold64     = 0b00,
            Threshold32     = 0b01,
            Threshold96     = 0b10,
            Threshold128    = 0b11,
        ],
    ],
}

register_structs! {
    pub MtlRegs {
        /// MTL operating mode register
        (0x000 => pub MTLOMR: ReadWrite<u32, MTLOMR::Register>),
        (0x004 => _0),
        /// Interrupt status register
        (0x020 => pub MTLISR: ReadWrite<u32>),
        (0x024 => _1),
        /// Tx queue 0 operating mode register
        (0x100 => pub MTLTXQ0OMR: ReadWrite<u32, MTLTXQiOMR::Register>),
        /// Tx queue 0 underflow register
        (0x104 => pub MTLTXQ0UR: ReadWrite<u32>),
        /// Tx queue 0 debug register
        (0x108 => pub MTLTXQ0DR: ReadWrite<u32>),
        (0x10C => _2),
        /// Tx queue 0 ETS status register
        (0x114 => pub MTLTXQ0ESR: ReadWrite<u32>),
        /// Tx queue 0 quantum weight register
        (0x118 => pub MTLTXQ0QWR: ReadWrite<u32>),
        (0x11C => _3),
        /// Queue 0 interrupt control status register
        (0x12C => pub MTLQ0ICSR: ReadWrite<u32>),
        /// Rx queue 0 operating mode register
        (0x130 => pub MTLRXQ0OMR: ReadWrite<u32, MTLRXQiOMR::Register>),
        /// Rx queue 0 missed packet and overflow counter register
        (0x134 => pub MTLRXQ0MPOCR: ReadWrite<u32>),
        /// Rx queue 0 debug register
        (0x138 => pub MTLRXQ0DR: ReadWrite<u32>),
        /// Rx queue 0 control register
        (0x13C => pub MTLRXQ0CR: ReadWrite<u32>),
        /// Tx queue 1 operating mode register
        (0x140 => pub MTLTXQ1OMR: ReadWrite<u32>),
        /// Tx queue 1 underflow register
        (0x144 => pub MTLTXQ1UR: ReadWrite<u32>),
        /// Tx queue 1 debug register
        (0x148 => pub MTLTXQ1DR: ReadWrite<u32>),
        (0x14C => _4),
        /// Tx queue 1 ETS control register
        (0x150 => pub MTLTXQ1ECR: ReadWrite<u32>),
        /// Tx queue 1 ETS status register
        (0x154 => pub MTLTXQ1ESR: ReadWrite<u32>),
        /// Tx queue 1 quantum weight register
        (0x158 => pub MTLTXQ1QWR: ReadWrite<u32>),
        /// Tx queue 1 send slope credit register
        (0x15C => pub MTLTXQ1SSCR: ReadWrite<u32>),
        /// Tx queue 1 hiCredit register
        (0x160 => pub MTLTXQ1HCR: ReadWrite<u32>),
        /// Tx queue 1 loCredit register
        (0x164 => pub MTLTXQ1LCR: ReadWrite<u32>),
        (0x168 => _5),
        /// Queue 1 interrupt control status register
        (0x16C => pub MTLQ1ICSR: ReadWrite<u32>),
        /// Rx queue 1 operating mode register
        (0x170 => pub MTLRXQ1OMR: ReadWrite<u32>),
        /// Rx queue 1 missed packet and overflow counter register
        (0x174 => pub MTLRXQ1MPOCR: ReadWrite<u32>),
        /// Rx queue 1 debug register
        (0x178 => pub MTLRXQ1DR: ReadWrite<u32>),
        /// Rx queue 1 control register
        (0x17C => pub MTLRXQ1CR: ReadWrite<u32>),
        (0x180 => _6),
        (0x400 => @END),
    }
}
