//! Bus device interfaces
use core::ops::Range;

use alloc::sync::Arc;
use yggdrasil_abi::error::Error;

use crate::{device::Device, dma::DmaAllocator};

/// Bus device which provides an interconnect between two or more address spaces.
///
/// NOTE: only memory-to-memory busses are supported via this trait as of yet.
pub trait Bus: Device {
    /// Translates a range of bus addresses into the addresses represented in host memory.
    ///
    /// NOTE: nested busses with bus1 -> bus0 -> host translation schemes are not yet supported.
    fn map_range(&self, bus_range: Range<u64>) -> Option<Range<u64>>;

    /// TODO: document
    fn create_dma_allocator(self: Arc<Self>) -> Result<Arc<dyn DmaAllocator>, Error> {
        Err(Error::NotImplemented)
    }
}
