/dts-v1/;

#include <riscv64/jh7110-pinctrl.h>

/ {
	compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
	#address-cells = <0x02>;
	#size-cells = <0x02>;
	model = "StarFive VisionFive 2 v1.3B";

	cpus {
		#address-cells = <0x01>;
		#size-cells = <0x00>;
		timebase-frequency = "", "=\t";

		cpu0: cpu@0 {
			compatible = "sifive,s7", "riscv";
			reg = <0x00>;
			device_type = "cpu";
			i-cache-block-size = <0x40>;
			i-cache-sets = <0x40>;
			i-cache-size = <0x4000>;
			next-level-cache = <0x01>;
			riscv,isa = "rv64imac_zba_zbb";
			status = "disabled";
			phandle = <0x05>;

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <0x01>;
				phandle = <0x11>;
			};
		};

		cpu1: cpu@1 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <0x01>;
			d-cache-block-size = <0x40>;
			d-cache-sets = <0x40>;
			d-cache-size = <0x8000>;
			d-tlb-sets = <0x01>;
			d-tlb-size = <0x28>;
			device_type = "cpu";
			i-cache-block-size = <0x40>;
			i-cache-sets = <0x40>;
			i-cache-size = <0x8000>;
			i-tlb-sets = <0x01>;
			i-tlb-size = <0x28>;
			mmu-type = "riscv,sv39";
			next-level-cache = <0x01>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			operating-points-v2 = <0x02>;
			clocks = <&syscrg 0x01>;
			clock-names = "cpu";
			#cooling-cells = <0x02>;
			cpu-supply = <0x04>;
			phandle = <0x06>;

			cpu1_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <0x01>;
				phandle = <0x12>;
			};
		};

		cpu2: cpu@2 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <0x02>;
			d-cache-block-size = <0x40>;
			d-cache-sets = <0x40>;
			d-cache-size = <0x8000>;
			d-tlb-sets = <0x01>;
			d-tlb-size = <0x28>;
			device_type = "cpu";
			i-cache-block-size = <0x40>;
			i-cache-sets = <0x40>;
			i-cache-size = <0x8000>;
			i-tlb-sets = <0x01>;
			i-tlb-size = <0x28>;
			mmu-type = "riscv,sv39";
			next-level-cache = <0x01>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			operating-points-v2 = <0x02>;
			clocks = <&syscrg 0x01>;
			clock-names = "cpu";
			#cooling-cells = <0x02>;
			cpu-supply = <0x04>;
			phandle = <0x07>;

			cpu2_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <0x01>;
				phandle = <0x13>;
			};
		};

		cpu3: cpu@3 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <0x03>;
			d-cache-block-size = <0x40>;
			d-cache-sets = <0x40>;
			d-cache-size = <0x8000>;
			d-tlb-sets = <0x01>;
			d-tlb-size = <0x28>;
			device_type = "cpu";
			i-cache-block-size = <0x40>;
			i-cache-sets = <0x40>;
			i-cache-size = <0x8000>;
			i-tlb-sets = <0x01>;
			i-tlb-size = <0x28>;
			mmu-type = "riscv,sv39";
			next-level-cache = <0x01>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			operating-points-v2 = <0x02>;
			clocks = <&syscrg 0x01>;
			clock-names = "cpu";
			#cooling-cells = <0x02>;
			cpu-supply = <0x04>;
			phandle = <0x08>;

			cpu3_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <0x01>;
				phandle = <0x14>;
			};
		};

		cpu4: cpu@4 {
			compatible = "sifive,u74-mc", "riscv";
			reg = <0x04>;
			d-cache-block-size = <0x40>;
			d-cache-sets = <0x40>;
			d-cache-size = <0x8000>;
			d-tlb-sets = <0x01>;
			d-tlb-size = <0x28>;
			device_type = "cpu";
			i-cache-block-size = <0x40>;
			i-cache-sets = <0x40>;
			i-cache-size = <0x8000>;
			i-tlb-sets = <0x01>;
			i-tlb-size = <0x28>;
			mmu-type = "riscv,sv39";
			next-level-cache = <0x01>;
			riscv,isa = "rv64imafdc_zba_zbb";
			tlb-split;
			operating-points-v2 = <0x02>;
			clocks = <&syscrg 0x01>;
			clock-names = "cpu";
			#cooling-cells = <0x02>;
			cpu-supply = <0x04>;
			phandle = <0x09>;

			cpu4_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <0x01>;
				phandle = <0x15>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
				core4 {
					cpu = <&cpu4>;
				};
			};
		};
	};

	clk_dvp_clk: dvp-clock {
		compatible = "fixed-clock";
		clock-output-names = "dvp_clk";
		#clock-cells = <0x00>;
		clock-frequency = <0x46cf710>;
		phandle = <0x4c>;
	};

	clk_gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
		compatible = "fixed-clock";
		clock-output-names = "gmac0_rgmii_rxin";
		#clock-cells = <0x00>;
		clock-frequency = <0x7735940>;
		phandle = <0x44>;
	};

	clk_gmac0_rmii_refin: gmac0-rmii-refin-clock {
		compatible = "fixed-clock";
		clock-output-names = "gmac0_rmii_refin";
		#clock-cells = <0x00>;
		clock-frequency = <0x2faf080>;
		phandle = <0x43>;
	};

	clk_gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
		compatible = "fixed-clock";
		clock-output-names = "gmac1_rgmii_rxin";
		#clock-cells = <0x00>;
		clock-frequency = <0x7735940>;
		phandle = <0x36>;
	};

	clk_gmac1_rmii_refin: gmac1-rmii-refin-clock {
		compatible = "fixed-clock";
		clock-output-names = "gmac1_rmii_refin";
		#clock-cells = <0x00>;
		clock-frequency = <0x2faf080>;
		phandle = <0x35>;
	};

	clk_hdmitx0_pixelclk: hdmitx0-pixel-clock {
		compatible = "fixed-clock";
		clock-output-names = "hdmitx0_pixelclk";
		#clock-cells = <0x00>;
		clock-frequency = <0x11b3dc40>;
		phandle = <0x4f>;
	};

	clk_i2srx_bclk_ext: i2srx-bclk-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "i2srx_bclk_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0xbb8000>;
		phandle = <0x23>;
	};

	clk_i2srx_lrck_ext: i2srx-lrck-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "i2srx_lrck_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0x2ee00>;
		phandle = <0x24>;
	};

	clk_i2stx_bclk_ext: i2stx-bclk-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "i2stx_bclk_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0xbb8000>;
		phandle = <0x31>;
	};

	clk_i2stx_lrck_ext: i2stx-lrck-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "i2stx_lrck_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0x2ee00>;
		phandle = <0x32>;
	};

	clk_mclk_ext: mclk-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "mclk_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0xbb8000>;
		phandle = <0x20>;
	};

	clk_osc: oscillator {
		compatible = "fixed-clock";
		clock-output-names = "osc";
		#clock-cells = <0x00>;
		clock-frequency = <0x16e3600>;
		phandle = <0x29>;
	};

	clk_rtc_osc: rtc-oscillator {
		compatible = "fixed-clock";
		clock-output-names = "rtc_osc";
		#clock-cells = <0x00>;
		clock-frequency = <0x8000>;
		phandle = <0x45>;
	};

	axi_cfg: stmmac-axi-config {
		snps,lpi_en;
		snps,wr_osr_lmt = <0x0f>;
		snps,rd_osr_lmt = <0x0f>;
		snps,blen = <0x100 0x80 0x40 0x20 0x00 0x00 0x00>;
		phandle = <0x3f>;
	};

	clk_tdm_ext: tdm-ext-clock {
		compatible = "fixed-clock";
		clock-output-names = "tdm_ext";
		#clock-cells = <0x00>;
		clock-frequency = <0x2ee0000>;
		phandle = <0x1d>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <0x10>;
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;

		clint: timer@2000000 {
			compatible = "starfive,jh7110-clint", "sifive,clint0";
			reg = <0x00 0x2000000 0x00 0x10000>;
			interrupts-extended = <&cpu0_intc 0x03>,
                                  <&cpu0_intc 0x07>,
                                  <&cpu1_intc 0x03>,
                                  <&cpu1_intc 0x07>,
                                  <&cpu2_intc 0x03>,
                                  <&cpu2_intc 0x07>,
                                  <&cpu3_intc 0x03>,
                                  <&cpu3_intc 0x07>,
                                  <&cpu4_intc 0x03>,
                                  <&cpu4_intc 0x07>;
			phandle = <0x6e>;
		};

		ccache: cache-controller@2010000 {
			compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
			reg = <0x00 0x2010000 0x00 0x4000 0x00 0x8000000 0x00 0x2000000 0x00 0xa000000 0x00 0x2000000>;
			interrupts = <0x01 0x03 0x04 0x02>;
			cache-block-size = <0x40>;
			cache-level = <0x02>;
			cache-sets = <0x800>;
			cache-size = <0x200000>;
			cache-unified;
			phandle = <0x01>;
		};

		plic: interrupt-controller@c000000 {
			compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
			reg = <0x00 0xc000000 0x00 0x4000000>;
			interrupts-extended = <&cpu0_intc 0x0b>,
                                  <&cpu1_intc 0x0b>,
                                  <&cpu1_intc 0x09>,
                                  <&cpu2_intc 0x0b>,
                                  <&cpu2_intc 0x09>,
                                  <&cpu3_intc 0x0b>,
                                  <&cpu3_intc 0x09>,
                                  <&cpu4_intc 0x0b>,
                                  <&cpu4_intc 0x09>;
			interrupt-controller;
			#interrupt-cells = <0x01>;
			#address-cells = <0x00>;
			riscv,ndev = <0x88>;
			phandle = <0x10>;
		};

		uart0: serial@10000000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00 0x10000000 0x00 0x10000>;
			clocks = <&syscrg 0x92>,
                     <&syscrg 0x91>;
			clock-names = "baudclk",
                          "apb_pclk";
			resets = <&syscrg 0x53>,
                     <&syscrg 0x54>;
			interrupts = <0x20>;
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			status = "okay";
			pinctrl-names = "default";
			pinctrl-0 = <&uart0_pins>;
			phandle = <0x6f>;
		};

		uart1: serial@10010000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00 0x10010000 0x00 0x10000>;
			clocks = <&syscrg 0x94>,
                     <&syscrg 0x93>;
			clock-names = "baudclk",
                          "apb_pclk";
			resets = <&syscrg 0x55>,
                     <&syscrg 0x56>;
			interrupts = <0x21>;
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			status = "okay";
            pinctrl-names = "default";
            pinctrl-0 = <&uart1_pins>;
			phandle = <0x70>;
		};

		uart2: serial@10020000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00 0x10020000 0x00 0x10000>;
			clocks = <&syscrg 0x96>,
                     <&syscrg 0x95>;
			clock-names = "baudclk",
                          "apb_pclk";
			resets = <&syscrg 0x57>,
                     <&syscrg 0x58>;
			interrupts = <0x22>;
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			status = "disabled";
			phandle = <0x71>;
		};

		stgcrg: clock-controller@10230000 {
			compatible = "starfive,jh7110-stgcrg";
			reg = <0x00 0x10230000 0x00 0x10000>;
			clocks = <&clk_osc>,
                     <&syscrg 0x36>,
                     <&syscrg 0x08>,
                     <&syscrg 0x5f>,
                     <&syscrg 0x02>,
                     <&syscrg 0x37>,
                     <&syscrg 0x06>,
                     <&syscrg 0x0b>;
			clock-names = "osc",
                          "hifi4_core",
                          "stg_axiahb",
                          "usb_125m",
                          "cpu_bus",
                          "hifi4_axi",
                          "nocstg_bus",
                          "apb_bus";
			#clock-cells = <0x01>;
			#reset-cells = <0x01>;
			phandle = <0x27>;
		};

		stg_syscon: syscon@10240000 {
			compatible = "starfive,jh7110-stg-syscon", "syscon";
			reg = <0x00 0x10240000 0x00 0x1000>;
			phandle = <0x26>;
		};

		uart3: serial@12000000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00 0x12000000 0x00 0x10000>;
			clocks = <&syscrg 0x98>,
                     <&syscrg 0x97>;
			clock-names = "baudclk",
                          "apb_pclk";
			resets = <&syscrg 0x59>,
                     <&syscrg 0x5a>;
			interrupts = <0x2d>;
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			status = "disabled";
			phandle = <0x82>;
		};

		uart4: serial@12010000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00 0x12010000 0x00 0x10000>;
			clocks = <&syscrg 0x9a>,
                     <&syscrg 0x99>;
			clock-names = "baudclk",
                          "apb_pclk";
			resets = <&syscrg 0x5b>,
                     <&syscrg 0x5c>;
			interrupts = <0x2e>;
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			status = "disabled";
			phandle = <0x83>;
		};

		uart5: serial@12020000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x00 0x12020000 0x00 0x10000>;
			clocks = <&syscrg 0x9c>,
                     <&syscrg 0x9b>;
			clock-names = "baudclk",
                          "apb_pclk";
			resets = <&syscrg 0x5d>,
                     <&syscrg 0x5e>;
			interrupts = <0x2f>;
			reg-io-width = <0x04>;
			reg-shift = <0x02>;
			status = "disabled";
			phandle = <0x84>;
		};

		syscrg: clock-controller@13020000 {
			compatible = "starfive,jh7110-syscrg";
			reg = <0x00 0x13020000 0x00 0x10000>;
			clocks = <&clk_osc>,
                     <&clk_gmac1_rmii_refin>,
                     <&clk_gmac1_rgmii_rxin>,
                     <&clk_i2stx_bclk_ext>,
                     <&clk_i2stx_lrck_ext>,
                     <&clk_i2srx_bclk_ext>,
                     <&clk_i2srx_lrck_ext>,
                     <&clk_tdm_ext>,
                     <&clk_mclk_ext>,
                     <&pll 0x00>,
                     <&pll 0x01>,
                     <&pll 0x02>;
			clock-names = "osc",
                          "gmac1_rmii_refin",
                          "gmac1_rgmii_rxin",
                          "i2stx_bclk_ext",
                          "i2stx_lrck_ext",
                          "i2srx_bclk_ext",
                          "i2srx_lrck_ext",
                          "tdm_ext",
                          "mclk_ext",
                          "pll0_out",
                          "pll1_out",
                          "pll2_out";
			#clock-cells = <0x01>;
			#reset-cells = <0x01>;
			phandle = <0x03>;
		};

		sys_syscon: syscon@13030000 {
			compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
			reg = <0x00 0x13030000 0x00 0x1000>;
			phandle = <0x22>;

			pll: clock-controller {
				compatible = "starfive,jh7110-pll";
				clocks = <&clk_osc>;
				#clock-cells = <0x01>;
				phandle = <0x37>;
			};
		};

		sys_pinctrl: pinctrl@13040000 {
			compatible = "starfive,jh7110-sys-pinctrl";
			reg = <0x00 0x13040000 0x00 0x10000>;
			clocks = <&syscrg 0x70>;
			resets = <&syscrg 0x02>;
			interrupts = <0x56>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			gpio-controller;
			#gpio-cells = <0x02>;
			phandle = <0x1a>;

			uart0_pins: uart0-0 {
				phandle = <0x16>;

				tx-pins {
					// pinmux = <0xff140005>;
                    pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, GPOEN_ENABLE, GPI_NONE)>;
					bias-disable;
					drive-strength = <12>;
					input-disable;
					input-schmitt-disable;
					slew-rate = <0x00>;
				};

				rx-pins {
					// pinmux = <0xe000406>;
                    pinmux = <GPIOMUX(6, GPOUT_LOW, GPOEN_DISABLE, GPI_SYS_UART0_RX)>;
					bias-disable;
					drive-strength = <2>;
					input-enable;
					input-schmitt-enable;
					slew-rate = <0x00>;
				};
			};

            uart1_pins: uart1-0 {
                tx-pins {
                    pinmux = <GPIOMUX(63, GPOUT_SYS_UART1_TX, GPOEN_ENABLE, GPI_NONE)>;
                    bias-disable;
                    drive-strength = <12>;
                    input-disable;
                    input-schmitt-disable;
                    slew-rate = <0>;
                };
                rx-pins {
                    pinmux = <GPIOMUX(60, GPOUT_LOW, GPOEN_DISABLE, GPI_SYS_UART1_RX)>;
                    bias-disable;
                    drive-strength = <2>;
                    input-enable;
                    input-schmitt-enable;
                    slew-rate = <0>;
                };
            };
		};

		timer@13050000 {
			compatible = "starfive,jh7110-timer";
			reg = <0x00 0x13050000 0x00 0x10000>;
			interrupts = <0x45 0x46 0x47 0x48>;
			clocks = <&syscrg 0x7c>,
                     <&syscrg 0x7d>,
                     <&syscrg 0x7e>,
                     <&syscrg 0x7f>,
                     <&syscrg 0x80>;
			clock-names = "apb",
                          "ch0",
                          "ch1",
                          "ch2",
                          "ch3";
			resets = <&syscrg 0x75>,
                     <&syscrg 0x76>,
                     <&syscrg 0x77>,
                     <&syscrg 0x78>,
                     <&syscrg 0x79>;
			reset-names = "apb",
                          "ch0",
                          "ch1",
                          "ch2",
                          "ch3";
		};

		mailbox@13060000 {
			compatible = "starfive,mail_box";
			reg = <0x00 0x13060000 0x00 0x1000>;
			clocks = <&syscrg 0x71>;
			clock-names = "clk_apb";
			resets = <&syscrg 0x44>;
			reset-names = "mbx_rre";
			interrupts = <0x1a 0x1b>;
			#mbox-cells = <0x02>;
			status = "okay";
			phandle = <0x0d>;
		};

		watchdog@13070000 {
			compatible = "starfive,jh7110-wdt";
			reg = <0x00 0x13070000 0x00 0x10000>;
			clocks = <&syscrg 0x7a>,
                     <&syscrg 0x7b>;
			clock-names = "apb",
                          "core";
			resets = <&syscrg 0x6d>,
                     <&syscrg 0x6e>;
		};

		dma-controller@16008000 {
			compatible = "arm,pl080", "arm,primecell";
			arm,primecell-periphid = <0x41080>;
			reg = <0x00 0x16008000 0x00 0x4000>;
			interrupts = <0x1d>;
			clocks = <&stgcrg 0x0f>;
			clock-names = "apb_pclk";
			resets = <&stgcrg 0x03>;
			lli-bus-interface-ahb1;
			mem-bus-interface-ahb1;
			memcpy-burst-size = <0x100>;
			memcpy-bus-width = <0x20>;
			#dma-cells = <0x02>;
			phandle = <0x39>;
		};

		gmac0: ethernet@16030000 {
			compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
			reg = <0x00 0x16030000 0x00 0x10000>;
			clocks = <&aoncrg 0x03>,
                     <&aoncrg 0x02>,
                     <&syscrg 0x6d>,
                     <&aoncrg 0x06>,
                     <&syscrg 0x6f>;
			clock-names = "stmmaceth",
                          "pclk",
                          "ptp_ref",
                          "tx",
                          "gtx";
			resets = <&aoncrg 0x00>,
                     <&aoncrg 0x01>;
			reset-names = "stmmaceth",
                          "ahb";
			interrupts = <0x07 0x06 0x05>;
			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
			rx-fifo-depth = <0x800>;
			tx-fifo-depth = <0x800>;
			snps,multicast-filter-bins = <0x40>;
			snps,perfect-filter-entries = <0x100>;
			snps,fixed-burst;
			snps,no-pbl-x8;
			snps,force_thresh_dma_mode;
			snps,axi-config = <&axi_cfg>;
			snps,tso;
			snps,en-tx-lpi-clockgating;
			snps,txpbl = <0x10>;
			snps,rxpbl = <0x10>;
			starfive,syscon = <&aon_syscon 0x0c 0x12>;
			status = "okay";
			phy-handle = <&gmac0_phy>;
			phy-mode = "rgmii-id";
			starfive,tx-use-rgmii-clk;
			assigned-clocks = <&aoncrg 0x05>;
			assigned-clock-parents = <&aoncrg 0x04>;
			phandle = <0x9e>;

			mdio {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				compatible = "snps,dwmac-mdio";

				gmac0_phy: ethernet-phy@0 {
					reg = <0x00>;
					motorcomm,tx-clk-adj-enabled;
					motorcomm,tx-clk-100-inverted;
					motorcomm,tx-clk-1000-inverted;
					motorcomm,rx-clk-drv-microamp = <0xf82>;
					motorcomm,rx-data-drv-microamp = <0xb5e>;
					rx-internal-delay-ps = <0x5dc>;
					tx-internal-delay-ps = <0x5dc>;
					phandle = <0x41>;
				};
			};
		};

		gmac1: ethernet@16040000 {
			compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
			reg = <0x00 0x16040000 0x00 0x10000>;
			clocks = <&syscrg 0x62>,
                     <&syscrg 0x61>,
                     <&syscrg 0x66>,
                     <&syscrg 0x6a>,
                     <&syscrg 0x6b>;
			clock-names = "stmmaceth",
                          "pclk",
                          "ptp_ref",
                          "tx",
                          "gtx";
			resets = <&syscrg 0x42>,
                     <&syscrg 0x43>;
			reset-names = "stmmaceth",
                          "ahb";
			interrupts = <0x4e 0x4d 0x4c>;
			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
			rx-fifo-depth = <0x800>;
			tx-fifo-depth = <0x800>;
			snps,multicast-filter-bins = <0x40>;
			snps,perfect-filter-entries = <0x100>;
			snps,fixed-burst;
			snps,no-pbl-x8;
			snps,force_thresh_dma_mode;
			snps,axi-config = <&axi_cfg>;
			snps,tso;
			snps,en-tx-lpi-clockgating;
			snps,txpbl = <0x10>;
			snps,rxpbl = <0x10>;
			starfive,syscon = <&sys_syscon 0x90 0x02>;
			status = "okay";
			phy-handle = <&gmac1_phy>;
			phy-mode = "rgmii-id";
			starfive,tx-use-rgmii-clk;
			assigned-clocks = <&syscrg 0x69>;
			assigned-clock-parents = <&syscrg 0x65>;
			phandle = <0x9f>;

			mdio {
				#address-cells = <0x01>;
				#size-cells = <0x00>;
				compatible = "snps,dwmac-mdio";

				gmac1_phy: ethernet-phy@1 {
					reg = <0x00>;
					motorcomm,tx-clk-adj-enabled;
					motorcomm,tx-clk-100-inverted;
					motorcomm,rx-clk-drv-microamp = <0xf82>;
					motorcomm,rx-data-drv-microamp = <0xb5e>;
					rx-internal-delay-ps = <0x12c>;
					tx-internal-delay-ps = <0x00>;
					phandle = <0x42>;
				};
			};
		};

		axi_dma: dma-controller@16050000 {
			compatible = "starfive,jh7110-axi-dma";
			reg = <0x00 0x16050000 0x00 0x10000>;
			clocks = <&stgcrg 0x1b>,
                     <&stgcrg 0x1c>;
			clock-names = "core-clk",
                          "cfgr-clk";
			resets = <&stgcrg 0x05>,
                     <&stgcrg 0x06>;
			interrupts = <0x49>;
			#dma-cells = <0x01>;
			dma-channels = <0x04>;
			snps,dma-masters = <0x01>;
			snps,data-width = <0x03>;
			snps,block-size = <0x10000 0x10000 0x10000 0x10000>;
			snps,priority = <0x00 0x01 0x02 0x03>;
			snps,axi-max-burst-len = <0x10>;
			phandle = <0x1e>;
		};

		aoncrg: clock-controller@17000000 {
			compatible = "starfive,jh7110-aoncrg";
			reg = <0x00 0x17000000 0x00 0x10000>;
			clocks = <&clk_osc>,
                     <&clk_gmac0_rmii_refin>,
                     <&clk_gmac0_rgmii_rxin>,
                     <&syscrg 0x08>,
                     <&syscrg 0x0b>,
                     <&syscrg 0x6c>,
                     <&clk_rtc_osc>;
			clock-names = "osc",
                          "gmac0_rmii_refin",
                          "gmac0_rgmii_rxin",
                          "stg_axiahb",
                          "apb_bus",
                          "gmac0_gtxclk",
                          "rtc_osc";
			#clock-cells = <0x01>;
			#reset-cells = <0x01>;
			phandle = <0x3e>;
		};

		aon_syscon: syscon@17010000 {
			compatible = "starfive,jh7110-aon-syscon", "syscon";
			reg = <0x00 0x17010000 0x00 0x1000>;
			#power-domain-cells = <0x01>;
			phandle = <0x40>;
		};

		aon_pinctrl: pinctrl@17020000 {
			compatible = "starfive,jh7110-aon-pinctrl";
			reg = <0x00 0x17020000 0x00 0x10000>;
			resets = <&aoncrg 0x02>;
			interrupts = <0x55>;
			interrupt-controller;
			#interrupt-cells = <0x02>;
			gpio-controller;
			#gpio-cells = <0x02>;
			phandle = <0x62>;
		};

		pmu: power-controller@17030000 {
			compatible = "starfive,jh7110-pmu";
			reg = <0x00 0x17030000 0x00 0x10000>;
			interrupts = <0x6f>;
			#power-domain-cells = <0x01>;
			phandle = <0x38>;
		};

		rtc: rtc@17040000 {
			compatible = "starfive,jh7110-rtc";
			reg = <0x00 0x17040000 0x00 0x10000>;
			interrupts = <0x0a 0x0b 0x0c>;
			interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
			clocks = <&aoncrg 0x0a>,
                     <&aoncrg 0x0d>;
			clock-names = "pclk",
                          "cal_clk";
			resets = <&aoncrg 0x07>,
                     <&aoncrg 0x05>,
                     <&aoncrg 0x06>;
			reset-names = "rst_osc",
                          "rst_apb",
                          "rst_cal";
			rtc,cal-clock-freq = <0xf4240>;
			phandle = <0xa0>;
		};

		voutcrg: clock-controller@295c0000 {
			compatible = "starfive,jh7110-voutcrg";
			reg = <0x00 0x295c0000 0x00 0x10000>;
			clocks = <&syscrg 0x3a>,
                     <&syscrg 0x3d>,
                     <&syscrg 0x3e>,
                     <&syscrg 0x3f>,
                     <&syscrg 0xa5>,
                     <&clk_hdmitx0_pixelclk>;
			clock-names = "vout_src",
                          "vout_top_ahb",
                          "vout_top_axi",
                          "vout_top_hdmitx0_mclk",
                          "i2stx0_bclk",
                          "hdmitx0_pixelclk";
			resets = <&syscrg 0x2b>;
			#clock-cells = <0x01>;
			#reset-cells = <0x01>;
			power-domains = <&pmu 0x04>;
			phandle = <0x4e>;
		};
	};

	aliases {
		ethernet0 = "/soc/ethernet@16030000";
		ethernet1 = "/soc/ethernet@16040000";
		serial0 = "/soc/serial@10000000";
		serial3 = "/soc/serial@12000000";
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@40000000 {
		device_type = "memory";
		reg = <0x00 0x40000000 0x01 0x00>;
	};

	reserved-memory {
		#address-cells = <0x02>;
		#size-cells = <0x02>;
		ranges;

		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x00 0x20000000>;
			alignment = <0x00 0x1000>;
			alloc-ranges = <0x00 0x70000000 0x00 0x20000000>;
			linux,cma-default;
		};

		e24@c0000000 {
			reg = <0x00 0x6ce00000 0x00 0x1600000>;
			phandle = <0x5b>;
		};

		xrpbuffer@f0000000 {
			reg = <0x00 0x69c00000 0x00 0x1ffffff 0x00 0x6bc00000 0x00 0x1000 0x00 0x6bc01000 0x00 0xfff000 0x00 0x6cc00000 0x00 0x1000>;
			phandle = <0xab>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led-ack {
			gpios = <&aon_pinctrl 0x03 0x00>;
			color = <0x02>;
			function = "heartbeat";
			linux,default-trigger = "heartbeat";
			label = "ack";
		};
	};

	gpio-restart {
		compatible = "gpio-restart";
		gpios = <&sys_pinctrl 0x23 0x00>;
		priority = <0xe0>;
	};

	ac108_mclk {
		compatible = "fixed-clock";
		#clock-cells = <0x00>;
		clock-frequency = <0x16e3600>;
		phandle = <0xae>;
	};

	clk-ext-camera {
		compatible = "fixed-clock";
		#clock-cells = <0x00>;
		clock-frequency = <0x16e3600>;
		phandle = <0x2c>;
	};

	wm8960_mclk {
		compatible = "fixed-clock";
		#clock-cells = <0x00>;
		clock-frequency = <0x1770000>;
		phandle = <0xaf>;
	};

	__symbols__ {
		S7_0 = "/cpus/cpu@0";
		cpu0_intc = "/cpus/cpu@0/interrupt-controller";
		U74_1 = "/cpus/cpu@1";
		cpu1_intc = "/cpus/cpu@1/interrupt-controller";
		U74_2 = "/cpus/cpu@2";
		cpu2_intc = "/cpus/cpu@2/interrupt-controller";
		U74_3 = "/cpus/cpu@3";
		cpu3_intc = "/cpus/cpu@3/interrupt-controller";
		U74_4 = "/cpus/cpu@4";
		cpu4_intc = "/cpus/cpu@4/interrupt-controller";
		cpu_opp = "/opp-table-0";
		display = "/display-subsystem";
		dsi_output = "/dsi-output";
		mipi_in = "/dsi-output/ports/port@0/endpoint";
		sf_dpi_output = "/dsi-output/ports/port@1/endpoint";
		mailbox_client0 = "/mailbox_client";
		rgb_output = "/rgb-output";
		hdmi_input0 = "/rgb-output/ports/port@0/endpoint@0";
		tda988x_pin = "/tda988x_pin";
		cpu_alert0 = "/thermal-zones/cpu-thermal/trips/cpu_alert0";
		dvp_clk = "/dvp-clock";
		gmac0_rgmii_rxin = "/gmac0-rgmii-rxin-clock";
		gmac0_rmii_refin = "/gmac0-rmii-refin-clock";
		gmac1_rgmii_rxin = "/gmac1-rgmii-rxin-clock";
		gmac1_rmii_refin = "/gmac1-rmii-refin-clock";
		hdmitx0_pixelclk = "/hdmitx0-pixel-clock";
		i2srx_bclk_ext = "/i2srx-bclk-ext-clock";
		i2srx_lrck_ext = "/i2srx-lrck-ext-clock";
		i2stx_bclk_ext = "/i2stx-bclk-ext-clock";
		i2stx_lrck_ext = "/i2stx-lrck-ext-clock";
		mclk_ext = "/mclk-ext-clock";
		osc = "/oscillator";
		rtc_osc = "/rtc-oscillator";
		stmmac_axi_setup = "/stmmac-axi-config";
		tdm_ext = "/tdm-ext-clock";
		clint = "/soc/timer@2000000";
		ccache = "/soc/cache-controller@2010000";
		plic = "/soc/interrupt-controller@c000000";
		uart0 = "/soc/serial@10000000";
		uart1 = "/soc/serial@10010000";
		uart2 = "/soc/serial@10020000";
		i2c0 = "/soc/i2c@10030000";
		i2c1 = "/soc/i2c@10040000";
		i2c2 = "/soc/i2c@10050000";
		panel_out0 = "/soc/i2c@10050000/seeed_plane_i2c@45/port/endpoint";
		tinker_ft5406 = "/soc/i2c@10050000/tinker_ft5406@38";
		panel_out1 = "/soc/i2c@10050000/panel_radxa@19/port/endpoint";
		spi0 = "/soc/spi@10060000";
		spi_dev0 = "/soc/spi@10060000/spi@0";
		spi1 = "/soc/spi@10070000";
		spi2 = "/soc/spi@10080000";
		tdm = "/soc/tdm@10090000";
		spdif = "/soc/spdif@100a0000";
		pwmdac = "/soc/pwmdac@100b0000";
		pdm = "/soc/pdm@100d0000";
		i2srx_mst = "/soc/i2srx_mst@100e0000";
		i2srx = "/soc/i2s@100e0000";
		usb0 = "/soc/usb@10100000";
		usb_cdns3 = "/soc/usb@10100000/usb@0";
		usbphy0 = "/soc/phy@10200000";
		pciephy0 = "/soc/phy@10210000";
		pciephy1 = "/soc/phy@10220000";
		stgcrg = "/soc/clock-controller@10230000";
		xrp = "/soc/xrp@10230000";
		stg_syscon = "/soc/syscon@10240000";
		uart3 = "/soc/serial@12000000";
		uart4 = "/soc/serial@12010000";
		uart5 = "/soc/serial@12020000";
		i2c3 = "/soc/i2c@12030000";
		i2c4 = "/soc/i2c@12040000";
		i2c5 = "/soc/i2c@12050000";
		axp15060 = "/soc/i2c@12050000/pmic@36";
		mipi_0p9 = "/soc/i2c@12050000/pmic@36/regulators/ALDO1";
		hdmi_0p9 = "/soc/i2c@12050000/pmic@36/regulators/ALDO5";
		hdmi_1p8 = "/soc/i2c@12050000/pmic@36/regulators/ALDO3";
		vcc_3v3 = "/soc/i2c@12050000/pmic@36/regulators/dcdc1";
		vdd_cpu = "/soc/i2c@12050000/pmic@36/regulators/dcdc2";
		emmc_vdd = "/soc/i2c@12050000/pmic@36/regulators/aldo4";
		i2c6 = "/soc/i2c@12060000";
		imx219 = "/soc/i2c@12060000/imx219@10";
		imx219_to_csi2rx0 = "/soc/i2c@12060000/imx219@10/port/endpoint";
		imx708 = "/soc/i2c@12060000/imx708@1a";
		imx708_to_csi2rx0 = "/soc/i2c@12060000/imx708@1a/port/endpoint";
		ov4689 = "/soc/i2c@12060000/ov4689@36";
		ov4689_to_csi2rx0 = "/soc/i2c@12060000/ov4689@36/port/endpoint";
		spi3 = "/soc/spi@12070000";
		spi4 = "/soc/spi@12080000";
		spi5 = "/soc/spi@12090000";
		spi6 = "/soc/spi@120a0000";
		i2stx0 = "/soc/i2s@120b0000";
		i2stx1 = "/soc/i2s@120c0000";
		pwm = "/soc/pwm@120d0000";
		sfctemp = "/soc/temperature-sensor@120e0000";
		qspi = "/soc/spi@13010000";
		nor_flash = "/soc/spi@13010000/flash@0";
		syscrg = "/soc/clock-controller@13020000";
		sys_syscon = "/soc/syscon@13030000";
		pllclk = "/soc/syscon@13030000/clock-controller";
		sysgpio = "/soc/pinctrl@13040000";
		i2c0_pins = "/soc/pinctrl@13040000/i2c0-0";
		i2c2_pins = "/soc/pinctrl@13040000/i2c2-0";
		i2c5_pins = "/soc/pinctrl@13040000/i2c5-0";
		i2c6_pins = "/soc/pinctrl@13040000/i2c6-0";
		i2srx_pins = "/soc/pinctrl@13040000/i2srx-0";
		i2stx1_pins = "/soc/pinctrl@13040000/i2stx1-0";
		mclk_ext_pins = "/soc/pinctrl@13040000/mclk-ext-0";
		mmc0_pins = "/soc/pinctrl@13040000/mmc0-0";
		mmc1_pins = "/soc/pinctrl@13040000/mmc1-0";
		pcie0_pins = "/soc/pinctrl@13040000/pcie0-0";
		pcie1_pins = "/soc/pinctrl@13040000/pcie1-0";
		pwm_pins = "/soc/pinctrl@13040000/pwm-0";
		pwmdac_pins = "/soc/pinctrl@13040000/pwmdac-0";
		spi0_pins = "/soc/pinctrl@13040000/spi0-0";
		tdm_pins = "/soc/pinctrl@13040000/tdm-0";
		uart0_pins = "/soc/pinctrl@13040000/uart0-0";
		hdmi_pins = "/soc/pinctrl@13040000/hdmi-0";
		mailbox_contrl0 = "/soc/mailbox@13060000";
		jpu = "/soc/jpu@13090000";
		vpu_dec = "/soc/vpu_dec@130a0000";
		vpu_enc = "/soc/vpu_enc@130b0000";
		can0 = "/soc/can@130d0000";
		can1 = "/soc/can@130e0000";
		crypto = "/soc/crypto@16000000";
		sdma = "/soc/dma-controller@16008000";
		rng = "/soc/rng@1600c000";
		mmc0 = "/soc/mmc@16010000";
		mmc1 = "/soc/mmc@16020000";
		gmac0 = "/soc/ethernet@16030000";
		phy0 = "/soc/ethernet@16030000/mdio/ethernet-phy@0";
		gmac1 = "/soc/ethernet@16040000";
		phy1 = "/soc/ethernet@16040000/mdio/ethernet-phy@1";
		dma = "/soc/dma-controller@16050000";
		aoncrg = "/soc/clock-controller@17000000";
		aon_syscon = "/soc/syscon@17010000";
		aongpio = "/soc/pinctrl@17020000";
		pwrc = "/soc/power-controller@17030000";
		rtc = "/soc/rtc@17040000";
		gpu = "/soc/gpu@18000000";
		csi2rx = "/soc/csi-bridge@19800000";
		vin_sysctl = "/soc/vin_sysctl@19800000";
		csi2rx0_from_imx219 = "/soc/vin_sysctl@19800000/ports/port@1/endpoint@0";
		csi2rx0_from_imx708 = "/soc/vin_sysctl@19800000/ports/port@1/endpoint@1";
		csi2rx0_from_ov4689 = "/soc/vin_sysctl@19800000/ports/port@1/endpoint@2";
		ispcrg = "/soc/clock-controller@19810000";
		csi_phy = "/soc/phy@19820000";
		dc8200 = "/soc/dc8200@29400000";
		dc_out = "/soc/dc8200@29400000/port";
		dc_out_dpi0 = "/soc/dc8200@29400000/port/endpoint@0";
		dc_out_dpi1 = "/soc/dc8200@29400000/port/endpoint@1";
		dc_out_dpi2 = "/soc/dc8200@29400000/port/endpoint@2";
		hdmi = "/soc/hdmi@29590000";
		hdmi_in = "/soc/hdmi@29590000/port";
		hdmi_in_lcdc = "/soc/hdmi@29590000/port/endpoint@0";
		dssctrl = "/soc/dssctrl@295B0000";
		voutcrg = "/soc/clock-controller@295c0000";
		mipi_dsi = "/soc/mipi@295d0000";
		dsi0_output = "/soc/mipi@295d0000/ports/port@0/endpoint@0";
		dsi1_output = "/soc/mipi@295d0000/ports/port@0/endpoint@1";
		dsi_in_port = "/soc/mipi@295d0000/ports/port@1/endpoint";
		mipi_dphy = "/soc/mipi-dphy@295e0000";
		co_process = "/soc/e24@6e210000";
		e24_mem = "/reserved-memory/e24@c0000000";
		xrp_reserved = "/reserved-memory/xrpbuffer@f0000000";
		pwmdac_codec = "/pwmdac-codec";
		sound3 = "/snd-card3";
		sndcpu0 = "/snd-card3/simple-audio-card,dai-link@0/cpu";
		sound1 = "/snd-card1";
		sndi2s0 = "/snd-card1/simple-audio-card,dai-link@0/cpu";
		ac108_mclk = "/ac108_mclk";
		clk_ext_camera = "/clk-ext-camera";
		wm8960_mclk = "/wm8960_mclk";
	};
};
