yggdrasil/kernel/driver/net/rtl81xx/src/lib.rs

#![no_std]

use alloc::sync::Arc;
use device_api::device::Device;
use libk::error::Error;
use rtl8139::Rtl8139;
use rtl8168::Rtl8168;
use ygg_driver_pci::{
    device::{PciDeviceInfo, PreferredInterruptMode},
    PciBaseAddress, PciCommandRegister, PciConfigurationSpace,
};

extern crate alloc;

pub mod rtl8139;
pub mod rtl8168;

pub fn probe_8168(info: &PciDeviceInfo) -> Result<Arc<dyn Device>, Error> {
    let base = info
        .config_space
        .bar(2)
        .and_then(PciBaseAddress::as_memory)
        .ok_or(Error::InvalidArgument)?;

    // if let Some(power) = info.config_space.capability::<PowerManagementCapability>() {
    //     power.set_device_power_state(DevicePowerState::D0);
    // }

    // Enable MMIO + interrupts + bus mastering
    info.set_command(true, true, false, true);

    let device = Rtl8168::new(base, info.clone())?;
    Ok(Arc::new(device))
}

pub fn probe_8139(info: &PciDeviceInfo) -> Result<Arc<dyn Device>, Error> {
    info.init_interrupts(PreferredInterruptMode::Msi(false))?;

    // Enable MMIO + interrupts + bus mastering
    let mut command = info.config_space.command();
    command |= (PciCommandRegister::BUS_MASTER | PciCommandRegister::ENABLE_MEMORY).bits();
    command &= !(PciCommandRegister::ENABLE_IO | PciCommandRegister::DISABLE_INTERRUPTS).bits();
    info.config_space.set_command(command);

    let base = info
        .config_space
        .bar(1)
        .and_then(PciBaseAddress::as_memory)
        .ok_or(Error::InvalidArgument)?;

    let device = Rtl8139::new(base, info.clone())?;
    Ok(Arc::new(device))
}