From 1ad90ce1813cf9f7de60de9834999ce7b7c08734 Mon Sep 17 00:00:00 2001
From: Mark Poliakov <mark@alnyan.me>
Date: Tue, 10 Dec 2024 13:02:36 +0200
Subject: [PATCH] x86: add puts() impl to com-port
---
kernel/src/arch/x86/peripherals/serial.rs | 25 +++++++++++++++++------
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/kernel/src/arch/x86/peripherals/serial.rs b/kernel/src/arch/x86/peripherals/serial.rs
index 500b07c3..b7a021a0 100644
--- a/kernel/src/arch/x86/peripherals/serial.rs
+++ b/kernel/src/arch/x86/peripherals/serial.rs
@@ -31,22 +31,35 @@ impl DebugSink for Port {
self.send_byte(c)
}
+ fn puts(&self, s: &str) -> Result<(), Error> {
+ let mut inner = self.inner.lock();
+ for b in s.bytes() {
+ inner.write(b)?;
+ }
+ Ok(())
+ }
+
fn supports_control_sequences(&self) -> bool {
true
}
}
-impl SerialDevice for Port {
- fn send_byte(&self, byte: u8) -> Result<(), Error> {
- let inner = self.inner.lock();
-
- while inner.lsr.read() & Self::LSR_THRE == 0 {
+impl Inner {
+ fn write(&mut self, byte: u8) -> Result<(), Error> {
+ while self.lsr.read() & Port::LSR_THRE == 0 {
core::hint::spin_loop();
}
- inner.dr.write(byte);
+ self.dr.write(byte);
Ok(())
}
+}
+
+impl SerialDevice for Port {
+ fn send_byte(&self, byte: u8) -> Result<(), Error> {
+ let mut inner = self.inner.lock();
+ inner.write(byte)
+ }
fn is_terminal(&self) -> bool {
false