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Migrate to 1.82 rustc nightly

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This commit is contained in:
Mark Poliakov 2024-07-25 11:58:47 +03:00
parent 8eb5d2ecf1
commit 1bd9d65a5e
65 changed files with 791 additions and 256 deletions
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1
Cargo.lock generated
View File

@ -1197,7 +1197,6 @@ dependencies = [
[[package]]
name = "qemu"
version = "0.1.0"
source = "git+https://git.alnyan.me/yggdrasil/qemu.git#d20b34f9533684edeab295b0a76f3e12620d4e09"
[[package]]
name = "quick-error"

1
Cargo.toml
View File

@ -14,4 +14,5 @@ members = [
"lib/abi",
"lib/libyalloc",
"lib/runtime",
"lib/qemu"
]

3
kernel/Cargo.toml
View File

@ -78,3 +78,6 @@ kernel-arch-aarch64 = { path = "arch/aarch64" }
[features]
default = ["fb_console"]
fb_console = []
[lints.rust]
unexpected_cfgs = { level = "allow", check-cfg = ['cfg(rust_analyzer)'] }

8
kernel/arch/aarch64/src/lib.rs
View File

@ -1,11 +1,5 @@
#![no_std]
#![feature(
effects,
strict_provenance,
asm_const,
naked_functions,
trait_upcasting
)]
#![feature(strict_provenance, asm_const, naked_functions, trait_upcasting)]
extern crate alloc;

12
kernel/arch/aarch64/src/mem/mod.rs
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@ -12,8 +12,8 @@ use kernel_arch_interface::{
KERNEL_VIRT_OFFSET,
};
use libk_mm_interface::{
address::{FromRaw, PhysicalAddress},
table::{EntryLevel, EntryLevelExt},
address::PhysicalAddress,
table::{page_index, EntryLevel, EntryLevelExt},
KernelImageObject,
};
use memtables::aarch64::{FixedTables, KERNEL_L3_COUNT};
@ -34,8 +34,8 @@ const MAPPING_OFFSET: usize = KERNEL_VIRT_OFFSET;
const KERNEL_PHYS_BASE: usize = 0x40080000;
// Precomputed mappings
const KERNEL_L1_INDEX: usize = (KERNEL_VIRT_OFFSET + KERNEL_PHYS_BASE).page_index::<L1>();
const KERNEL_START_L2_INDEX: usize = (KERNEL_VIRT_OFFSET + KERNEL_PHYS_BASE).page_index::<L2>();
const KERNEL_L1_INDEX: usize = page_index::<L1>(KERNEL_VIRT_OFFSET + KERNEL_PHYS_BASE);
const KERNEL_START_L2_INDEX: usize = page_index::<L2>(KERNEL_VIRT_OFFSET + KERNEL_PHYS_BASE);
const KERNEL_END_L2_INDEX: usize = KERNEL_START_L2_INDEX + KERNEL_L3_COUNT;
// Must not be zero, should be at 4MiB
@ -95,7 +95,7 @@ impl KernelTableManager for KernelTableManagerImpl {
count: usize,
attrs: DeviceMemoryAttributes,
) -> Result<RawDeviceMemoryMapping<Self>, Error> {
map_device_memory(PhysicalAddress::from_raw(base), count, attrs)
map_device_memory(PhysicalAddress::from_u64(base), count, attrs)
}
unsafe fn unmap_device_pages(mapping: &RawDeviceMemoryMapping<Self>) {
@ -379,7 +379,7 @@ pub unsafe fn init_fixed_tables() {
let device_mapping_l2_phys = addr_of!(DEVICE_MAPPING_L2) as usize - KERNEL_VIRT_OFFSET;
for i in 0..DEVICE_MAPPING_L3_COUNT {
let device_mapping_l3_phys = PhysicalAddress::from_raw(
let device_mapping_l3_phys = PhysicalAddress::from_usize(
&DEVICE_MAPPING_L3S[i] as *const _ as usize - KERNEL_VIRT_OFFSET,
);
DEVICE_MAPPING_L2[i] = PageEntry::table(device_mapping_l3_phys, PageAttributes::empty());

17
kernel/arch/aarch64/src/mem/table.rs
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@ -5,7 +5,7 @@ use core::{
use bitflags::bitflags;
use libk_mm_interface::{
address::{AsPhysicalAddress, FromRaw, IntoRaw, PhysicalAddress},
address::{AsPhysicalAddress, PhysicalAddress},
pointer::{PhysicalRef, PhysicalRefMut},
table::{
EntryLevel, EntryLevelDrop, MapAttributes, NextPageTable, NonTerminalEntryLevel,
@ -191,15 +191,14 @@ where
impl<L: NonTerminalEntryLevel> PageEntry<L> {
pub fn table(phys: PhysicalAddress, attrs: PageAttributes) -> Self {
Self(
IntoRaw::<u64>::into_raw(phys)
| (PageAttributes::TABLE | PageAttributes::PRESENT | attrs).bits(),
phys.into_u64() | (PageAttributes::TABLE | PageAttributes::PRESENT | attrs).bits(),
PhantomData,
)
}
pub fn normal_block(phys: PhysicalAddress, attrs: PageAttributes) -> Self {
Self(
IntoRaw::<u64>::into_raw(phys)
phys.into_u64()
| (PageAttributes::BLOCK
| PageAttributes::PRESENT
| PageAttributes::ACCESS
@ -213,7 +212,7 @@ impl<L: NonTerminalEntryLevel> PageEntry<L> {
pub fn device_block(phys: PhysicalAddress) -> Self {
Self(
IntoRaw::<u64>::into_raw(phys)
phys.into_u64()
| (PageAttributes::BLOCK
| PageAttributes::PRESENT
| PageAttributes::ACCESS
@ -232,7 +231,7 @@ impl<L: NonTerminalEntryLevel> PageEntry<L> {
if self.0 & PageAttributes::PRESENT.bits() != 0
&& self.0 & PageAttributes::BLOCK.bits() == 0
{
Some(PhysicalAddress::from_raw(self.0 & !0xFFF))
Some(PhysicalAddress::from_u64(self.0 & !0xFFF))
} else {
None
}
@ -242,7 +241,7 @@ impl<L: NonTerminalEntryLevel> PageEntry<L> {
impl PageEntry<L3> {
pub fn normal_page(phys: PhysicalAddress, attrs: PageAttributes) -> Self {
Self(
IntoRaw::<u64>::into_raw(phys)
phys.into_u64()
| (PageAttributes::PAGE
| PageAttributes::PRESENT
| PageAttributes::ACCESS
@ -256,7 +255,7 @@ impl PageEntry<L3> {
pub fn device_page(phys: PhysicalAddress) -> Self {
Self(
IntoRaw::<u64>::into_raw(phys)
phys.into_u64()
| (PageAttributes::PAGE
| PageAttributes::PRESENT
| PageAttributes::ACCESS
@ -272,7 +271,7 @@ impl PageEntry<L3> {
pub fn as_page(&self) -> Option<PhysicalAddress> {
let mask = (PageAttributes::PRESENT | PageAttributes::PAGE).bits();
if self.0 & mask == mask {
Some(PhysicalAddress::from_raw(self.0 & !0xFFF))
Some(PhysicalAddress::from_u64(self.0 & !0xFFF))
} else {
None
}

2
kernel/arch/interface/src/lib.rs
View File

@ -1,5 +1,5 @@
#![no_std]
#![feature(step_trait, effects, const_trait_impl, never_type)]
#![feature(step_trait, const_trait_impl, never_type)]
use alloc::vec::Vec;
use cpu::IpiQueue;

4
kernel/arch/x86_64/src/context.rs
View File

@ -4,7 +4,7 @@ use kernel_arch_interface::{
mem::{KernelTableManager, PhysicalMemoryAllocator},
task::{ForkFrame, StackBuilder, TaskContext, TaskFrame, UserContextInfo},
};
use libk_mm_interface::address::{AsPhysicalAddress, IntoRaw, PhysicalAddress};
use libk_mm_interface::address::{AsPhysicalAddress, PhysicalAddress};
use yggdrasil_abi::{arch::SavedFrame, error::Error};
use crate::{mem::KERNEL_TABLES, registers::FpuContext};
@ -423,7 +423,7 @@ impl<K: KernelTableManager, PA: PhysicalMemoryAllocator<Address = PhysicalAddres
setup_common_context(
&mut stack,
__x86_64_task_enter_kernel as _,
unsafe { KERNEL_TABLES.as_physical_address().into_raw() },
unsafe { KERNEL_TABLES.as_physical_address().into_u64() },
0,
);

8
kernel/arch/x86_64/src/lib.rs
View File

@ -1,12 +1,6 @@
#![no_std]
#![allow(clippy::new_without_default)]
#![feature(
effects,
strict_provenance,
asm_const,
naked_functions,
trait_upcasting
)]
#![feature(strict_provenance, asm_const, naked_functions, trait_upcasting)]
extern crate alloc;

14
kernel/arch/x86_64/src/mem/mod.rs
View File

@ -9,8 +9,8 @@ use kernel_arch_interface::mem::{
DeviceMemoryAttributes, KernelTableManager, RawDeviceMemoryMapping,
};
use libk_mm_interface::{
address::{FromRaw, PhysicalAddress},
table::{EntryLevel, EntryLevelExt},
address::PhysicalAddress,
table::{page_index, EntryLevel, EntryLevelExt},
KernelImageObject,
};
use memtables::x86_64::FixedTables;
@ -32,9 +32,9 @@ const KERNEL_PHYS_BASE: usize = 0x200000;
// Mapped at compile time
const KERNEL_MAPPING_BASE: usize = KERNEL_VIRT_OFFSET + KERNEL_PHYS_BASE;
const KERNEL_L0_INDEX: usize = KERNEL_MAPPING_BASE.page_index::<L0>();
const KERNEL_L1_INDEX: usize = KERNEL_MAPPING_BASE.page_index::<L1>();
const KERNEL_START_L2_INDEX: usize = KERNEL_MAPPING_BASE.page_index::<L2>();
const KERNEL_L0_INDEX: usize = page_index::<L0>(KERNEL_MAPPING_BASE);
const KERNEL_L1_INDEX: usize = page_index::<L1>(KERNEL_MAPPING_BASE);
const KERNEL_START_L2_INDEX: usize = page_index::<L2>(KERNEL_MAPPING_BASE);
// Must not be zero, should be at 4MiB
const_assert_ne!(KERNEL_START_L2_INDEX, 0);
@ -95,7 +95,7 @@ impl KernelTableManager for KernelTableManagerImpl {
count: usize,
attrs: DeviceMemoryAttributes,
) -> Result<RawDeviceMemoryMapping<Self>, Error> {
map_device_memory(PhysicalAddress::from_raw(base), count, attrs)
map_device_memory(PhysicalAddress::from_u64(base), count, attrs)
}
unsafe fn unmap_device_pages(mapping: &RawDeviceMemoryMapping<Self>) {
@ -364,7 +364,7 @@ pub unsafe fn init_fixed_tables() {
let ram_mapping_l1_phys = addr_of!(RAM_MAPPING_L1) as usize - KERNEL_VIRT_OFFSET;
for i in 0..DEVICE_MAPPING_L3_COUNT {
let device_mapping_l3_phys = PhysicalAddress::from_raw(
let device_mapping_l3_phys = PhysicalAddress::from_usize(
&DEVICE_MAPPING_L3S[i] as *const _ as usize - KERNEL_VIRT_OFFSET,
);
DEVICE_MAPPING_L2[i] = PageEntry::table(device_mapping_l3_phys, PageAttributes::WRITABLE);

4
kernel/arch/x86_64/src/mem/process.rs
View File

@ -2,7 +2,7 @@
use core::marker::PhantomData;
use libk_mm_interface::{
address::{AsPhysicalAddress, IntoRaw, PhysicalAddress},
address::{AsPhysicalAddress, PhysicalAddress},
pointer::PhysicalRefMut,
process::ProcessAddressSpaceManager,
table::{
@ -73,7 +73,7 @@ impl<TA: TableAllocator> ProcessAddressSpaceManager<TA> for ProcessAddressSpaceI
fn as_address_with_asid(&self) -> u64 {
// TODO x86-64 PCID/ASID?
unsafe { self.l0.as_physical_address().into_raw() }
unsafe { self.l0.as_physical_address().into_u64() }
}
unsafe fn clear(&mut self) {

6
kernel/arch/x86_64/src/mem/table.rs
View File

@ -6,7 +6,7 @@ use core::{
use bitflags::bitflags;
use libk_mm_interface::{
address::{AsPhysicalAddress, FromRaw, PhysicalAddress},
address::{AsPhysicalAddress, PhysicalAddress},
pointer::{PhysicalRef, PhysicalRefMut},
table::{
EntryLevel, EntryLevelDrop, MapAttributes, NextPageTable, NonTerminalEntryLevel,
@ -98,7 +98,7 @@ impl PageEntry<L3> {
/// not
pub fn as_page(self) -> Option<PhysicalAddress> {
if self.0 & PageAttributes::PRESENT.bits() != 0 {
Some(PhysicalAddress::from_raw(self.0 & !0xFFF))
Some(PhysicalAddress::from_u64(self.0 & !0xFFF))
} else {
None
}
@ -145,7 +145,7 @@ impl<L: NonTerminalEntryLevel> PageEntry<L> {
if self.0 & PageAttributes::PRESENT.bits() != 0
&& self.0 & PageAttributes::BLOCK.bits() == 0
{
Some(PhysicalAddress::from_raw(self.0 & !0xFFF))
Some(PhysicalAddress::from_u64(self.0 & !0xFFF))
} else {
None
}

6
kernel/driver/block/ahci/src/data.rs
View File

@ -2,7 +2,7 @@ use core::mem::size_of;
use alloc::string::String;
use bytemuck::{Pod, Zeroable};
use libk_mm::address::{IntoRaw, PhysicalAddress};
use libk_mm::address::PhysicalAddress;
use libk_util::{ConstAssert, IsTrue};
use static_assertions::const_assert_eq;
@ -165,7 +165,7 @@ impl CommandListEntry {
attr: (size_of::<RegisterHostToDeviceFis>() / size_of::<u32>()) as _,
prdtl: prd_count as _,
prdbc: 0,
ctba: command_table_entry.into_raw(),
ctba: command_table_entry.into(),
_0: [0; 4],
})
}
@ -194,7 +194,7 @@ impl PhysicalRegionDescriptor {
let dbc_mask = (is_last as u32) << 31;
Ok(Self {
buffer_address: address.into_raw(),
buffer_address: address.into(),
_0: 0,
dbc: ((byte_count as u32 - 1) << 1) | 1 | dbc_mask,
})

2
kernel/driver/block/ahci/src/error.rs
View File

@ -2,7 +2,7 @@ use yggdrasil_abi::error::Error;
#[derive(Debug)]
pub enum AhciError {
MemoryError(Error),
MemoryError(#[allow(dead_code)] Error),
RegionTooLarge,
DeviceError,
}

2
kernel/driver/block/ahci/src/lib.rs
View File

@ -1,4 +1,4 @@
#![feature(generic_const_exprs, inline_const)]
#![feature(generic_const_exprs)]
#![allow(incomplete_features)]
#![no_std]

6
kernel/driver/block/ahci/src/regs.rs
View File

@ -1,4 +1,4 @@
use libk_mm::address::{IntoRaw, PhysicalAddress};
use libk_mm::address::PhysicalAddress;
use tock_registers::{
interfaces::{ReadWriteable, Readable, Writeable},
register_bitfields, register_structs,
@ -150,13 +150,13 @@ impl PortRegs {
}
pub fn set_received_fis_address_64(&self, address: PhysicalAddress) {
let address: u64 = address.into_raw();
let address: u64 = address.into();
self.FB.set(address as u32);
self.FBU.set((address >> 32) as u32);
}
pub fn set_command_list_address_64(&self, address: PhysicalAddress) {
let address: u64 = address.into_raw();
let address: u64 = address.into();
self.CLB.set(address as u32);
self.CLBU.set((address >> 32) as u32);
}

11
kernel/driver/block/nvme/src/lib.rs
View File

@ -1,4 +1,4 @@
#![feature(strict_provenance, const_trait_impl, let_chains, if_let_guard, effects)]
#![feature(strict_provenance, const_trait_impl, let_chains, if_let_guard)]
#![allow(missing_docs)]
#![no_std]
@ -18,10 +18,7 @@ use device_api::{
};
use drive::NvmeDrive;
use libk::task::{cpu_count, cpu_index, runtime};
use libk_mm::{
address::{IntoRaw, PhysicalAddress},
device::DeviceMemoryIo,
};
use libk_mm::{address::PhysicalAddress, device::DeviceMemoryIo};
use libk_util::{
sync::{IrqGuard, IrqSafeSpinlock},
OneTimeInit,
@ -369,8 +366,8 @@ impl Device for NvmeController {
AQA::ASQS.val(Self::ADMIN_QUEUE_SIZE as u32 - 1)
+ AQA::ACQS.val(Self::ADMIN_QUEUE_SIZE as u32 - 1),
);
regs.ASQ.set(admin_q.sq_physical_pointer().into_raw());
regs.ACQ.set(admin_q.cq_physical_pointer().into_raw());
regs.ASQ.set(admin_q.sq_physical_pointer().into());
regs.ACQ.set(admin_q.cq_physical_pointer().into());
// Configure the controller
const IOSQES: u32 = size_of::<SubmissionQueueEntry>().ilog2();

4
kernel/driver/block/nvme/src/queue.rs
View File

@ -12,7 +12,7 @@ use alloc::{
use bytemuck::{Pod, Zeroable};
use futures_util::Future;
use libk_mm::{
address::{AsPhysicalAddress, IntoRaw, PhysicalAddress},
address::{AsPhysicalAddress, PhysicalAddress},
PageBox,
};
use libk_util::{sync::IrqSafeSpinlock, waker::QueueWaker};
@ -107,7 +107,7 @@ impl PhysicalRegionPage {
}
pub const fn with_addr(address: PhysicalAddress) -> Self {
Self(address.into_raw())
Self(address.into_u64())
}
}

8
kernel/driver/bus/pci/src/lib.rs
View File

@ -11,7 +11,7 @@ use alloc::{collections::BTreeMap, sync::Arc, vec::Vec};
use bitflags::bitflags;
use device::{PciBusDevice, PciDeviceInfo, PciDriver, PciInterrupt, PciInterruptRoute, PciMatch};
use device_api::Device;
use libk_mm::address::{FromRaw, PhysicalAddress};
use libk_mm::address::PhysicalAddress;
use libk_util::{sync::IrqSafeSpinlock, OneTimeInit};
use yggdrasil_abi::error::Error;
@ -227,8 +227,8 @@ pub struct PciBusManager {
impl PciBaseAddress {
pub fn as_memory(self) -> Option<PhysicalAddress> {
match self {
Self::Memory32(address) => Some(PhysicalAddress::from_raw(address as u64)),
Self::Memory64(address) => Some(PhysicalAddress::from_raw(address)),
Self::Memory32(address) => Some(PhysicalAddress::from_u64(address as u64)),
Self::Memory64(address) => Some(PhysicalAddress::from_u64(address)),
_ => None,
}
}
@ -416,7 +416,7 @@ impl PciBusManager {
segment_number: entry.pci_segment_group as u8,
bus_number_start: entry.bus_number_start,
bus_number_end: entry.bus_number_end,
ecam_phys_base: Some(PhysicalAddress::from_raw(entry.base_address)),
ecam_phys_base: Some(PhysicalAddress::from_u64(entry.base_address)),
// TODO obtain this from ACPI SSDT
irq_translation_map: BTreeMap::new(),

3
kernel/driver/usb/xhci/src/device.rs
View File

@ -1,6 +1,5 @@
use alloc::{boxed::Box, sync::Arc, vec::Vec};
use futures_util::{future::BoxFuture, FutureExt};
use libk_mm::address::IntoRaw;
use libk_util::sync::spin_rwlock::IrqSafeRwLock;
use xhci_lib::context::{self, InputHandler};
use ygg_driver_usb::{
@ -81,7 +80,7 @@ impl XhciBusDevice {
{
let ep_cx = input.device_mut().endpoint_mut(dci as _);
ep_cx.set_tr_dequeue_pointer(ring.dequeue_pointer().into_raw());
ep_cx.set_tr_dequeue_pointer(ring.dequeue_pointer().into());
ep_cx.set_dequeue_cycle_state();
ep_cx.set_endpoint_type(ep_type);
ep_cx.set_error_count(3);

4
kernel/driver/usb/xhci/src/lib.rs
View File

@ -13,7 +13,7 @@ mod ring;
use alloc::boxed::Box;
pub use controller::Xhci;
use device_api::{interrupt::InterruptAffinity, Device};
use libk_mm::{address::IntoRaw, PageBox};
use libk_mm::PageBox;
use libk_util::sync::spin_rwlock::IrqSafeRwLock;
use regs::{Mapper, PortSpeed};
use ring::{ControlTransferRing, GenericTransferRing};
@ -73,7 +73,7 @@ impl XhciContext<8> {
let ep0 = input.device_mut().endpoint_mut(1);
ep0.set_endpoint_type(context::EndpointType::Control);
ep0.set_tr_dequeue_pointer(default_control_ring.dequeue_pointer().into_raw());
ep0.set_tr_dequeue_pointer(default_control_ring.dequeue_pointer().into());
ep0.set_dequeue_cycle_state();
ep0.set_error_count(3);
ep0.set_max_packet_size(speed.default_max_packet_size() as _);

12
kernel/driver/usb/xhci/src/regs.rs
View File

@ -2,7 +2,7 @@ use core::{cell::UnsafeCell, num::NonZeroUsize};
use alloc::{sync::Arc, vec::Vec};
use libk_mm::{
address::{AsPhysicalAddress, IntoRaw, PhysicalAddress},
address::{AsPhysicalAddress, PhysicalAddress},
device::RawDeviceMemoryMapping,
PageBox,
};
@ -147,10 +147,10 @@ impl Regs {
let mut i = self.interrupters.write();
o.dcbaap.update_volatile(|u| unsafe {
u.set(dcbaa.as_physical_address().into_raw());
u.set(dcbaa.as_physical_address().into());
});
o.crcr.update_volatile(|u| {
u.set_command_ring_pointer(cmd_ring.base().into_raw());
u.set_command_ring_pointer(cmd_ring.base().into());
u.set_ring_cycle_state();
});
@ -160,10 +160,10 @@ impl Regs {
});
intr0.erdp.update_volatile(|u| {
log::debug!("::: Dequeue Pointer: {:#x}", evt_ring.dequeue_pointer());
u.set_event_ring_dequeue_pointer(evt_ring.dequeue_pointer().into_raw());
u.set_event_ring_dequeue_pointer(evt_ring.dequeue_pointer().into());
});
intr0.erstba.update_volatile(|u| {
u.set(erst.physical_address().into_raw());
u.set(erst.physical_address().into());
});
// intr0.imod.update_volatile(|u| {
// u.set_interrupt_moderation_interval(0)
@ -207,7 +207,7 @@ impl Regs {
let mut i = self.interrupters.write();
i.interrupter_mut(0).erdp.update_volatile(|u| {
u.set_event_ring_dequeue_pointer(pointer.into_raw());
u.set_event_ring_dequeue_pointer(pointer.into());
u.clear_event_handler_busy();
});
}

9
kernel/driver/virtio/core/src/queue.rs
View File

@ -8,10 +8,7 @@ use core::{
sync::atomic::{fence, Ordering},
};
use libk_mm::{
address::{AsPhysicalAddress, IntoRaw},
PageBox,
};
use libk_mm::{address::AsPhysicalAddress, PageBox};
use crate::{error::Error, transport::Transport};
@ -224,7 +221,7 @@ impl VirtQueue {
let next = (self.free_head + 1) % self.capacity as u16;
desc.write(Descriptor {
address: item.as_physical_address().into_raw(),
address: item.as_physical_address().into(),
len: item.len().try_into().unwrap(),
// TODO MAGIC
flags: (1 << 0) | (1 << 1),
@ -241,7 +238,7 @@ impl VirtQueue {
let next = (self.free_head + 1) % self.capacity as u16;
desc.write(Descriptor {
address: item.as_physical_address().into_raw(),
address: item.as_physical_address().into(),
len: item.len().try_into().unwrap(),
// TODO
flags: (1 << 0),

11
kernel/driver/virtio/core/src/transport/mod.rs
View File

@ -1,9 +1,6 @@
use core::mem::size_of;
use libk_mm::{
address::{IntoRaw, PhysicalAddress},
device::DeviceMemoryIo,
};
use libk_mm::{address::PhysicalAddress, device::DeviceMemoryIo};
use tock_registers::{
interfaces::{Readable, Writeable},
registers::WriteOnly,
@ -67,9 +64,9 @@ pub trait Transport {
let cfg = self.common_cfg();
cfg.queue_select.set(queue);
cfg.queue_size.set(capacity);
cfg.queue_desc.set(descriptor_table_phys.into_raw());
cfg.queue_driver.set(available_ring_phys.into_raw());
cfg.queue_device.set(used_ring_phys.into_raw());
cfg.queue_desc.set(descriptor_table_phys.into());
cfg.queue_driver.set(available_ring_phys.into());
cfg.queue_device.set(used_ring_phys.into());
if self.supports_msix() {
cfg.queue_msix_vector.set(msix_vector.unwrap_or(0xFFFF));
} else {

7
kernel/lib/device-tree/src/dt.rs
View File

@ -5,10 +5,7 @@ use fdt_rs::{
index::{iters::DevTreeIndexNodeSiblingIter, DevTreeIndex, DevTreeIndexNode, DevTreeIndexProp},
prelude::PropReader,
};
use libk_mm::{
address::{FromRaw, PhysicalAddress},
phys::PhysicalMemoryRegion,
};
use libk_mm::{address::PhysicalAddress, phys::PhysicalMemoryRegion};
use yggdrasil_abi::error::Error;
const INDEX_BUFFER_SIZE: usize = 65536;
@ -235,7 +232,7 @@ impl Iterator for FdtMemoryRegionIter<'_> {
.cell2_array_item(0, self.address_cells, self.size_cells)
.unwrap();
let base = PhysicalAddress::from_raw(base);
let base = PhysicalAddress::from_u64(base);
let size = size as usize;
break Some(PhysicalMemoryRegion { base, size });

5
kernel/libk/Cargo.toml
View File

@ -7,7 +7,7 @@ edition = "2021"
authors = ["Mark Poliakov <mark@alnyan.me>"]
[lib]
crate_type = ["rlib", "dylib"]
crate-type = ["rlib", "dylib"]
[dependencies]
libk-mm = { path = "libk-mm" }
@ -34,3 +34,6 @@ version = "0.7.2"
git = "https://git.alnyan.me/yggdrasil/yggdrasil-elf.git"
default-features = false
features = ["no_std_stream"]
[lints.rust]
unexpected_cfgs = { level = "allow", check-cfg = ['cfg(rust_analyzer)'] }

86
kernel/libk/libk-mm/interface/src/address.rs
View File

@ -13,19 +13,17 @@ use kernel_arch_interface::mem::KernelTableManager;
#[repr(transparent)]
pub struct PhysicalAddress(pub(crate) u64);
/// Interface for converting addresses from their raw values to more specific types
#[const_trait]
pub trait FromRaw<T> {
/// Converts a raw value into the address wrapper type
fn from_raw(value: T) -> Self;
}
/// Interface for converting wrapper types into their raw address representations
#[const_trait]
pub trait IntoRaw<T> {
/// Converts a wrapper type value into its raw address
fn into_raw(self) -> T;
}
// /// Interface for converting addresses from their raw values to more specific types
// pub trait FromRaw<T> {
// /// Converts a raw value into the address wrapper type
// fn from_raw(value: T) -> Self;
// }
//
// /// Interface for converting wrapper types into their raw address representations
// pub trait IntoRaw<T> {
// /// Converts a wrapper type value into its raw address
// fn into_raw(self) -> T;
// }
/// Interface for obtaining physical addresses of values
pub trait AsPhysicalAddress {
@ -51,6 +49,22 @@ impl PhysicalAddress {
Self(self.0 + offset as u64)
}
pub const fn from_usize(value: usize) -> Self {
Self(value as u64)
}
pub const fn from_u64(value: u64) -> Self {
Self(value)
}
pub const fn into_usize(self) -> usize {
self.0 as usize
}
pub const fn into_u64(self) -> u64 {
self.0
}
/// Returns `true` if the address is zero
#[inline(always)]
pub const fn is_zero(self) -> bool {
@ -100,29 +114,29 @@ impl Sub for PhysicalAddress {
// Conversions
impl const FromRaw<u64> for PhysicalAddress {
fn from_raw(value: u64) -> Self {
Self(value)
}
}
impl const FromRaw<usize> for PhysicalAddress {
fn from_raw(value: usize) -> Self {
Self(value as u64)
}
}
impl const IntoRaw<u64> for PhysicalAddress {
fn into_raw(self) -> u64 {
self.0
}
}
impl const IntoRaw<usize> for PhysicalAddress {
fn into_raw(self) -> usize {
self.0 as usize
}
}
// impl FromRaw<u64> for PhysicalAddress {
// fn from_raw(value: u64) -> Self {
// Self(value)
// }
// }
//
// impl FromRaw<usize> for PhysicalAddress {
// fn from_raw(value: usize) -> Self {
// Self(value as u64)
// }
// }
//
// impl IntoRaw<u64> for PhysicalAddress {
// fn into_raw(self) -> u64 {
// self.0
// }
// }
//
// impl IntoRaw<usize> for PhysicalAddress {
// fn into_raw(self) -> usize {
// self.0 as usize
// }
// }
impl From<PhysicalAddress> for u64 {
fn from(addr: PhysicalAddress) -> u64 {

6
kernel/libk/libk-mm/interface/src/lib.rs
View File

@ -1,9 +1,9 @@
#![no_std]
#![feature(step_trait, const_trait_impl, effects, strict_provenance)]
#![feature(step_trait, const_trait_impl, strict_provenance)]
use core::ops::{Deref, DerefMut};
use address::{AsPhysicalAddress, FromRaw, PhysicalAddress};
use address::{AsPhysicalAddress, PhysicalAddress};
use kernel_arch_interface::KERNEL_VIRT_OFFSET;
pub mod address;
@ -32,7 +32,7 @@ impl<T> KernelImageObject<T> {
impl<T> AsPhysicalAddress for KernelImageObject<T> {
unsafe fn as_physical_address(&self) -> PhysicalAddress {
PhysicalAddress::from_raw(&self.inner as *const _ as usize - KERNEL_VIRT_OFFSET)
PhysicalAddress::from_usize(&self.inner as *const _ as usize - KERNEL_VIRT_OFFSET)
}
}

42
kernel/libk/libk-mm/interface/src/table.rs
View File

@ -35,7 +35,30 @@ bitflags! {
}
}
#[const_trait]
pub const fn page_index<T: EntryLevel>(address: usize) -> usize {
address >> T::SHIFT & 0x1FF
}
pub const fn page_offset<T: EntryLevel>(address: usize) -> usize {
address & (T::SIZE - 1)
}
pub const fn page_count<T: EntryLevel>(address: usize) -> usize {
(address + T::SIZE - 1) / T::SIZE
}
pub const fn page_align_up<T: EntryLevel>(address: usize) -> usize {
(address + T::SIZE - 1) & !(T::SIZE - 1)
}
pub const fn page_align_down<T: EntryLevel>(address: usize) -> usize {
address & !(T::SIZE - 1)
}
pub const fn is_page_aligned_for<T: EntryLevel>(address: usize) -> bool {
page_offset::<T>(address) == 0
}
pub trait EntryLevelExt: Sized {
fn page_index<T: EntryLevel>(&self) -> usize;
fn page_offset<T: EntryLevel>(&self) -> usize;
@ -45,7 +68,6 @@ pub trait EntryLevelExt: Sized {
fn is_page_aligned_for<T: EntryLevel>(&self) -> bool;
}
#[const_trait]
trait AddressLike: Sized + Copy {
fn into_usize(self) -> usize;
fn from_usize(v: usize) -> Self;
@ -102,7 +124,7 @@ pub trait NonTerminalEntryLevel: EntryLevel {
type NextLevel: EntryLevel;
}
impl const AddressLike for usize {
impl AddressLike for usize {
#[inline(always)]
fn into_usize(self) -> usize {
self
@ -114,7 +136,7 @@ impl const AddressLike for usize {
}
}
impl const AddressLike for PhysicalAddress {
impl AddressLike for PhysicalAddress {
fn from_usize(v: usize) -> Self {
Self(v as _)
}
@ -124,30 +146,30 @@ impl const AddressLike for PhysicalAddress {
}
}
impl<T: ~const AddressLike> const EntryLevelExt for T {
impl<T: AddressLike> EntryLevelExt for T {
#[inline(always)]
fn page_index<L: EntryLevel>(&self) -> usize {
(self.into_usize() >> L::SHIFT) & 0x1FF
page_index::<L>(self.into_usize())
}
#[inline(always)]
fn page_offset<L: EntryLevel>(&self) -> usize {
self.into_usize() & (L::SIZE - 1)
page_offset::<L>(self.into_usize())
}
#[inline(always)]
fn page_count<L: EntryLevel>(&self) -> usize {
(self.into_usize() + L::SIZE - 1) / L::SIZE
page_count::<L>(self.into_usize())
}
#[inline(always)]
fn page_align_up<L: EntryLevel>(&self) -> Self {
Self::from_usize((self.into_usize() + L::SIZE - 1) & !(L::SIZE - 1))
Self::from_usize(page_align_up::<L>(self.into_usize()))
}
#[inline(always)]
fn page_align_down<L: EntryLevel>(&self) -> Self {
Self::from_usize(self.into_usize() & !(L::SIZE - 1))
Self::from_usize(page_align_down::<L>(self.into_usize()))
}
#[inline(always)]

6
kernel/libk/libk-mm/src/address.rs
View File

@ -1,5 +1,5 @@
use kernel_arch::{mem::KernelTableManager, KernelTableManagerImpl};
pub use libk_mm_interface::address::{AsPhysicalAddress, FromRaw, IntoRaw, PhysicalAddress};
pub use libk_mm_interface::address::{AsPhysicalAddress, PhysicalAddress};
pub trait Virtualize {
fn virtualize(self) -> usize;
@ -8,10 +8,10 @@ pub trait Virtualize {
impl Virtualize for PhysicalAddress {
fn virtualize(self) -> usize {
KernelTableManagerImpl::virtualize(self.into_raw())
KernelTableManagerImpl::virtualize(self.into_u64())
}
fn from_virtualized(value: usize) -> Self {
PhysicalAddress::from_raw(KernelTableManagerImpl::physicalize(value))
PhysicalAddress::from_u64(KernelTableManagerImpl::physicalize(value))
}
}

12
kernel/libk/libk-mm/src/device.rs
View File

@ -6,7 +6,7 @@ use core::{
use alloc::sync::Arc;
use kernel_arch::KernelTableManagerImpl;
use libk_mm_interface::address::{AsPhysicalAddress, FromRaw, IntoRaw, PhysicalAddress};
use libk_mm_interface::address::{AsPhysicalAddress, PhysicalAddress};
use yggdrasil_abi::error::Error;
pub use kernel_arch::mem::{DeviceMemoryAttributes, DeviceMemoryCaching};
@ -50,7 +50,7 @@ impl DeviceMemoryMapping {
size: usize,
attrs: DeviceMemoryAttributes,
) -> Result<Self, Error> {
let inner = RawDeviceMemoryMapping::map(base.into_raw(), size, attrs)?;
let inner = RawDeviceMemoryMapping::map(base.into_u64(), size, attrs)?;
let address = inner.address;
Ok(Self {
inner: Arc::new(inner),
@ -94,7 +94,7 @@ impl<'a, T: Sized> DeviceMemoryIo<'a, T> {
attrs: DeviceMemoryAttributes,
) -> Result<DeviceMemoryIo<'a, [T]>, Error> {
let layout = Layout::array::<T>(count).unwrap();
let inner = RawDeviceMemoryMapping::map(base.into_raw(), layout.size(), attrs)?;
let inner = RawDeviceMemoryMapping::map(base.into_u64(), layout.size(), attrs)?;
let value = core::slice::from_raw_parts(inner.address as *mut T, count);
Ok(DeviceMemoryIo {
@ -113,7 +113,7 @@ impl<'a, T: Sized> DeviceMemoryIo<'a, T> {
base: PhysicalAddress,
attrs: DeviceMemoryAttributes,
) -> Result<DeviceMemoryIo<'a, T>, Error> {
let inner = RawDeviceMemoryMapping::map(base.into_raw(), size_of::<T>(), attrs)?;
let inner = RawDeviceMemoryMapping::map(base.into_u64(), size_of::<T>(), attrs)?;
let value = &*(inner.address as *const T);
Ok(DeviceMemoryIo {
@ -154,7 +154,7 @@ impl<'a, T: ?Sized> Deref for DeviceMemoryIo<'a, T> {
impl<T: ?Sized> AsPhysicalAddress for DeviceMemoryIo<'_, T> {
unsafe fn as_physical_address(&self) -> PhysicalAddress {
PhysicalAddress::from_raw(self.inner.base_address)
PhysicalAddress::from_usize(self.inner.base_address)
}
}
@ -173,7 +173,7 @@ impl<'a, T: Sized> DeviceMemoryIoMut<'a, T> {
attrs: DeviceMemoryAttributes,
) -> Result<DeviceMemoryIoMut<'a, [T]>, Error> {
let layout = Layout::array::<T>(len).unwrap();
let inner = RawDeviceMemoryMapping::map(base.into_raw(), layout.size(), attrs)?;
let inner = RawDeviceMemoryMapping::map(base.into_u64(), layout.size(), attrs)?;
let value = core::slice::from_raw_parts_mut(inner.address as *mut T, len);
Ok(DeviceMemoryIoMut { inner, value })

3
kernel/libk/libk-mm/src/lib.rs
View File

@ -4,8 +4,7 @@
slice_ptr_get,
step_trait,
const_trait_impl,
maybe_uninit_as_bytes,
effects
maybe_uninit_as_bytes
)]
#![no_std]

15
kernel/libk/libk-mm/src/phys/manager.rs
View File

@ -2,10 +2,7 @@
use core::sync::atomic::{AtomicUsize, Ordering};
use kernel_arch::KernelTableManagerImpl;
use libk_mm_interface::{
address::{FromRaw, IntoRaw, PhysicalAddress},
pointer::PhysicalRefMut,
};
use libk_mm_interface::{address::PhysicalAddress, pointer::PhysicalRefMut};
use yggdrasil_abi::{error::Error, system::SystemMemoryStats};
use crate::L3_PAGE_SIZE;
@ -86,7 +83,7 @@ impl PhysicalMemoryManager {
STATS.used_pages.fetch_add(1, Ordering::Relaxed);
return Ok(PhysicalAddress::from_raw(i * L3_PAGE_SIZE + self.offset));
return Ok(PhysicalAddress::from_usize(i * L3_PAGE_SIZE + self.offset));
}
if self.last_free_bit != 0 {
@ -114,7 +111,7 @@ impl PhysicalMemoryManager {
STATS.used_pages.fetch_add(512, Ordering::Relaxed);
return Ok(PhysicalAddress::from_raw(i * L3_PAGE_SIZE + self.offset));
return Ok(PhysicalAddress::from_usize(i * L3_PAGE_SIZE + self.offset));
}
if self.last_free_bit != 0 {
@ -141,7 +138,7 @@ impl PhysicalMemoryManager {
STATS.used_pages.fetch_add(count, Ordering::Relaxed);
return Ok(PhysicalAddress::from_raw(i * L3_PAGE_SIZE + self.offset));
return Ok(PhysicalAddress::from_usize(i * L3_PAGE_SIZE + self.offset));
}
if self.last_free_bit != 0 {
@ -158,7 +155,7 @@ impl PhysicalMemoryManager {
///
/// `addr` must be a page-aligned physical address previously allocated by this implementation.
pub unsafe fn free_page(&mut self, page: PhysicalAddress) {
let page: usize = page.into_raw();
let page = page.into_usize();
assert!(page >= self.offset);
let index = (page - self.offset) / L3_PAGE_SIZE;
@ -174,7 +171,7 @@ impl PhysicalMemoryManager {
///
/// Will panic if the address does not point to a valid, reserved (and unallocated) page.
pub fn add_available_page(&mut self, page: PhysicalAddress) {
let page: usize = page.into_raw();
let page = page.into_usize();
assert!(page >= self.offset);
let index = (page - self.offset) / L3_PAGE_SIZE;

14
kernel/libk/libk-mm/src/phys/mod.rs
View File

@ -1,7 +1,7 @@
use core::ops::Range;
use kernel_arch::mem::PhysicalMemoryAllocator;
use libk_mm_interface::address::{FromRaw, IntoRaw, PhysicalAddress};
use libk_mm_interface::address::PhysicalAddress;
use libk_util::{sync::IrqSafeSpinlock, OneTimeInit};
use yggdrasil_abi::{error::Error, system::SystemMemoryStats};
@ -30,7 +30,7 @@ pub struct PhysicalMemoryRegion {
}
// 8 * 4096 bits per page, 1 page per bit
const MEMORY_UPPER_LIMIT: PhysicalAddress = PhysicalAddress::from_raw(TRACKED_PAGE_LIMIT * 4096);
const MEMORY_UPPER_LIMIT: PhysicalAddress = PhysicalAddress::from_usize(TRACKED_PAGE_LIMIT * 4096);
/// Global physical memory manager
pub static PHYSICAL_MEMORY: OneTimeInit<IrqSafeSpinlock<PhysicalMemoryManager>> =
@ -191,12 +191,12 @@ pub unsafe fn init_from_iter<
},
);
if IntoRaw::<usize>::into_raw(phys_start) & (L2_PAGE_SIZE - 1) != 0 {
if phys_start.into_usize() & (L2_PAGE_SIZE - 1) != 0 {
todo!();
}
let mut manager =
PhysicalMemoryManager::new(page_bitmap_phys_base, phys_start.into_raw(), total_count);
PhysicalMemoryManager::new(page_bitmap_phys_base, phys_start.into_usize(), total_count);
let mut collected = 0;
const MAX_MEMORY: usize = 64 * 1024;
@ -228,10 +228,10 @@ fn kernel_physical_memory_region() -> PhysicalMemoryRegion {
static __kernel_end: u8;
}
let start = unsafe { addr_of!(__kernel_start) };
let end = unsafe { addr_of!(__kernel_end) };
let start = addr_of!(__kernel_start);
let end = addr_of!(__kernel_end);
let base = PhysicalAddress::from_raw(start.addr() - kernel_arch::KERNEL_VIRT_OFFSET);
let base = PhysicalAddress::from_usize(start.addr() - kernel_arch::KERNEL_VIRT_OFFSET);
let size = end.addr() - start.addr();
PhysicalMemoryRegion { base, size }

2
kernel/libk/libk-util/src/hash_table.rs
View File

@ -23,7 +23,7 @@ where
pub const fn new() -> Self {
Self {
buckets: [const { Vec::new() }; N],
hasher: DefaultHashBuilder::default(),
hasher: DefaultHashBuilder::new(),
}
}
}

3
kernel/libk/libk-util/src/lib.rs
View File

@ -4,9 +4,8 @@
new_uninit,
allocator_api,
let_chains,
inline_const,
const_trait_impl,
effects
build_hasher_default_const_new
)]
extern crate alloc;

2
kernel/libk/src/lib.rs
View File

@ -5,7 +5,6 @@
maybe_uninit_slice,
step_trait,
const_trait_impl,
effects,
slice_ptr_get,
strict_provenance,
never_type,
@ -14,7 +13,6 @@
maybe_uninit_uninit_array,
const_maybe_uninit_uninit_array,
new_uninit,
inline_const,
trait_alias,
if_let_guard,
trait_upcasting,

4
kernel/libk/src/task/runtime/task.rs
View File

@ -36,6 +36,10 @@ impl Termination for () {
fn print(&self) {}
}
impl Termination for ! {
fn print(&self) {}
}
impl<T, E: fmt::Debug> Termination for Result<T, E> {
fn print(&self) {
if let Err(error) = self {

4
kernel/src/arch/aarch64/boot/mod.rs
View File

@ -10,7 +10,7 @@ use kernel_arch_aarch64::CPU_COUNT;
use kernel_fs::devfs;
use libk::task::runtime;
use libk_mm::{
address::{IntoRaw, PhysicalAddress, Virtualize},
address::{PhysicalAddress, Virtualize},
phys,
table::EntryLevel,
};
@ -86,7 +86,7 @@ unsafe extern "C" fn __aarch64_el1_bsp_lower_entry(dtb: PhysicalAddress) -> ! {
let elr = absolute_address!(__aarch64_bsp_upper_entry);
// TODO pass dtb
enter_higher_half(sp, elr, dtb.into_raw());
enter_higher_half(sp, elr, dtb.into_usize());
}
unsafe extern "C" fn __aarch64_bsp_upper_entry(dtb: PhysicalAddress) -> ! {

8
kernel/src/arch/aarch64/gic/mod.rs
View File

@ -17,7 +17,7 @@ use device_tree::{device_tree_driver, dt::DevTreeIndexPropExt};
use kernel_arch_aarch64::{GicInterface, CPU_COUNT};
use libk::{arch::Cpu, device::register_external_interrupt_controller, task::cpu_index};
use libk_mm::{
address::{FromRaw, IntoRaw, PhysicalAddress},
address::PhysicalAddress,
device::{DeviceMemoryIo, RawDeviceMemoryMapping},
};
use libk_util::{sync::IrqSafeSpinlock, OneTimeInit};
@ -53,7 +53,7 @@ impl Device for Gic {
unsafe fn init(&'static self) -> Result<(), Error> {
let gicd_mmio = Arc::new(RawDeviceMemoryMapping::map(
self.gicd_base.into_raw(),
self.gicd_base.into_u64(),
0x1000,
Default::default(),
)?);
@ -227,8 +227,8 @@ device_tree_driver! {
let (gicd_base, _) = reg.cell2_array_item(1, dt.address_cells, dt.size_cells)?;
Some(Box::new(unsafe { Gic::new(
PhysicalAddress::from_raw(gicc_base),
PhysicalAddress::from_raw(gicd_base),
PhysicalAddress::from_u64(gicc_base),
PhysicalAddress::from_u64(gicd_base),
)}))
}
}

8
kernel/src/arch/aarch64/mod.rs
View File

@ -19,7 +19,7 @@ use kernel_arch_aarch64::{
};
use libk::{arch::Cpu, device::external_interrupt_controller};
use libk_mm::{
address::{FromRaw, IntoRaw, PhysicalAddress},
address::PhysicalAddress,
phys::PhysicalMemoryRegion,
phys::{self, reserved::reserve_region},
pointer::PhysicalRef,
@ -121,8 +121,8 @@ impl AArch64 {
let initrd_start = initrd_start.cell1_array_item(0, address_cells)?;
let initrd_end = initrd_end.cell1_array_item(0, address_cells)?;
let initrd_start = PhysicalAddress::from_raw(initrd_start);
let initrd_end = PhysicalAddress::from_raw(initrd_end);
let initrd_start = PhysicalAddress::from_u64(initrd_start);
let initrd_end = PhysicalAddress::from_u64(initrd_end);
Some((initrd_start, initrd_end))
}
@ -144,7 +144,7 @@ impl AArch64 {
}
}
MEMORY_LIMIT.store(memory_end.into_raw(), Ordering::Release);
MEMORY_LIMIT.store(memory_end.into_usize(), Ordering::Release);
Ok(())
}

22
kernel/src/arch/x86_64/acpi.rs
View File

@ -18,7 +18,7 @@ use device_api::{
use kernel_arch_x86_64::CPU_COUNT;
use libk::device::external_interrupt_controller;
use libk_mm::{
address::{FromRaw, PhysicalAddress, Virtualize},
address::{PhysicalAddress, Virtualize},
heap::GLOBAL_HEAP,
pointer::PhysicalRef,
};
@ -87,7 +87,7 @@ impl acpi_system::Handler for AcpiHandlerImpl {
unsafe fn map_slice(address: u64, length: u64) -> Self::MappedSlice {
PhysicalRef::map_slice(
PhysicalAddress::from_raw(address),
PhysicalAddress::from_u64(address),
length.try_into().unwrap(),
)
}
@ -126,47 +126,47 @@ impl acpi_system::Handler for AcpiHandlerImpl {
}
fn mem_read_u8(address: u64) -> u8 {
let value = unsafe { read_memory(PhysicalAddress::from_raw(address)) };
let value = unsafe { read_memory(PhysicalAddress::from_u64(address)) };
log::trace!("mem_read_u8 {:#x} -> {:#x}", address, value);
value
}
fn mem_read_u16(address: u64) -> u16 {
let value = unsafe { read_memory(PhysicalAddress::from_raw(address)) };
let value = unsafe { read_memory(PhysicalAddress::from_u64(address)) };
log::trace!("mem_read_u16 {:#x} -> {:#x}", address, value);
value
}
fn mem_read_u32(address: u64) -> u32 {
let value = unsafe { read_memory(PhysicalAddress::from_raw(address)) };
let value = unsafe { read_memory(PhysicalAddress::from_u64(address)) };
log::trace!("mem_read_u32 {:#x} -> {:#x}", address, value);
value
}
fn mem_read_u64(address: u64) -> u64 {
let value = unsafe { read_memory(PhysicalAddress::from_raw(address)) };
let value = unsafe { read_memory(PhysicalAddress::from_u64(address)) };
log::trace!("mem_read_u64 {:#x} -> {:#x}", address, value);
value
}
fn mem_write_u8(address: u64, value: u8) {
log::trace!("mem_write_u8 {:#x}, {:#x}", address, value);
unsafe { write_memory(PhysicalAddress::from_raw(address), value) }
unsafe { write_memory(PhysicalAddress::from_u64(address), value) }
}
fn mem_write_u16(address: u64, value: u16) {
log::trace!("mem_write_u16 {:#x}, {:#x}", address, value);
unsafe { write_memory(PhysicalAddress::from_raw(address), value) }
unsafe { write_memory(PhysicalAddress::from_u64(address), value) }
}
fn mem_write_u32(address: u64, value: u32) {
log::trace!("mem_write_u32 {:#x}, {:#x}", address, value);
unsafe { write_memory(PhysicalAddress::from_raw(address), value) }
unsafe { write_memory(PhysicalAddress::from_u64(address), value) }
}
fn mem_write_u64(address: u64, value: u64) {
log::trace!("mem_write_u64 {:#x}, {:#x}", address, value);
unsafe { write_memory(PhysicalAddress::from_raw(address), value) }
unsafe { write_memory(PhysicalAddress::from_u64(address), value) }
}
fn install_interrupt_handler(irq: u32) -> Result<(), AcpiSystemError> {
@ -327,7 +327,7 @@ impl AcpiHandler for AcpiHandlerImpl {
PhysicalMapping::new(
physical_address,
NonNull::new_unchecked(
PhysicalAddress::from_raw(physical_address).virtualize() as *mut T
PhysicalAddress::from_usize(physical_address).virtualize() as *mut T
),
size,
size,

7
kernel/src/arch/x86_64/apic/ioapic.rs
View File

@ -8,10 +8,7 @@ use device_api::{
},
Device,
};
use libk_mm::{
address::{FromRaw, PhysicalAddress},
device::DeviceMemoryIo,
};
use libk_mm::{address::PhysicalAddress, device::DeviceMemoryIo};
use libk_util::sync::IrqSafeSpinlock;
use tock_registers::{
interfaces::{Readable, Writeable},
@ -281,7 +278,7 @@ impl IoApic {
// let mapping = unsafe { DeviceMemoryMapping::map(base, size) };
let regs = unsafe {
DeviceMemoryIo::<'_, Regs>::map(
PhysicalAddress::from_raw(ioapic.address as u64),
PhysicalAddress::from_u64(ioapic.address as u64),
Default::default(),
)?
};

10
kernel/src/arch/x86_64/apic/local.rs
View File

@ -14,11 +14,7 @@ use kernel_arch_x86_64::{
mem::table::L3, registers::MSR_IA32_APIC_BASE, LocalApicInterface, CPU_COUNT,
};
use libk::arch::Cpu;
use libk_mm::{
address::{FromRaw, IntoRaw, PhysicalAddress},
device::DeviceMemoryIo,
table::EntryLevelExt,
};
use libk_mm::{address::PhysicalAddress, device::DeviceMemoryIo, table::EntryLevelExt};
use libk_util::{
sync::{IrqGuard, IrqSafeSpinlock},
OneTimeInit,
@ -256,7 +252,7 @@ impl MessageInterruptController for LocalApic {
);
let value = 32 + APIC_MSI_OFFSET + i as u32;
let address = IntoRaw::<usize>::into_raw(Self::base()) | ((self.id as usize) << 12);
let address = Self::base().into_usize() | ((self.id as usize) << 12);
*msi = MsiInfo {
address,
@ -363,7 +359,7 @@ impl LocalApic {
#[inline]
fn base() -> PhysicalAddress {
PhysicalAddress::from_raw(MSR_IA32_APIC_BASE.read_base())
PhysicalAddress::from_u64(MSR_IA32_APIC_BASE.read_base())
}
#[inline]

23
kernel/src/arch/x86_64/mod.rs
View File

@ -18,7 +18,7 @@ use kernel_fs::devfs;
use libk::{arch::Cpu, device::register_external_interrupt_controller};
use libk_device::register_monotonic_timestamp_provider;
use libk_mm::{
address::{FromRaw, IntoRaw, PhysicalAddress, Virtualize},
address::{PhysicalAddress, Virtualize},
phys::{self, reserved::reserve_region, PhysicalMemoryRegion},
table::{EntryLevel, EntryLevelExt},
};
@ -114,7 +114,7 @@ impl X86_64 {
reserve_region(
"mmap",
PhysicalMemoryRegion {
base: PhysicalAddress::from_raw(data.memory_map.address),
base: PhysicalAddress::from_u64(data.memory_map.address),
size: data.memory_map.len as usize * size_of::<AvailableMemoryRegion>(),
},
);
@ -129,7 +129,7 @@ impl X86_64 {
reserve_region(
"initrd",
PhysicalMemoryRegion {
base: PhysicalAddress::from_raw(aligned_start),
base: PhysicalAddress::from_u64(aligned_start),
size: (aligned_end - aligned_start) as usize,
},
);
@ -146,7 +146,8 @@ impl X86_64 {
_memory_start: PhysicalAddress,
memory_end: PhysicalAddress,
) -> Result<(), Error> {
let end_l1i = IntoRaw::<usize>::into_raw(memory_end)
let end_l1i = memory_end
.into_usize()
.page_align_up::<L1>()
.page_index::<L1>();
@ -157,7 +158,7 @@ impl X86_64 {
);
}
MEMORY_LIMIT.store(memory_end.into_raw(), Ordering::Release);
MEMORY_LIMIT.store(memory_end.into_usize(), Ordering::Release);
// Check if 1GiB pages are supported
if PROCESSOR_FEATURES
@ -169,7 +170,7 @@ impl X86_64 {
// TODO NX
unsafe {
RAM_MAPPING_L1[l1i] = PageEntry::<L1>::block(
PhysicalAddress::from_raw(l1i * L1::SIZE),
PhysicalAddress::from_usize(l1i * L1::SIZE),
PageAttributes::WRITABLE,
);
}
@ -205,7 +206,7 @@ impl X86_64 {
for l2i in 0..512 {
// TODO NX
l2[l2i] = PageEntry::<L2>::block(
PhysicalAddress::from_raw((l1i * L1::SIZE) | (l2i * L2::SIZE)),
PhysicalAddress::from_usize((l1i * L1::SIZE) | (l2i * L2::SIZE)),
PageAttributes::WRITABLE,
);
}
@ -226,13 +227,13 @@ impl X86_64 {
unsafe fn init_physical_memory_from_yboot(data: &LoadProtocolV1) -> Result<(), Error> {
let mmap = EarlyMapping::<AvailableMemoryRegion>::map_slice(
PhysicalAddress::from_raw(data.memory_map.address),
PhysicalAddress::from_u64(data.memory_map.address),
data.memory_map.len as usize,
)?;
phys::init_from_iter(
mmap.as_ref().iter().map(|reg| PhysicalMemoryRegion {
base: PhysicalAddress::from_raw(reg.start_address),
base: PhysicalAddress::from_u64(reg.start_address),
size: reg.page_count as usize * L3::SIZE,
}),
Self::map_physical_memory,
@ -305,7 +306,7 @@ impl X86_64 {
match self.boot_data.get() {
&BootData::YBoot(data) => {
let start = PhysicalAddress::from_raw(data.initrd_address);
let start = PhysicalAddress::from_u64(data.initrd_address);
Self::init_initrd(start, start.add(data.initrd_size as usize));
}
}
@ -407,7 +408,7 @@ impl X86_64 {
let info = &data.opt_framebuffer;
self.framebuffer.init(LinearFramebuffer::from_physical_bits(
PhysicalAddress::from_raw(info.res_address),
PhysicalAddress::from_u64(info.res_address),
info.res_size as usize,
info.res_stride as usize,
info.res_width,

8
kernel/src/arch/x86_64/smp.rs
View File

@ -13,7 +13,7 @@ use kernel_arch_x86_64::{
};
use libk::arch::Cpu;
use libk_mm::{
address::{AsPhysicalAddress, FromRaw, IntoRaw, PhysicalAddress, Virtualize},
address::{AsPhysicalAddress, PhysicalAddress, Virtualize},
phys,
pointer::PhysicalRefMut,
TableAllocatorImpl,
@ -26,8 +26,8 @@ use super::acpi::AcpiAllocator;
static AP_BOOTSTRAP_BIN: &[u8] = include_bytes!(concat!(env!("OUT_DIR"), "/__x86_64_ap_boot.bin"));
const AP_STACK_PAGES: usize = 8;
const AP_BOOTSTRAP_DATA: PhysicalAddress = PhysicalAddress::from_raw(0x6000usize);
const AP_BOOTSTRAP_CODE: PhysicalAddress = PhysicalAddress::from_raw(0x7000usize);
const AP_BOOTSTRAP_DATA: PhysicalAddress = PhysicalAddress::from_u64(0x6000);
const AP_BOOTSTRAP_CODE: PhysicalAddress = PhysicalAddress::from_u64(0x7000);
#[repr(C)]
#[allow(dead_code)]
@ -94,7 +94,7 @@ pub unsafe fn start_ap_cores(info: &ProcessorInfo<AcpiAllocator>) {
identity_l2[0] = PageEntry::<L2>::block(PhysicalAddress::ZERO, PageAttributes::WRITABLE);
assert_eq!(KERNEL_TABLES.l0.data[0], 0);
KERNEL_TABLES.l0.data[0] = IntoRaw::<u64>::into_raw(identity_l1.as_physical_address())
KERNEL_TABLES.l0.data[0] = identity_l1.as_physical_address().into_u64()
| (PageAttributes::WRITABLE | PageAttributes::PRESENT).bits();
// Load AP_BOOTSTRAP_CODE

6
kernel/src/device/bus/dt_pci.rs
View File

@ -6,7 +6,7 @@ use device_tree::{
device_tree_driver,
dt::{self, DevTreeIndexNodeExt, DevTreeIndexPropExt, DevTreeNodeInfo},
};
use libk_mm::address::{FromRaw, PhysicalAddress};
use libk_mm::address::PhysicalAddress;
use ygg_driver_pci::{
device::{PciInterrupt, PciInterruptPin, PciInterruptRoute},
PciAddress, PciAddressRange, PciBusManager, PciRangeType,
@ -48,7 +48,7 @@ fn extract_ranges(dt: &DevTreeNodeInfo) -> Vec<PciAddressRange> {
_ => unimplemented!(),
};
let host_base = PhysicalAddress::from_raw(match dt.address_cells {
let host_base = PhysicalAddress::from_u64(match dt.address_cells {
2 => {
let hi = ranges
.cell1_array_item(i * cells_per_range + pci_address_cells, 1)
@ -164,7 +164,7 @@ device_tree_driver! {
let (cfg_space_base, _) = reg
.cell2_array_item(0, dt.address_cells, dt.size_cells)
.unwrap();
let cfg_space_base = PhysicalAddress::from_raw(cfg_space_base);
let cfg_space_base = PhysicalAddress::from_u64(cfg_space_base);
let bus_start = bus_range.cell1_array_item(0, 1)? as u8;
let bus_end = bus_range.cell1_array_item(1, 1)? as u8;

4
kernel/src/device/bus/mod.rs
View File

@ -1,6 +1,6 @@
//! Bus devices
#[cfg(target_arch = "aarch64")]
#[cfg(any(target_arch = "aarch64", rust_analyzer))]
pub mod dt_pci;
#[cfg(target_arch = "aarch64")]
#[cfg(any(target_arch = "aarch64", rust_analyzer))]
pub mod simple_bus;

4
kernel/src/device/display/linear_fb.rs
View File

@ -9,7 +9,7 @@ use abi::{error::Error, io::DeviceRequest, process::ProcessId};
use device_api::Device;
use libk::{task::thread::Thread, vfs::block::BlockDevice};
use libk_mm::{
address::{IntoRaw, PhysicalAddress},
address::PhysicalAddress,
device::{DeviceMemoryAttributes, DeviceMemoryCaching, RawDeviceMemoryMapping},
table::{EntryLevel, MapAttributes},
PageProvider,
@ -56,7 +56,7 @@ impl LinearFramebuffer {
) -> Result<Self, Error> {
let base = unsafe {
RawDeviceMemoryMapping::map(
phys_base.into_raw(),
phys_base.into(),
size,
DeviceMemoryAttributes {
caching: DeviceMemoryCaching::Cacheable,

7
kernel/src/device/serial/pl011.rs
View File

@ -14,10 +14,7 @@ use libk::{
device::external_interrupt_controller,
vfs::{CharDevice, FileReadiness},
};
use libk_mm::{
address::{FromRaw, PhysicalAddress},
device::DeviceMemoryIo,
};
use libk_mm::{address::PhysicalAddress, device::DeviceMemoryIo};
use libk_util::{sync::IrqSafeSpinlock, OneTimeInit};
use tock_registers::{
interfaces::{ReadWriteable, Readable, Writeable},
@ -247,7 +244,7 @@ device_tree_driver! {
// TODO obtain IRQ from dt
irq: Irq::External(1),
context: TtyContext::new(),
base: PhysicalAddress::from_raw(base)
base: PhysicalAddress::from_u64(base)
}))
}
}

3
kernel/src/main.rs
View File

@ -4,9 +4,7 @@
decl_macro,
naked_functions,
asm_const,
panic_info_message,
optimize_attribute,
effects,
const_trait_impl,
maybe_uninit_slice,
arbitrary_self_types,
@ -22,7 +20,6 @@
iter_collect_into,
iter_next_chunk,
exact_size_is_empty,
inline_const,
maybe_uninit_uninit_array,
const_maybe_uninit_uninit_array,
never_type

7
kernel/src/panic.rs
View File

@ -8,7 +8,7 @@ use libk_util::sync::{hack_locks, SpinFence};
use crate::{
arch::{Platform, PLATFORM},
debug::{debug_internal, LogLevel},
debug::LogLevel,
device::display::console::flush_consoles,
};
@ -80,10 +80,7 @@ pub(crate) fn panic_handler(pi: &core::panic::PanicInfo) -> ! {
log_print_raw!(LogLevel::Fatal, "\n");
if let Some(msg) = pi.message() {
debug_internal(*msg, LogLevel::Fatal);
log_print_raw!(LogLevel::Fatal, "\n");
}
log_print_raw!(LogLevel::Fatal, "{}\n", pi.message());
log_print_raw!(LogLevel::Fatal, "--- END PANIC ---\n");

1
lib/qemu/.gitignore vendored Normal file
View File

@ -0,0 +1 @@
/target

7
lib/qemu/Cargo.lock generated Normal file
View File

@ -0,0 +1,7 @@
# This file is automatically @generated by Cargo.
# It is not intended for manual editing.
version = 3
[[package]]
name = "qemu"
version = "0.1.0"

6
lib/qemu/Cargo.toml Normal file
View File

@ -0,0 +1,6 @@
[package]
name = "qemu"
version = "0.1.0"
edition = "2021"
[dependencies]

153
lib/qemu/src/aarch64.rs Normal file
View File

@ -0,0 +1,153 @@
use std::{path::PathBuf, process::Command};
use crate::{Architecture, IntoArgs};
#[derive(Debug)]
pub enum Machine {
Virt { virtualize: bool },
}
#[derive(Debug)]
pub enum Cpu {
CortexA57,
}
#[derive(Debug)]
pub enum Image {
Kernel {
kernel: PathBuf,
initrd: Option<PathBuf>,
},
}
#[derive(Debug)]
pub struct QemuAArch64;
impl IntoArgs for Machine {
fn add_args(&self, command: &mut Command) {
command.arg("-M");
match self {
&Self::Virt { virtualize } => {
let mut arg = "virt".to_owned();
if virtualize {
arg.push_str(",virtualization=on");
}
command.arg(arg);
}
}
}
}
impl IntoArgs for Cpu {
fn add_args(&self, command: &mut Command) {
command.arg("-cpu");
match self {
Self::CortexA57 => {
command.arg("cortex-a57");
}
}
}
}
impl IntoArgs for Image {
fn add_args(&self, command: &mut Command) {
match self {
Self::Kernel { kernel, initrd } => {
command.arg("-kernel").arg(kernel);
if let Some(initrd) = initrd {
command.arg("-initrd").arg(initrd);
}
}
}
}
}
impl IntoArgs for QemuAArch64 {
fn add_args(&self, _command: &mut Command) {}
}
impl Architecture for QemuAArch64 {
type MachineType = Machine;
type CpuType = Cpu;
type ImageType = Image;
const DEFAULT_COMMAND: &'static str = "qemu-system-aarch64";
}
#[cfg(test)]
mod tests {
use crate::{aarch64::Machine, device::QemuSerialTarget, Qemu};
use super::{Cpu, Image};
#[test]
fn boot_options() {
let mut qemu = Qemu::new_aarch64();
qemu.with_boot_image(Image::Kernel {
kernel: "my-kernel.bin".into(),
initrd: Some("my-initrd.img".into()),
});
let command = qemu.into_command();
assert_eq!(
command.get_args().collect::<Vec<_>>(),
vec!["-kernel", "my-kernel.bin", "-initrd", "my-initrd.img"]
);
let mut qemu = Qemu::new_aarch64();
qemu.with_boot_image(Image::Kernel {
kernel: "my-kernel.bin".into(),
initrd: None,
});
let command = qemu.into_command();
assert_eq!(
command.get_args().collect::<Vec<_>>(),
vec!["-kernel", "my-kernel.bin"]
);
}
#[test]
fn machine_options() {
let mut qemu = Qemu::new_aarch64();
qemu.with_machine(Machine::Virt { virtualize: true });
let command = qemu.into_command();
assert_eq!(
command.get_args().collect::<Vec<_>>(),
vec!["-M", "virt,virtualization=on"]
);
}
#[test]
fn full_commands() {
let mut qemu = Qemu::new_aarch64();
qemu.override_qemu("my-qemu");
qemu.with_boot_image(Image::Kernel {
kernel: "my-kernel.bin".into(),
initrd: Some("my-initrd.img".into()),
});
qemu.with_machine(Machine::Virt { virtualize: false });
qemu.with_cpu(Cpu::CortexA57);
qemu.with_serial(QemuSerialTarget::MonStdio);
let command = qemu.into_command();
assert_eq!(
command.get_args().collect::<Vec<_>>(),
vec![
"-serial",
"mon:stdio",
"-M",
"virt",
"-cpu",
"cortex-a57",
"-kernel",
"my-kernel.bin",
"-initrd",
"my-initrd.img"
]
);
}
}

80
lib/qemu/src/device.rs Normal file
View File

@ -0,0 +1,80 @@
use std::process::Command;
use crate::IntoArgs;
#[derive(Debug)]
pub enum QemuNic {
VirtioPci { mac: Option<String> },
}
#[derive(Debug)]
pub enum QemuDevice {
NetworkTap {
nic: QemuNic,
script: Option<String>,
ifname: Option<String>,
},
}
#[derive(Debug)]
pub enum QemuSerialTarget {
MonStdio,
Stdio,
}
impl IntoArgs for QemuNic {
fn add_args(&self, command: &mut Command) {
match self {
Self::VirtioPci { mac } => {
command.arg("-device");
let mut val = "virtio-net-pci,netdev=net0".to_owned();
if let Some(mac) = mac {
val.push_str(",mac=");
val.push_str(mac);
}
command.arg(val);
}
}
}
}
// TODO separate handling for devices
impl IntoArgs for QemuDevice {
fn add_args(&self, command: &mut Command) {
match self {
Self::NetworkTap {
nic,
script,
ifname,
} => {
command.arg("-netdev");
let mut val = "tap,id=net0".to_owned();
if let Some(script) = script {
val.push_str(",script=");
val.push_str(script);
}
if let Some(ifname) = ifname {
val.push_str(",ifname=");
val.push_str(ifname);
}
command.arg(val);
nic.add_args(command);
}
}
}
}
impl IntoArgs for QemuSerialTarget {
fn add_args(&self, command: &mut Command) {
command.arg("-serial");
match self {
Self::MonStdio => {
command.arg("mon:stdio");
}
Self::Stdio => {
command.arg("stdio");
}
}
}
}

206
lib/qemu/src/lib.rs Normal file
View File

@ -0,0 +1,206 @@
use std::{fmt::Debug, path::PathBuf, process::Command};
use device::{QemuDevice, QemuSerialTarget};
pub mod aarch64;
pub mod x86_64;
pub mod device;
pub trait Architecture: IntoArgs {
type MachineType: IntoArgs;
type CpuType: IntoArgs;
type ImageType: IntoArgs;
const DEFAULT_COMMAND: &'static str;
}
pub trait IntoArgs {
fn add_args(&self, command: &mut Command);
}
impl<T: IntoArgs> IntoArgs for Option<T> {
fn add_args(&self, command: &mut Command) {
if let Some(val) = self {
val.add_args(command);
}
}
}
#[derive(Debug, Default)]
struct QemuCommon {
devices: Vec<QemuDevice>,
serial: Option<QemuSerialTarget>,
}
#[derive(Debug, Default)]
pub struct Qemu<A: Architecture> {
binary_override: Option<PathBuf>,
common: QemuCommon,
cpu: Option<A::CpuType>,
machine: Option<A::MachineType>,
boot_image: Option<A::ImageType>,
no_display: bool,
memory_megabytes: Option<usize>,
smp: Option<usize>,
arch: A,
}
impl Qemu<aarch64::QemuAArch64> {
pub fn new_aarch64() -> Self {
Qemu::new(aarch64::QemuAArch64)
}
}
impl Qemu<x86_64::QemuX86_64> {
pub fn new_x86_64() -> Self {
Qemu::new(x86_64::QemuX86_64::default())
}
pub fn with_bios_image(&mut self, image: PathBuf) -> &mut Self {
self.arch.bios_image = Some(image);
self
}
pub fn with_boot_slot(&mut self, slot: char) -> &mut Self {
self.arch.boot_slot = Some(slot);
self
}
}
impl<A: Architecture> Qemu<A> {
pub fn new(arch: A) -> Self {
Self {
binary_override: None,
common: QemuCommon::default(),
memory_megabytes: None,
no_display: false,
cpu: None,
machine: None,
boot_image: None,
smp: None,
arch,
}
}
pub fn with_device(&mut self, device: QemuDevice) -> &mut Self {
self.common.devices.push(device);
self
}
pub fn with_memory_megabytes(&mut self, value: usize) -> &mut Self {
self.memory_megabytes = Some(value);
self
}
pub fn with_serial(&mut self, serial: QemuSerialTarget) -> &mut Self {
self.common.serial = Some(serial);
self
}
pub fn with_boot_image(&mut self, image: A::ImageType) -> &mut Self {
self.boot_image = Some(image);
self
}
pub fn with_cpu(&mut self, cpu: A::CpuType) -> &mut Self {
self.cpu = Some(cpu);
self
}
pub fn with_machine(&mut self, machine: A::MachineType) -> &mut Self {
self.machine = Some(machine);
self
}
pub fn disable_display(&mut self) -> &mut Self {
self.no_display = true;
self
}
pub fn override_qemu<S: Into<PathBuf>>(&mut self, qemu: S) -> &mut Self {
self.binary_override = Some(qemu.into());
self
}
pub fn into_command(self) -> Command {
let qemu = self
.binary_override
.clone()
.unwrap_or_else(|| A::DEFAULT_COMMAND.into());
let mut command = Command::new(qemu);
self.add_args(&mut command);
command
}
}
impl IntoArgs for QemuCommon {
fn add_args(&self, command: &mut Command) {
self.serial.add_args(command);
}
}
impl<A: Architecture> IntoArgs for Qemu<A> {
fn add_args(&self, command: &mut Command) {
self.common.add_args(command);
for device in &self.common.devices {
device.add_args(command);
}
if let Some(mem) = self.memory_megabytes {
command.args(["-m", &format!("{}m", mem)]);
}
self.machine.add_args(command);
self.cpu.add_args(command);
self.boot_image.add_args(command);
if self.no_display {
command.args(["-display", "none"]);
}
if let Some(smp) = self.smp {
command.args(["-smp", &format!("{}", smp)]);
}
self.arch.add_args(command);
}
}
#[cfg(test)]
mod tests {
use crate::{device::QemuSerialTarget, Qemu};
#[test]
fn empty() {
let builder = Qemu::new_aarch64();
let command = builder.into_command();
assert_eq!(command.get_program(), "qemu-system-aarch64");
assert_eq!(command.get_args().len(), 0);
}
#[test]
fn qemu_override() {
let mut qemu = Qemu::new_aarch64();
qemu.override_qemu("test-qemu");
let command = qemu.into_command();
assert_eq!(command.get_program(), "test-qemu");
}
#[test]
fn common_options() {
let mut qemu = Qemu::new_aarch64();
qemu.with_serial(QemuSerialTarget::MonStdio);
let command = qemu.into_command();
assert_eq!(
command.get_args().collect::<Vec<_>>(),
vec!["-serial", "mon:stdio"]
);
}
}

84
lib/qemu/src/x86_64.rs Normal file
View File

@ -0,0 +1,84 @@
use std::{path::PathBuf, process::Command};
use crate::{Architecture, IntoArgs};
#[derive(Debug)]
pub enum Machine {
Q35,
}
#[derive(Debug)]
pub enum Cpu {
Host { enable_kvm: bool },
}
#[derive(Debug)]
pub enum Image {
Drive(PathBuf),
}
#[derive(Debug, Default)]
pub struct QemuX86_64 {
pub bios_image: Option<PathBuf>,
pub boot_slot: Option<char>,
}
impl IntoArgs for Machine {
fn add_args(&self, command: &mut Command) {
match self {
Self::Q35 => {
command.args(["-M", "q35"]);
}
}
}
}
impl IntoArgs for Cpu {
fn add_args(&self, command: &mut Command) {
match self {
&Self::Host { enable_kvm } => {
command.args(["-cpu", "host"]);
if enable_kvm {
command.arg("-enable-kvm");
}
}
}
}
}
impl IntoArgs for Image {
fn add_args(&self, command: &mut Command) {
match self {
Self::Drive(path) => {
command.args(["-drive", &format!("format=raw,file={}", path.display())]);
}
}
}
}
impl IntoArgs for QemuX86_64 {
fn add_args(&self, command: &mut Command) {
if let Some(slot) = self.boot_slot {
command.arg("-boot");
command.arg(format!("{}", slot));
}
if let Some(bios_image) = self.bios_image.as_ref() {
command.args([
"-drive",
&format!(
"format=raw,if=pflash,readonly=on,file={}",
bios_image.display()
),
]);
}
}
}
impl Architecture for QemuX86_64 {
type MachineType = Machine;
type CpuType = Cpu;
type ImageType = Image;
const DEFAULT_COMMAND: &'static str = "qemu-system-x86_64";
}

2
lib/runtime/src/lib.rs
View File

@ -1,5 +1,5 @@
//! Yggdrasil OS application runtime
#![feature(rustc_private, exposed_provenance)]
#![feature(rustc_private, strict_provenance)]
#![no_std]
#![deny(missing_docs)]
#![allow(nonstandard_style)]

14
tool/abi-generator/src/abi/ty/simple.rs
View File

@ -82,22 +82,22 @@ impl Type for SimpleType {
Self::NonZeroUsize => quote!(#value.into()),
Self::Primitive(ty) => ty.emit_to_syscall_arguments(env, value),
Self::Transparent { .. } => quote!(#value.into_syscall_register()),
Self::Str => quote!(#value.as_ptr().expose_addr(), #value.len()),
Self::Str => quote!(#value.as_ptr().addr(), #value.len()),
Self::Never => todo!("Prevent Never type from being a syscall argument"),
Self::Reference { mutable, pointee } => {
let pointee = pointee.as_rust_type();
match mutable {
true => quote!((#value as *mut #pointee).expose_addr()),
false => quote!((#value as *const #pointee).expose_addr()),
true => quote!((#value as *mut #pointee).addr()),
false => quote!((#value as *const #pointee).addr()),
}
}
Self::Array { mutable, .. } => match mutable {
true => quote!(#value.as_mut_ptr().expose_addr()),
false => quote!(#value.as_ptr().expose_addr()),
true => quote!(#value.as_mut_ptr().addr()),
false => quote!(#value.as_ptr().addr()),
},
Self::Slice { mutable, .. } => match mutable {
true => quote!(#value.as_mut_ptr().expose_addr(), #value.len()),
false => quote!(#value.as_ptr().expose_addr(), #value.len()),
true => quote!(#value.as_mut_ptr().addr(), #value.len()),
false => quote!(#value.as_ptr().addr(), #value.len()),
},
}
}

2
tool/abi-generator/src/lib.rs
View File

@ -1,4 +1,4 @@
#![feature(if_let_guard, extend_one, proc_macro_span)]
#![feature(if_let_guard, extend_one, proc_macro_span, strict_provenance)]
use crate::abi::ty::TypeWidth;

2
userspace/colors/Cargo.toml
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@ -7,7 +7,7 @@ authors = ["Mark Poliakov <mark@alnyan.me>"]
[dependencies]
yggdrasil-abi = { path = "../../lib/abi", features = ["serde"] }
serde-ipc = { path = "../lib/serde-ipc" }
libcolors = { path = "../lib/libcolors", default_features = false }
libcolors = { path = "../lib/libcolors", default-features = false }
flexbuffers = "2.0.0"
lazy_static = "1.4.0"

2
userspace/term/Cargo.toml
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@ -8,5 +8,5 @@ authors = ["Mark Poliakov <mark@alnyan.me>"]
[dependencies]
bytemuck = { version = "1.14.0", features = ["derive"] }
libcolors = { path = "../lib/libcolors", default_features = false, features = ["client"] }
libcolors = { path = "../lib/libcolors", default-features = false, features = ["client"] }
thiserror = "1.0.56"

2
xtask/Cargo.toml
View File

@ -9,7 +9,7 @@ clap = { version = "4.5.1", features = ["env", "derive"] }
git2 = "0.18.2"
thiserror = "1.0.57"
qemu = { git = "https://git.alnyan.me/yggdrasil/qemu.git" }
qemu = { path = "../lib/qemu" }
toml = "0.8.10"
serde = { version = "1.0.197", features = ["derive"] }
which = "6.0.0"