x86-64: couldn't get HPET to work on real hw
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c543576685
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@ -5,6 +5,8 @@ edition = "2021"
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build = "build.rs"
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# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
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[profile.dev.package.tock-registers]
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opt-level = 3
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[dependencies]
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yggdrasil-abi = { git = "https://git.alnyan.me/yggdrasil/yggdrasil-abi.git" }
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@ -22,9 +24,6 @@ tock-registers = "0.8.1"
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cfg-if = "1.0.0"
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git-version = "0.3.5"
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# bitmap-font = { version = "0.3.0", optional = true }
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# embedded-graphics = { version = "0.8.0", optional = true }
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log = "0.4.20"
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futures-util = { version = "0.3.28", default-features = false, features = ["alloc", "async-await"] }
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crossbeam-queue = { version = "0.3.8", default-features = false, features = ["alloc"] }
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@ -2,7 +2,7 @@
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use core::sync::atomic::Ordering;
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use abi::error::Error;
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use acpi_lib::{mcfg::Mcfg, AcpiTables, HpetInfo, InterruptModel};
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use acpi_lib::{mcfg::Mcfg, AcpiTables, InterruptModel};
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use alloc::boxed::Box;
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use cpu::Cpu;
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use device_api::{
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@ -45,7 +45,7 @@ use self::{
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acpi::{AcpiAllocator, AcpiHandlerImpl},
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apic::ioapic::IoApic,
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intrinsics::{IoPort, IoPortAccess},
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peripherals::{hpet::Hpet, ps2::PS2Controller},
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peripherals::{i8253::I8253, ps2::PS2Controller},
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smp::CPU_COUNT,
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};
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@ -140,7 +140,7 @@ pub struct X86_64 {
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combined_terminal: OneTimeInit<CombinedTerminal>,
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ioapic: OneTimeInit<IoApic>,
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timer: OneTimeInit<Hpet>,
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timer: OneTimeInit<I8253>,
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}
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/// x86-64 architecture implementation
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@ -392,9 +392,6 @@ impl X86_64 {
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self.ioapic.init(IoApic::from_acpi(&apic_info).unwrap());
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let hpet = HpetInfo::new(acpi).unwrap();
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self.timer.init(Hpet::from_acpi(&hpet).unwrap());
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acpi::init_acpi(acpi).unwrap();
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// Enumerate PCIe root devices
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@ -442,8 +439,11 @@ impl X86_64 {
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if cpu_id == 0 {
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self.init_acpi_from_boot_data();
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Self::disable_8259();
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self.timer.init(I8253::new());
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// Initialize debug output as soon as possible
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let com1_3 = Box::leak(Box::new(ComPort::new(0x3F8, 0x3E8, IrqNumber::Isa(4))));
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debug::add_sink(com1_3.port_a(), LogLevel::Debug);
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@ -478,7 +478,7 @@ impl X86_64 {
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ps2.init_irq().unwrap();
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device::register_device(self.ioapic.get());
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device::register_device(self.timer.get());
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// device::register_device(self.timer.get());
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device::register_device(ps2);
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// Initialize devices from PCI bus
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@ -1,279 +0,0 @@
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//! x86-64 implementation of a HPET
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use core::time::Duration;
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use abi::error::Error;
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use acpi_lib::hpet::HpetInfo as AcpiHpet;
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use device_api::{
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interrupt::{InterruptHandler, IrqLevel, IrqOptions, IrqTrigger},
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timer::MonotonicTimestampProviderDevice,
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Device,
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};
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use tock_registers::{
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interfaces::{ReadWriteable, Readable, Writeable},
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register_bitfields, register_structs,
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registers::{ReadOnly, ReadWrite},
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};
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use crate::{
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arch::{x86_64::IrqNumber, Architecture, ARCHITECTURE},
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device::timer,
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mem::device::DeviceMemoryIo,
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sync::IrqSafeSpinlock,
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};
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register_bitfields! {
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u64,
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GeneralCapabilities [
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COUNTER_CLK_PERIOD OFFSET(32) NUMBITS(32) [],
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COUNT_SIZE_CAP OFFSET(13) NUMBITS(1) [
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Supports64Bit = 1
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],
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NUM_TIM_CAP OFFSET(8) NUMBITS(5) [],
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],
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GeneralConfiguration [
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LEG_RT_CNF OFFSET(1) NUMBITS(1) [],
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ENABLE_CNF OFFSET(0) NUMBITS(1) [],
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],
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TimerConfigurationCapablities [
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TM_INT_TYPE_CNF OFFSET(1) NUMBITS(1) [
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EdgeTriggered = 0,
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LevelTriggered = 1,
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],
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TM_INT_ENB_CNF OFFSET(2) NUMBITS(1) [
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InterruptEnabled = 1,
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InterruptDisabled = 0
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],
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TM_TYPE_CNF OFFSET(3) NUMBITS(1) [
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Periodic = 1,
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OneShot = 0
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],
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TM_PER_INT_CAP OFFSET(4) NUMBITS(1) [
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SupportsPeriodic = 1,
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],
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TM_SIZE_CAP OFFSET(5) NUMBITS(1) [
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Timer64Bit = 1,
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Timer32Bit = 0,
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],
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TM_VAL_SET_CNF OFFSET(6) NUMBITS(1) [],
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TM_32MODE_CNF OFFSET(8) NUMBITS(1) [],
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TM_INT_ROUTE_CNF OFFSET(9) NUMBITS(5) [],
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TM_FSB_EN_CNF OFFSET(14) NUMBITS(1) [],
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TM_FSB_INT_DEL_CAP OFFSET(15) NUMBITS(1) [],
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TM_INT_ROUTE_CAP OFFSET(32) NUMBITS(32) [],
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]
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}
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register_structs! {
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#[allow(non_snake_case)]
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TimerRegs {
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(0x000 => ConfigurationCapability: ReadWrite<u64, TimerConfigurationCapablities::Register>),
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(0x008 => Comparator: ReadWrite<u64>),
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(0x010 => FsbInterruptRoute: ReadWrite<u64>),
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(0x018 => _0),
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(0x020 => @END),
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}
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}
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register_structs! {
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#[allow(non_snake_case)]
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Regs {
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(0x000 => GeneralCapabilities: ReadOnly<u64, GeneralCapabilities::Register>),
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(0x008 => _0),
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(0x010 => GeneralConfiguration: ReadWrite<u64, GeneralConfiguration::Register>),
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(0x018 => _1),
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(0x020 => GeneralInterruptStatus: ReadWrite<u64>),
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(0x028 => _2),
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(0x0F0 => MainCounter: ReadWrite<u64>),
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(0x0F8 => _3),
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(0x100 => Timers: [TimerRegs; 3]),
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(0x160 => _4),
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(0x400 => @END),
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}
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}
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struct Inner {
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regs: DeviceMemoryIo<Regs>,
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tim0_period: u64,
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tim0_counter: u64,
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}
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/// HPET timer group interface
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pub struct Hpet {
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inner: IrqSafeSpinlock<Inner>,
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}
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impl Inner {
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unsafe fn new(base: usize) -> Result<Self, Error> {
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// Femtoseconds in a millisecond
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const FS_IN_MS: u64 = 1000000000000;
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let regs = DeviceMemoryIo::<Regs>::map("hpet", base)?;
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// Disable the counter first
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regs.GeneralConfiguration
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.modify(GeneralConfiguration::ENABLE_CNF::CLEAR);
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// Disable legacy routing
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regs.GeneralConfiguration
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.modify(GeneralConfiguration::LEG_RT_CNF::CLEAR);
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// Reset the counter
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regs.MainCounter.set(0);
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// Disable all comparator interrupts
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for i in 0..3 {
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regs.Timers[i]
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.ConfigurationCapability
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.modify(TimerConfigurationCapablities::TM_INT_ENB_CNF::InterruptDisabled);
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}
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// Calculate the interrupt period
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let clk_period = regs
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.GeneralCapabilities
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.read(GeneralCapabilities::COUNTER_CLK_PERIOD);
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// Will give an interrupt interval of 1ms
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let tim0_period = FS_IN_MS / clk_period;
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// Enable the main counter
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regs.GeneralConfiguration
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.modify(GeneralConfiguration::ENABLE_CNF::SET);
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Ok(Self {
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regs,
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tim0_period,
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tim0_counter: 0,
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})
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}
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}
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impl MonotonicTimestampProviderDevice for Hpet {
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fn monotonic_timestamp(&self) -> Result<Duration, Error> {
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let inner = self.inner.lock();
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let counter = inner.regs.MainCounter.get();
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let period = inner.tim0_period;
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Ok(Duration::from_millis(counter / period))
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}
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}
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impl InterruptHandler for Hpet {
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fn handle_irq(&self) -> bool {
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let now = {
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let mut inner = self.inner.lock();
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inner.regs.GeneralInterruptStatus.set(1);
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inner.tim0_counter = inner.tim0_counter.wrapping_add(1);
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Duration::from_millis(inner.tim0_counter)
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};
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timer::tick(now);
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true
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}
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}
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impl Device for Hpet {
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fn display_name(&self) -> &'static str {
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"HPET"
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}
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unsafe fn init_irq(&'static self) -> Result<(), Error> {
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// Configure timer 0
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let intc = ARCHITECTURE.external_interrupt_controller();
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let inner = self.inner.lock();
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let tim0 = &inner.regs.Timers[0];
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if inner.tim0_period > 0x100000000
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&& !tim0
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.ConfigurationCapability
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.matches_all(TimerConfigurationCapablities::TM_SIZE_CAP::Timer64Bit)
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{
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panic!("Period is too large and timer doesn't support 64-bit");
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}
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// Temporarily disable the main counter
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inner
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.regs
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.GeneralConfiguration
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.modify(GeneralConfiguration::ENABLE_CNF::CLEAR);
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assert!(tim0
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.ConfigurationCapability
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.matches_all(TimerConfigurationCapablities::TM_PER_INT_CAP::SupportsPeriodic));
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let mut tim0_irq = None;
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let tim0_irqs = tim0
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.ConfigurationCapability
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.read(TimerConfigurationCapablities::TM_INT_ROUTE_CAP);
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// Skip most likely legacy routes: IRQ2, IRQ0
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for i in 3..32 {
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if tim0_irqs & (1 << i) != 0 {
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tim0_irq = Some(i);
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break;
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}
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}
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let tim0_irq = tim0_irq.expect("Could not pick an IRQ for HPET TIM0");
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// Bind and enable the IRQ
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let irq = IrqNumber::Gsi(tim0_irq);
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intc.register_irq(
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irq,
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IrqOptions {
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level: IrqLevel::ActiveLow,
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trigger: IrqTrigger::Level,
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},
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self,
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)?;
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intc.enable_irq(irq)?;
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// Disable FSB interrupt route and 32 bit mode
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tim0.ConfigurationCapability.modify(
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TimerConfigurationCapablities::TM_FSB_EN_CNF::CLEAR
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+ TimerConfigurationCapablities::TM_32MODE_CNF::CLEAR
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+ TimerConfigurationCapablities::TM_VAL_SET_CNF::SET,
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);
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// Setup interrupt route + edge-triggered
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tim0.ConfigurationCapability.modify(
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TimerConfigurationCapablities::TM_INT_ROUTE_CNF.val(tim0_irq as u64)
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+ TimerConfigurationCapablities::TM_INT_TYPE_CNF::LevelTriggered,
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);
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// Setup periodic mode
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tim0.ConfigurationCapability
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.modify(TimerConfigurationCapablities::TM_TYPE_CNF::Periodic);
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// Set the comparator
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tim0.Comparator.set(inner.tim0_period);
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// Enable the timer
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tim0.ConfigurationCapability
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.modify(TimerConfigurationCapablities::TM_INT_ENB_CNF::InterruptEnabled);
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// Reenable the main counter
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inner
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.regs
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.GeneralConfiguration
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.modify(GeneralConfiguration::ENABLE_CNF::SET);
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Ok(())
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}
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}
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impl Hpet {
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/// Creates a HPET instance from its ACPI definition
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pub fn from_acpi(info: &AcpiHpet) -> Result<Self, Error> {
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infoln!("Initializing HPET:");
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infoln!("Address: {:#x}", info.base_address);
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let inner = unsafe { Inner::new(info.base_address) }?;
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Ok(Self {
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inner: IrqSafeSpinlock::new(inner),
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})
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}
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}
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97
src/arch/x86_64/peripherals/i8253.rs
Normal file
97
src/arch/x86_64/peripherals/i8253.rs
Normal file
@ -0,0 +1,97 @@
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use core::time::Duration;
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use abi::error::Error;
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use device_api::{interrupt::InterruptHandler, timer::MonotonicTimestampProviderDevice, Device};
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use crate::{
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arch::{
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x86_64::{
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intrinsics::{IoPort, IoPortAccess},
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IrqNumber,
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},
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Architecture, ARCHITECTURE,
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},
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sync::IrqSafeSpinlock,
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task::runtime,
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};
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const FREQUENCY: u32 = 1193180;
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const CMD_CH0: u8 = 0 << 6;
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const CMD_ACC_WORD: u8 = 3 << 4;
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const CMD_MODE_RATE: u8 = 2 << 1;
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struct Inner {
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ch0_data: IoPort<u8>,
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#[allow(unused)]
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ch1_data: IoPort<u8>,
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#[allow(unused)]
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ch2_data: IoPort<u8>,
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cmd: IoPort<u8>,
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tick: u64,
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}
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pub struct I8253 {
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inner: IrqSafeSpinlock<Inner>,
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}
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impl MonotonicTimestampProviderDevice for I8253 {
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fn monotonic_timestamp(&self) -> Result<Duration, Error> {
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let tick = self.inner.lock().tick;
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Ok(Duration::from_millis(tick))
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}
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}
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impl InterruptHandler for I8253 {
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fn handle_irq(&self) -> bool {
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let mut inner = self.inner.lock();
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inner.tick += 1;
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let now = Duration::from_millis(inner.tick);
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drop(inner);
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runtime::tick(now);
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true
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}
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}
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impl Device for I8253 {
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fn display_name(&self) -> &'static str {
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"i8253 PIT"
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}
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unsafe fn init_irq(&'static self) -> Result<(), Error> {
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let intc = ARCHITECTURE.external_interrupt_controller();
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let inner = self.inner.lock();
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let div: u16 = (FREQUENCY / 1000).try_into().unwrap();
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inner.cmd.write(CMD_CH0 | CMD_ACC_WORD | CMD_MODE_RATE);
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inner.ch0_data.write(div as u8);
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inner.ch0_data.write((div >> 8) as u8);
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let irq = IrqNumber::Isa(0);
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intc.register_irq(irq, Default::default(), self)?;
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intc.enable_irq(irq)?;
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Ok(())
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}
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}
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impl I8253 {
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pub const fn new() -> Self {
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Self {
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inner: IrqSafeSpinlock::new(Inner {
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ch0_data: IoPort::new(0x40),
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ch1_data: IoPort::new(0x41),
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ch2_data: IoPort::new(0x42),
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cmd: IoPort::new(0x43),
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tick: 0,
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}),
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}
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}
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}
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@ -1,5 +1,5 @@
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//! x86-64 platform peripheral drivers
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pub mod hpet;
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pub mod i8253;
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pub mod ps2;
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pub mod serial;
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