nvme: dma cache flush, better performance (played with timer)

kernel/arch/x86_64/src/lib.rs

@@ -5,7 +5,7 @@
 extern crate alloc;
 
 use core::{
-    ops::DerefMut,
+    ops::{DerefMut, Range},
     sync::atomic::{AtomicUsize, Ordering},
 };
 
@@ -195,4 +195,30 @@ impl Architecture for ArchitectureImpl {
     fn cpu_available_features<S: Scheduler>(cpu: &CpuImpl<Self, S>) -> Option<&Self::CpuFeatures> {
         Some(&cpu.available_features)
     }
+
+    // Cache/barrier
+
+    fn load_barrier() {
+        unsafe { core::arch::x86_64::_mm_lfence() };
+    }
+
+    fn store_barrier() {
+        unsafe { core::arch::x86_64::_mm_sfence() };
+    }
+
+    fn memory_barrier() {
+        unsafe { core::arch::x86_64::_mm_mfence() };
+    }
+
+    fn flush_virtual_range(range: Range<usize>) {
+        // TODO I assume 64-byte cache line on all CPUs
+        // TODO clflush instruction may not be available, test for it
+        const CLSIZE: usize = 64;
+        let start = range.start & !(CLSIZE - 1);
+        let end = (range.end + (CLSIZE - 1)) & !(CLSIZE - 1);
+
+        for line in (start..end).step_by(CLSIZE) {
+            unsafe { core::arch::x86_64::_mm_clflush(line as _) };
+        }
+    }
 }