From 5b1b69e4672be79caaa27b7b9e78811c23ce9769 Mon Sep 17 00:00:00 2001 From: Mark Poliakov Date: Tue, 21 Jan 2025 19:53:33 +0200 Subject: [PATCH] rv64: remove commented out M-mode CSRs --- kernel/arch/riscv64/src/registers.rs | 319 --------------------------- 1 file changed, 319 deletions(-) diff --git a/kernel/arch/riscv64/src/registers.rs b/kernel/arch/riscv64/src/registers.rs index aa6c0fad..44fcb0ba 100644 --- a/kernel/arch/riscv64/src/registers.rs +++ b/kernel/arch/riscv64/src/registers.rs @@ -27,313 +27,6 @@ macro impl_csr_write($struct:ident, $repr:ty, $reg:ident, $register:ty) { } } -// pub mod misa { -// use tock_registers::{interfaces::Readable, register_bitfields}; -// -// use super::{impl_csr_read, impl_csr_write}; -// -// register_bitfields!( -// u64, -// pub MISA [ -// A OFFSET(0) NUMBITS(1) [], -// C OFFSET(2) NUMBITS(1) [], -// D OFFSET(3) NUMBITS(1) [], -// E OFFSET(4) NUMBITS(1) [], -// F OFFSET(5) NUMBITS(1) [], -// H OFFSET(6) NUMBITS(1) [], -// I OFFSET(7) NUMBITS(1) [], -// M OFFSET(12) NUMBITS(1) [], -// Q OFFSET(16) NUMBITS(1) [], -// S OFFSET(17) NUMBITS(1) [], -// U OFFSET(18) NUMBITS(1) [], -// X OFFSET(23) NUMBITS(1) [], -// ] -// ); -// -// pub struct Reg; -// -// impl_csr_read!(Reg, u64, misa, MISA::Register); -// impl_csr_write!(Reg, u64, misa, MISA::Register); -// -// impl Reg { -// pub fn is_valid(&self) -> bool { -// self.get() != 0 -// } -// } -// -// pub const MISA: Reg = Reg; -// } -// -// pub mod mstatus { -// use tock_registers::register_bitfields; -// -// use super::{impl_csr_read, impl_csr_write}; -// -// register_bitfields!( -// u64, -// pub MSTATUS [ -// /// Interrupt enable for S-mode -// SIE OFFSET(1) NUMBITS(1) [], -// /// Interrupt enable for M-mode -// MIE OFFSET(3) NUMBITS(1) [], -// /// Stored SIE state on S-mode trap delegation -// SPIE OFFSET(5) NUMBITS(1) [], -// /// U-mode big endian -// UBE OFFSET(6) NUMBITS(1) [], -// /// TODO: something written here on trap to M-mode -// MPIE OFFSET(7) NUMBITS(1) [], -// /// TODO: something for nested traps -// SPP OFFSET(8) NUMBITS(1) [], -// /// Vector register dirty status -// VS OFFSET(9) NUMBITS(2) [], -// /// Original mode before being trapped into M-mode -// MPP OFFSET(11) NUMBITS(2) [ -// U = 0, -// S = 1, -// M = 3 -// ], -// /// Float register dirty status -// FS OFFSET(13) NUMBITS(2) [], -// /// U-mode extension dirty status -// XS OFFSET(15) NUMBITS(2) [], -// /// Effective privilege mode at which loads and stores execute. -// /// -// /// When MPRV = 0, loads and stores behave as normal -// /// MPRV = 1, loads/stores are translated and protected -// MPRV OFFSET(17) NUMBITS(1) [], -// /// Permit supervisor user memory access -// /// -// /// When SUM = 0, S-mode access to pages accessible by U-mode will fault -// SUM OFFSET(18) NUMBITS(1) [], -// MXR OFFSET(19) NUMBITS(1) [], -// /// Trap virtual memory -// /// -// /// When TVM = 1, attempts to read/write satp CSR, execute sfence.vma or sinval.vma -// /// in S-mode will raise an illegal instruction exception -// TVM OFFSET(20) NUMBITS(1) [], -// /// Timeout wait -// /// -// /// When TW = 1, wfi executed in lower privilege level which does not complete -// /// within some implementation-specific timeout, raises an illegal -// /// instruction exception -// TW OFFSET(21) NUMBITS(1) [], -// TSR OFFSET(22) NUMBITS(1) [], -// /// U-mode XLEN value -// UXL OFFSET(32) NUMBITS(2) [], -// /// S-mode XLEN value -// SXL OFFSET(34) NUMBITS(2) [], -// /// S-mode big endian -// SBE OFFSET(36) NUMBITS(1) [], -// /// M-mode big endian -// MBE OFFSET(37) NUMBITS(1) [], -// SD OFFSET(63) NUMBITS(1) [], -// ] -// ); -// -// pub struct Reg; -// -// impl_csr_read!(Reg, u64, mstatus, MSTATUS::Register); -// impl_csr_write!(Reg, u64, mstatus, MSTATUS::Register); -// -// pub const MSTATUS: Reg = Reg; -// } -// -// pub mod mepc { -// use super::{impl_csr_read, impl_csr_write}; -// -// pub struct Reg; -// -// impl_csr_read!(Reg, u64, mepc, ()); -// impl_csr_write!(Reg, u64, mepc, ()); -// -// pub const MEPC: Reg = Reg; -// } -// -// pub mod mtvec { -// use tock_registers::{interfaces::ReadWriteable, register_bitfields}; -// -// use super::{impl_csr_read, impl_csr_write}; -// -// pub struct Reg; -// -// register_bitfields!( -// u64, -// pub MTVEC [ -// MODE OFFSET(0) NUMBITS(2) [ -// Direct = 0, -// Vectored = 1 -// ], -// BASE OFFSET(2) NUMBITS(62) [], -// ] -// ); -// -// impl_csr_read!(Reg, u64, mtvec, MTVEC::Register); -// impl_csr_write!(Reg, u64, mtvec, MTVEC::Register); -// -// impl Reg { -// pub fn set_base(&self, base: usize) { -// debug_assert_eq!(base & 0xF, 0); -// let mask = match base & 63 != 0 { -// false => 0, -// true => 0x3 << 62, -// }; -// self.modify(MTVEC::BASE.val(((base as u64) >> 2) | mask)); -// } -// } -// -// pub const MTVEC: Reg = Reg; -// } -// -// pub mod medeleg { -// use tock_registers::register_bitfields; -// -// use super::{impl_csr_read, impl_csr_write}; -// -// pub struct Reg; -// -// register_bitfields!( -// u64, -// pub MEDELEG [ -// ECALL_SMODE OFFSET(9) NUMBITS(1) [], -// ] -// ); -// -// impl_csr_read!(Reg, u64, medeleg, MEDELEG::Register); -// impl_csr_write!(Reg, u64, medeleg, MEDELEG::Register); -// -// pub const MEDELEG: Reg = Reg; -// } -// -// pub mod mideleg { -// use super::{impl_csr_read, impl_csr_write, MIE}; -// -// pub struct Reg; -// -// impl_csr_read!(Reg, u64, mideleg, MIE::Register); -// impl_csr_write!(Reg, u64, mideleg, MIE::Register); -// -// pub const MIDELEG: Reg = Reg; -// } -// -// pub mod mcause { -// use tock_registers::register_bitfields; -// -// use super::{impl_csr_read, impl_csr_write}; -// -// register_bitfields!( -// u64, -// pub MCAUSE [ -// CODE OFFSET(0) NUMBITS(63) [], -// INTERRUPT OFFSET(63) NUMBITS(1) [], -// ] -// ); -// -// pub struct Reg; -// -// impl_csr_read!(Reg, u64, mcause, MCAUSE::Register); -// impl_csr_write!(Reg, u64, mcause, MCAUSE::Register); -// -// pub const MCAUSE: Reg = Reg; -// } -// -// pub mod mie { -// use tock_registers::register_bitfields; -// -// use super::{impl_csr_read, impl_csr_write}; -// -// register_bitfields!( -// u64, -// pub MIE [ -// /// ??? -// SSIE OFFSET(1) NUMBITS(1) [], -// /// ??? -// MSIE OFFSET(3) NUMBITS(1) [], -// /// S-mode timer enable -// STIE OFFSET(5) NUMBITS(1) [], -// /// M-mode timer enable -// MTIE OFFSET(7) NUMBITS(1) [], -// /// S-mode external interrupt enable -// SEIE OFFSET(9) NUMBITS(1) [], -// /// M-mode external interrupt enable -// MEIE OFFSET(11) NUMBITS(1) [], -// ] -// ); -// -// pub struct Reg; -// -// impl_csr_read!(Reg, u64, mie, MIE::Register); -// impl_csr_write!(Reg, u64, mie, MIE::Register); -// -// pub const MIE: Reg = Reg; -// } -// -// pub mod mip { -// use tock_registers::register_bitfields; -// -// use super::{impl_csr_read, impl_csr_write}; -// -// register_bitfields!( -// u64, -// pub MIP [ -// /// ??? -// SSIP OFFSET(1) NUMBITS(1) [], -// /// ??? -// MSIP OFFSET(3) NUMBITS(1) [], -// /// S-mode timer pending -// STIP OFFSET(5) NUMBITS(1) [], -// /// M-mode timer pending -// MTIP OFFSET(7) NUMBITS(1) [], -// /// S-mode external interrupt pending -// SEIP OFFSET(9) NUMBITS(1) [], -// /// M-mode external interrupt pending -// MEIP OFFSET(11) NUMBITS(1) [], -// ] -// ); -// -// pub struct Reg; -// -// impl_csr_read!(Reg, u64, mip, MIP::Register); -// impl_csr_write!(Reg, u64, mip, MIP::Register); -// -// pub const MIP: Reg = Reg; -// } -// -// pub mod mcounteren { -// use tock_registers::register_bitfields; -// -// use super::{impl_csr_read, impl_csr_write}; -// -// register_bitfields!( -// u64, -// pub MCOUNTEREN [ -// /// Enable reading cycle counter from S-mode -// CY OFFSET(1) NUMBITS(1) [], -// /// Enable reading time counter from S-mode -// TM OFFSET(2) NUMBITS(1) [], -// /// Enable reading instret counter from S-mode -// IR OFFSET(3) NUMBITS(1) [], -// ] -// ); -// -// pub struct Reg; -// -// impl_csr_read!(Reg, u64, mcounteren, MCOUNTEREN::Register); -// impl_csr_write!(Reg, u64, mcounteren, MCOUNTEREN::Register); -// -// pub const MCOUNTEREN: Reg = Reg; -// } -// -// pub mod mscratch { -// use super::{impl_csr_read, impl_csr_write}; -// -// pub struct Reg; -// -// impl_csr_read!(Reg, u64, mscratch, ()); -// impl_csr_write!(Reg, u64, mscratch, ()); -// -// pub const MSCRATCH: Reg = Reg; -// } - pub mod satp { use tock_registers::register_bitfields; @@ -517,18 +210,6 @@ pub mod sie { pub const SIE: Reg = Reg; } -// pub use mcause::MCAUSE; -// pub use mcounteren::MCOUNTEREN; -// pub use medeleg::MEDELEG; -// pub use mepc::MEPC; -// pub use mideleg::MIDELEG; -// pub use mie::MIE; -// pub use mip::MIP; -// pub use misa::MISA; -// pub use mscratch::MSCRATCH; -// pub use mstatus::MSTATUS; -// pub use mtvec::MTVEC; - pub use satp::SATP; pub use scause::SCAUSE; pub use sepc::SEPC;