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stmmac: print Tx error statuses

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This commit is contained in:
Mark Poliakov 2025-01-27 16:48:02 +02:00
parent b423fd960f
commit 66ecf49c22
2 changed files with 17 additions and 12 deletions
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15
kernel/driver/net/stmmac/src/lib.rs
View File

@ -164,7 +164,6 @@ impl Device for Stmmac {
// TODO get these params from device tree
regs.DMA.DMASBMR.write(
DMASBMR::FB::SET
+ DMASBMR::AAL::SET
+ DMASBMR::BLEN256::SET
+ DMASBMR::BLEN128::SET
+ DMASBMR::BLEN64::SET
@ -191,13 +190,13 @@ impl Device for Stmmac {
.set(rx_ring_base + (rx_ring_capacity * size_of::<RxDescriptor>()) as u32);
// Setup DMA maximum segmen size, Rx buffer size + max burst len
regs.DMA.DMAC0CR.write(DMACiCR::PBLX8::CLEAR);
regs.DMA
.DMAC0CR
.write(DMACiCR::PBLX8::CLEAR + DMACiCR::MSS.val(1024));
regs.DMA.DMAC0TXCR.write(DMACiTXCR::TXPBL.val(256));
.DMAC0TXCR
.write(DMACiTXCR::TXPBL.val(32) + DMACiTXCR::OSF::SET);
regs.DMA
.DMAC0RXCR
.write(DMAC0RXCR::RBSZ.val(4096) + DMAC0RXCR::RXPBL.val(256));
.write(DMAC0RXCR::RBSZ.val(4096) + DMAC0RXCR::RXPBL.val(32));
// Enable DMA interrupts
// TODO enable abnormal interrupts to handle errors properly
@ -222,9 +221,9 @@ impl Device for Stmmac {
// TODO get TQS, RQS from device tree
regs.MTL
.MTLTXQ0OMR
.write(MTLTXQiOMR::TSF::SET + MTLTXQiOMR::TQS.val(1) + MTLTXQiOMR::TXQEN::Enable);
.write(MTLTXQiOMR::TSF::SET + MTLTXQiOMR::TQS.val(7) + MTLTXQiOMR::TXQEN::Enable);
regs.MTL.MTLRXQ0OMR.write(
MTLRXQiOMR::RQS.val(1)
MTLRXQiOMR::RQS.val(7)
+ MTLRXQiOMR::DIS_TCP_EF::SET
+ MTLRXQiOMR::RSF::SET
+ MTLRXQiOMR::FEP::SET
@ -263,7 +262,7 @@ impl Device for Stmmac {
// Setup link information
regs.MAC
.MACCR
.modify(MACCR::PS::Ps1000Mbps + MACCR::FES::Fes100Mbps + MACCR::DM::FullDuplex);
.modify(MACCR::PS::Ps1000Mbps + MACCR::DM::FullDuplex);
// Start Tx/Rx
regs.MAC.MACCR.modify(MACCR::TE::SET + MACCR::RE::SET);

14
kernel/driver/net/stmmac/src/ring.rs
View File

@ -102,8 +102,10 @@ impl TxRing {
break;
}
if entry.tx_completed() {
// Drop the buffer
if let Some(status) = entry.tx_status() {
if status != 0 {
log::warn!("tx_ring[{index}] error: {status:#x}");
}
let _ = self.buffers[index].take().unwrap();
self.rd = self.rd.wrapping_add(1);
count += 1;
@ -131,8 +133,12 @@ impl TxDescriptor {
}
}
pub fn tx_completed(&self) -> bool {
self.tdes3 & Self::TDES3_OWN == 0
pub fn tx_status(&self) -> Option<u32> {
if self.tdes3 & Self::TDES3_OWN == 0 {
Some(self.tdes3 & !(0xFFFF << 16))
} else {
None
}
}
pub fn setup_tx(