x86: fix hpet on ThinkPad T430 by enabling FSB delivery
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@ -5,7 +5,9 @@ use acpi::HpetInfo;
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use alloc::{collections::btree_map::BTreeMap, format, string::String, sync::Arc};
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use device_api::{
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device::{Device, DeviceInitContext},
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interrupt::{InterruptHandler, Irq, IrqOptions, IrqTrigger, IrqVector},
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interrupt::{
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InterruptAffinity, InterruptHandler, Irq, IrqOptions, IrqTrigger, IrqVector, MsiInfo,
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},
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};
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use libk::{device::external_interrupt_controller, task::runtime, time};
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use libk_mm::{address::PhysicalAddress, device::DeviceMemoryIo};
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@ -16,7 +18,7 @@ use tock_registers::{
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registers::{ReadOnly, ReadWrite},
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};
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use crate::arch::x86::dummy_init_context;
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use crate::arch::{x86::dummy_init_context, x86_64::X86_64};
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register_bitfields! {
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u64,
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@ -49,7 +51,11 @@ register_bitfields! {
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Edge = 0,
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Level = 1,
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],
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]
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],
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Tn_FSB_ROUTE [
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Tn_FSB_INT_VAL OFFSET(0) NUMBITS(32) [],
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Tn_FSB_INT_ADDR OFFSET(32) NUMBITS(32) [],
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],
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}
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register_structs! {
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@ -72,7 +78,7 @@ register_structs! {
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TimerRegs {
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(0x00 => Tn_CONFIG: ReadWrite<u64, Tn_CONFIG::Register>),
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(0x08 => Tn_COMPARATOR: ReadWrite<u64>),
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(0x10 => Tn_FSB_ROUTE: ReadWrite<u64>),
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(0x10 => Tn_FSB_ROUTE: ReadWrite<u64, Tn_FSB_ROUTE::Register>),
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(0x18 => _0),
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(0x20 => @END),
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}
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@ -136,12 +142,20 @@ impl Device for HpetTimer {
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let regs = self.regs.write();
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if regs.is_fsb_capable() {
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log::warn!("TODO: HPET supports FSB interrupt delivery, but the kernel doesn't yet");
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}
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#[cfg(target_arch = "x86_64")]
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let irq = if regs.is_fsb_capable() {
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let lapic = X86_64::cpu_local_apic();
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let msi_info = lapic.register_msi(InterruptAffinity::Any, self.clone())?;
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log::info!(
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"Set up {:?}, period={}t, periodic={}, msi mode",
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self.name,
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self.period,
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self.periodic
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);
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IrqDestination::Fsb(msi_info)
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} else {
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let irq = regs.select_irq().ok_or(Error::InvalidArgument)?;
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log::info!(
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"Set up {:?}, period={}t, periodic={}, irq={:?}",
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self.name,
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@ -159,7 +173,9 @@ impl Device for HpetTimer {
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self.clone(),
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)?;
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intc.enable_irq(irq)?;
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let irq = IrqDestination::Irq(irq);
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IrqDestination::Irq(irq)
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};
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let now = self.parent.read_counter();
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@ -216,6 +232,8 @@ impl HpetTimer {
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let periodic = regs.is_periodic();
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let bits64 = regs.is_64_bit();
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log::info!("hpet{index}: periodic={periodic}, bits64={bits64}, period={period}");
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let timer = Arc::new(HpetTimer {
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name: format!("hpet{index}"),
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regs: IrqSafeRwLock::new(regs),
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@ -235,14 +253,42 @@ impl Hpet {
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fn new(base: PhysicalAddress) -> Result<Self, Error> {
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let regs = unsafe { DeviceMemoryIo::<GeneralRegs>::map(base, Default::default()) }?;
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let base_period = regs.timer_period();
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// qemu: 100000000
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// t430: 14318179
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let base_frequency = FS_IN_S / base_period;
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Ok(Self {
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let hpet = Self {
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base,
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base_period,
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base_frequency,
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regs: IrqSafeRwLock::new(regs),
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timers: IrqSafeRwLock::new(BTreeMap::new()),
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})
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};
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hpet.test_timer_counts()?;
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Ok(hpet)
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}
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fn test_timer_counts(&self) -> Result<(), Error> {
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let regs = self.regs.write();
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regs.stop();
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for _ in 0..10000 {
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core::hint::spin_loop();
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}
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let start = regs.counter();
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regs.start();
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for _ in 0..100000 {
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core::hint::spin_loop();
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}
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regs.stop();
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let now = regs.counter();
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if now > start {
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Ok(())
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} else {
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Err(Error::InvalidOperation)
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}
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}
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pub fn setup_from_acpi(acpi: &HpetInfo) -> Result<Arc<Self>, Error> {
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@ -332,14 +378,28 @@ impl TimerRegs {
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}
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fn enable(&self, irq: IrqDestination) {
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let config = match irq {
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match irq {
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IrqDestination::Irq(Irq::External(irq)) => {
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Tn_CONFIG::Tn_INT_ROUTE_CNF.val(irq as u64) + Tn_CONFIG::Tn_INT_TYPE_CNF::Edge
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self.Tn_CONFIG.modify(
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Tn_CONFIG::Tn_INT_ROUTE_CNF.val(irq as u64)
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+ Tn_CONFIG::Tn_INT_TYPE_CNF::Edge
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+ Tn_CONFIG::Tn_FSB_EN_CNF::CLEAR,
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);
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}
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IrqDestination::Fsb(MsiInfo { address, value, .. }) => {
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let address: u32 = address
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.try_into()
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.expect("FIXME: non-32-bit LAPIC MSI address");
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self.Tn_CONFIG
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.modify(Tn_CONFIG::Tn_INT_TYPE_CNF::Edge + Tn_CONFIG::Tn_FSB_EN_CNF::SET);
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self.Tn_FSB_ROUTE.write(
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Tn_FSB_ROUTE::Tn_FSB_INT_VAL.val(value as u64)
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+ Tn_FSB_ROUTE::Tn_FSB_INT_ADDR.val(address as u64),
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);
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}
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_ => unreachable!(),
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};
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}
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self.Tn_CONFIG.modify(config);
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self.Tn_CONFIG.modify(Tn_CONFIG::Tn_INT_ENB_CNF::SET);
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}
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@ -396,4 +456,5 @@ impl GeneralRegs {
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enum IrqDestination {
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Irq(Irq),
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Fsb(MsiInfo),
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}
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@ -16,7 +16,7 @@ use kernel_arch_x86_64::{
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table::{PageAttributes, PageEntry, PageTable, L1, L2, L3},
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EarlyMapping, MEMORY_LIMIT, RAM_MAPPING_L1, RAM_MAPPING_OFFSET,
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},
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PerCpuData,
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LocalApicInterface, PerCpuData,
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};
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use libk::{
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arch::Cpu,
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@ -471,6 +471,10 @@ impl X86_64 {
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Ok(())
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}
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pub(crate) fn cpu_local_apic() -> Arc<dyn LocalApicInterface> {
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Cpu::local().local_apic.clone()
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}
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}
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impl InitrdSource for LoadProtocolV1 {
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