pci: implement acpi irq route lookup
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Cargo.lock
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Cargo.lock
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@ -15,7 +15,9 @@ pub mod handler;
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pub use handler::AcpiHandlerImpl;
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pub mod aml_handler;
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pub use acpi_system::{EventAction, FixedEvent};
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pub use acpi_system::{
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EventAction, FixedEvent, InterruptPolarity, InterruptTrigger, IrqDescriptor, PciPin,
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};
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static ACPI_SYSTEM: OneTimeInit<IrqSafeSpinlock<AcpiSystem<AcpiHandlerImpl>>> = OneTimeInit::new();
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@ -30,6 +32,19 @@ pub fn add_event_handler<F: Fn(&AcpiSystem<AcpiHandlerImpl>) -> EventAction + 's
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.map_err(|_| Error::InvalidArgument)
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}
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pub fn get_pci_route(
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aml_path: &str,
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device: u16,
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function: u16,
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pin: PciPin,
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) -> Option<IrqDescriptor> {
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ACPI_SYSTEM
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.get()
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.lock()
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.pci_route(aml_path, device, function, pin)
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.ok()
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}
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/// Initializes ACPI management
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pub fn switch_to_acpi(tables: &'static AcpiTables<AcpiHandlerImpl>) -> Result<(), Error> {
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// NOTE mostly broken for real HW
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@ -16,6 +16,7 @@ bitflags.workspace = true
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tock-registers.workspace = true
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[target.'cfg(target_arch = "x86_64")'.dependencies]
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ygg_driver_acpi.path = "../../acpi"
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acpi.workspace = true
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[lints]
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@ -121,7 +121,6 @@ impl PciDeviceInfo {
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// Ignore preferred_mode, the only supported is Legacy
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self.legacy_interrupt_mode()
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};
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IrqSafeRwLock::new(InterruptConfig {
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preferred_mode,
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configured_mode,
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@ -212,11 +211,7 @@ impl PciDeviceInfo {
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address: self.address,
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pin,
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};
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let route = self
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.segment
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.irq_translation_map
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.get(&src)
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.ok_or(Error::InvalidOperation)?;
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let route = self.segment.irq_translation_map.map_interrupt(&src)?;
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log::debug!(
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"PCI {} pin {:?} -> system IRQ #{}",
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55
kernel/driver/bus/pci/src/interrupt.rs
Normal file
55
kernel/driver/bus/pci/src/interrupt.rs
Normal file
@ -0,0 +1,55 @@
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use alloc::collections::btree_map::BTreeMap;
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use libk::error::Error;
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use crate::device::{PciInterrupt, PciInterruptRoute};
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#[derive(Debug)]
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pub enum PciInterruptMap {
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Fixed(BTreeMap<PciInterrupt, PciInterruptRoute>),
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#[cfg(any(target_arch = "x86_64", rust_analyzer))]
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Acpi(alloc::string::String),
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Legacy,
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}
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impl PciInterruptMap {
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pub fn map_interrupt(&self, interrupt: &PciInterrupt) -> Result<PciInterruptRoute, Error> {
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match self {
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Self::Fixed(map) => map.get(interrupt).cloned().ok_or(Error::DoesNotExist),
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#[cfg(any(target_arch = "x86_64", rust_analyzer))]
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Self::Acpi(aml_object_name) => {
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use device_api::interrupt::{IrqLevel, IrqOptions, IrqTrigger};
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use crate::device::PciInterruptPin;
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let aml_pin = match interrupt.pin {
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PciInterruptPin::A => ygg_driver_acpi::PciPin::IntA,
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PciInterruptPin::B => ygg_driver_acpi::PciPin::IntB,
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PciInterruptPin::C => ygg_driver_acpi::PciPin::IntC,
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PciInterruptPin::D => ygg_driver_acpi::PciPin::IntD,
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};
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let aml_route = ygg_driver_acpi::get_pci_route(
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aml_object_name.as_str(),
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interrupt.address.device as u16,
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interrupt.address.function as u16,
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aml_pin,
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)
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.ok_or(Error::DoesNotExist)?;
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let trigger = match aml_route.trigger {
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ygg_driver_acpi::InterruptTrigger::Edge => IrqTrigger::Edge,
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ygg_driver_acpi::InterruptTrigger::Level => IrqTrigger::Level,
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};
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let level = match aml_route.polarity {
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ygg_driver_acpi::InterruptPolarity::ActiveLow => IrqLevel::ActiveLow,
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ygg_driver_acpi::InterruptPolarity::ActiveHigh => IrqLevel::ActiveHigh,
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};
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Ok(PciInterruptRoute {
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options: IrqOptions { trigger, level },
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number: aml_route.irq,
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})
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}
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Self::Legacy => todo!(),
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}
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}
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}
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@ -6,12 +6,14 @@ extern crate alloc;
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use core::fmt;
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#[cfg(target_arch = "x86_64")]
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#[cfg(any(target_arch = "x86_64", rust_analyzer))]
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use acpi::mcfg::McfgEntry;
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use alloc::{collections::BTreeMap, format, sync::Arc, vec::Vec};
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use alloc::{format, sync::Arc, vec::Vec};
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use bitflags::bitflags;
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use device::{PciBusDevice, PciDeviceInfo, PciDriver, PciInterrupt, PciInterruptRoute, PciMatch};
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use device::{PciBusDevice, PciDeviceInfo, PciDriver, PciMatch};
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use device_api::device::Device;
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use interrupt::PciInterruptMap;
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use libk::fs::sysfs::{self, object::KObject};
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use libk_mm::address::PhysicalAddress;
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use libk_util::{sync::IrqSafeSpinlock, OneTimeInit};
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@ -20,6 +22,7 @@ use yggdrasil_abi::error::Error;
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pub mod capability;
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pub mod device;
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pub mod interrupt;
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mod nodes;
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mod space;
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@ -202,7 +205,7 @@ pub struct PciSegmentInfo {
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pub bus_number_end: u8,
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pub ecam_phys_base: Option<PhysicalAddress>,
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pub irq_translation_map: BTreeMap<PciInterrupt, PciInterruptRoute>,
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pub irq_translation_map: PciInterruptMap,
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pub has_msi: bool,
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}
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@ -462,7 +465,7 @@ impl PciBusManager {
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bus_number_start: 0,
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bus_number_end: 255,
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ecam_phys_base: None,
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irq_translation_map: BTreeMap::new(),
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irq_translation_map: PciInterruptMap::Legacy,
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has_msi: false,
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}),
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allocator: None,
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@ -486,8 +489,8 @@ impl PciBusManager {
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bus_number_end: entry.bus_number_end,
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ecam_phys_base: Some(PhysicalAddress::from_u64(entry.base_address)),
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// TODO obtain this from ACPI SSDT
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irq_translation_map: BTreeMap::new(),
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// TODO get the segment's PCI root bridge AML name
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irq_translation_map: PciInterruptMap::Acpi("\\_SB.PCI0._PRT".into()),
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has_msi: true,
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}),
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// Firmware done this for us
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@ -11,7 +11,7 @@ use libk_mm::{
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};
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use libk_util::sync::IrqSafeSpinlock;
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use crate::arch::x86::intrinsics::{io_wait, IoPort, IoPortAccess};
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use kernel_arch_x86::intrinsics::{io_wait, IoPort, IoPortAccess};
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#[derive(Clone, Copy)]
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#[repr(C)]
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@ -83,7 +83,7 @@ impl Regs {
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impl Inner {
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fn map_gsi(&mut self, gsi: u32, vector: u32, apic_id: u32) -> Result<(), Error> {
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assert!(gsi < self.max_gsi);
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assert!(gsi <= self.max_gsi);
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assert!(vector < 0x100);
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log::info!("map_irq gsi{}, vec{}, apic{}", gsi, vector, apic_id);
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@ -110,7 +110,7 @@ impl Inner {
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}
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fn configure_gsi(&mut self, gsi: u32, level: IrqLevel, trigger: IrqTrigger) {
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assert!(gsi < self.max_gsi);
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assert!(gsi <= self.max_gsi);
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let mut low = self.regs.read(REG_REDIRECTION_BASE + gsi * 2);
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@ -138,7 +138,7 @@ impl Inner {
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}
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fn set_gsi_enabled(&mut self, gsi: u32, enabled: bool) {
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assert!(gsi < self.max_gsi);
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assert!(gsi <= self.max_gsi);
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let low = self.regs.read(REG_REDIRECTION_BASE + gsi * 2);
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if enabled {
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