dwmac: print Tx error statuses
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93ab72d4a0
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fbd963d26c
@ -150,7 +150,6 @@ impl Device for Stmmac {
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// TODO get these params from device tree
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regs.DMA.DMASBMR.write(
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DMASBMR::FB::SET
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+ DMASBMR::AAL::SET
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+ DMASBMR::BLEN256::SET
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+ DMASBMR::BLEN128::SET
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+ DMASBMR::BLEN64::SET
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@ -177,13 +176,13 @@ impl Device for Stmmac {
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.set(rx_ring_base + (rx_ring_capacity * size_of::<RxDescriptor>()) as u32);
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// Setup DMA maximum segmen size, Rx buffer size + max burst len
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regs.DMA.DMAC0CR.write(DMACiCR::PBLX8::CLEAR);
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regs.DMA
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.DMAC0CR
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.write(DMACiCR::PBLX8::CLEAR + DMACiCR::MSS.val(1024));
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regs.DMA.DMAC0TXCR.write(DMACiTXCR::TXPBL.val(256));
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.DMAC0TXCR
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.write(DMACiTXCR::TXPBL.val(32) + DMACiTXCR::OSF::SET);
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regs.DMA
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.DMAC0RXCR
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.write(DMAC0RXCR::RBSZ.val(4096) + DMAC0RXCR::RXPBL.val(256));
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.write(DMAC0RXCR::RBSZ.val(4096) + DMAC0RXCR::RXPBL.val(32));
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// Enable DMA interrupts
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// TODO enable abnormal interrupts to handle errors properly
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@ -208,9 +207,9 @@ impl Device for Stmmac {
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// TODO get TQS, RQS from device tree
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regs.MTL
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.MTLTXQ0OMR
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.write(MTLTXQiOMR::TSF::SET + MTLTXQiOMR::TQS.val(1) + MTLTXQiOMR::TXQEN::Enable);
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.write(MTLTXQiOMR::TSF::SET + MTLTXQiOMR::TQS.val(7) + MTLTXQiOMR::TXQEN::Enable);
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regs.MTL.MTLRXQ0OMR.write(
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MTLRXQiOMR::RQS.val(1)
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MTLRXQiOMR::RQS.val(7)
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+ MTLRXQiOMR::DIS_TCP_EF::SET
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+ MTLRXQiOMR::RSF::SET
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+ MTLRXQiOMR::FEP::SET
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@ -249,7 +248,7 @@ impl Device for Stmmac {
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// Setup link information
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regs.MAC
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.MACCR
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.modify(MACCR::PS::Ps1000Mbps + MACCR::FES::Fes100Mbps + MACCR::DM::FullDuplex);
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.modify(MACCR::PS::Ps1000Mbps + MACCR::DM::FullDuplex);
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// Start Tx/Rx
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regs.MAC.MACCR.modify(MACCR::TE::SET + MACCR::RE::SET);
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@ -1,7 +1,7 @@
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use core::mem;
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use alloc::vec::Vec;
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use libk::error::Error;
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use libk::{debug, error::Error};
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use libk_mm::{
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address::{AsPhysicalAddress, PhysicalAddress},
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PageBox,
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@ -99,8 +99,10 @@ impl TxRing {
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break;
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}
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if entry.tx_completed() {
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// Drop the buffer
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if let Some(status) = entry.tx_status() {
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if status != 0 {
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log::warn!("tx_ring[{index}] error: {status:#x}");
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}
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let _ = self.buffers[index].take().unwrap();
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self.rd = self.rd.wrapping_add(1);
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count += 1;
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@ -128,8 +130,12 @@ impl TxDescriptor {
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}
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}
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pub fn tx_completed(&self) -> bool {
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self.tdes3 & Self::TDES3_OWN == 0
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pub fn tx_status(&self) -> Option<u32> {
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if self.tdes3 & Self::TDES3_OWN == 0 {
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Some(self.tdes3 & !(0xFFFF << 16))
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} else {
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None
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}
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}
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pub fn setup_tx(
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