684 lines
21 KiB
Rust
684 lines
21 KiB
Rust
//! PCI/PCIe bus interfaces
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#![no_std]
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#![allow(clippy::missing_transmute_annotations)]
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extern crate alloc;
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use core::fmt;
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#[cfg(target_arch = "x86_64")]
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use acpi::mcfg::McfgEntry;
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use alloc::{collections::BTreeMap, format, sync::Arc, vec::Vec};
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use bitflags::bitflags;
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use device::{PciBusDevice, PciDeviceInfo, PciDriver, PciInterrupt, PciInterruptRoute, PciMatch};
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use device_api::device::Device;
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use libk::fs::sysfs::{self, object::KObject};
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use libk_mm::address::PhysicalAddress;
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use libk_util::{sync::IrqSafeSpinlock, OneTimeInit};
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use space::legacy;
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use yggdrasil_abi::error::Error;
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pub mod capability;
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pub mod device;
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mod nodes;
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mod space;
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pub use space::{
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ecam::PciEcam,
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legacy::{LegacyPciAccess, PciLegacyConfigurationSpace},
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PciConfigSpace, PciConfigurationSpace,
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};
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bitflags! {
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/// Command register of the PCI configuration space
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pub struct PciCommandRegister: u16 {
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/// If set, I/O access to the device is enabled
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const ENABLE_IO = 1 << 0;
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/// If set, memory-mapped access to the device is enabled
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const ENABLE_MEMORY = 1 << 1;
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/// If set, the device can generate PCI bus accesses on its own
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const BUS_MASTER = 1 << 2;
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/// If set, interrupts are masked from being raised
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const DISABLE_INTERRUPTS = 1 << 10;
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}
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}
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bitflags! {
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/// Status register of the PCI configuration space
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pub struct PciStatusRegister: u16 {
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/// Read-only. If set, the configuration space has a pointer to the capabilities list.
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const CAPABILITIES_LIST = 1 << 4;
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}
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}
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/// Represents the address of a single object on a bus (or the bus itself)
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#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug)]
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pub struct PciAddress {
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/// PCIe segment group, ignored (?) with PCI
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pub segment: u8,
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/// Bus number
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pub bus: u8,
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/// Slot/device number
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pub device: u8,
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/// Function number
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pub function: u8,
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}
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/// Address provided by PCI configuration space Base Address Register
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#[derive(Debug, Clone, Copy)]
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pub enum PciBaseAddress {
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/// 32-bit memory address
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Memory32(u32),
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/// 64-bit memory address
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Memory64(u64),
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/// I/O space address
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Io(u16),
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}
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/// Unique ID assigned to PCI capability structures
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#[derive(Clone, Copy, PartialEq, Eq, Debug)]
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#[non_exhaustive]
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#[repr(u8)]
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pub enum PciCapabilityId {
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/// MSI (32-bit or 64-bit)
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Msi = 0x05,
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/// Vendor-specific capability
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VendorSpecific = 0x09,
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/// MSI-X
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MsiX = 0x11,
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/// Unknown capability missing from this list
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Unknown,
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}
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/// Interface used for querying PCI capabilities
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#[allow(unused)]
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pub trait PciCapability {
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/// Capability ID
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const ID: PciCapabilityId;
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/// Wrapper for accessing the capability data structure
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type CapabilityData<'a, S: PciConfigurationSpace + ?Sized + 'a>;
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fn check<S: PciConfigurationSpace + ?Sized>(space: &S, offset: usize, len: usize) -> bool {
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true
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}
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/// Constructs an access wrapper for this capability with given offset
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fn data<'s, S: PciConfigurationSpace + ?Sized + 's>(
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space: &'s S,
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offset: usize,
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len: usize,
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) -> Self::CapabilityData<'s, S>;
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}
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struct BusAddressAllocator {
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pci_base_64: u64,
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pci_base_32: u32,
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// pci_base_io: u16,
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host_base_64: PhysicalAddress,
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host_base_32: PhysicalAddress,
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// host_base_io: PhysicalAddress,
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size_64: usize,
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size_32: usize,
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// size_io: usize,
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offset_64: u64,
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offset_32: u32,
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}
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#[cfg_attr(
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any(target_arch = "x86_64", target_arch = "x86", target_arch = "riscv64"),
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allow(dead_code)
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)]
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impl BusAddressAllocator {
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pub fn from_ranges(ranges: &[PciAddressRange]) -> Self {
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let mut range_32 = None;
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let mut range_64 = None;
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// let mut range_io = None;
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for range in ranges {
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let range_val = (range.pci_base, range.host_base, range.size);
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match range.ty {
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// PciRangeType::Io if range_io.is_none() => {
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// range_io.replace(range_val);
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// }
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PciRangeType::Memory32 if range_32.is_none() => {
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range_32.replace(range_val);
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}
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PciRangeType::Memory64 if range_64.is_none() => {
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range_64.replace(range_val);
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}
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_ => (),
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}
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}
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let (pci_base_32, host_base_32, size_32) = range_32.unwrap();
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let (pci_base_64, host_base_64, size_64) = range_64.unwrap();
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// let (pci_base_io, host_base_io, size_io) = range_io.unwrap();
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Self {
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pci_base_64,
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pci_base_32: pci_base_32.try_into().unwrap(),
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// pci_base_io: pci_base_io.try_into().unwrap(),
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host_base_64,
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host_base_32,
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// host_base_io,
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size_64,
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size_32,
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// size_io,
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offset_64: 0,
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offset_32: 0,
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}
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}
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pub fn allocate(&mut self, ty: PciRangeType, size: usize) -> (PciBaseAddress, PhysicalAddress) {
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match ty {
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PciRangeType::Io => todo!(),
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PciRangeType::Memory32 => {
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if self.offset_32 as usize + size >= self.size_32 {
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todo!();
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}
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let bar = PciBaseAddress::Memory32(self.pci_base_32 + self.offset_32);
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let host = self.host_base_32.add(self.offset_32 as usize);
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self.offset_32 += size as u32;
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(bar, host)
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}
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PciRangeType::Memory64 => {
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if self.offset_64 as usize + size >= self.size_64 {
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todo!();
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}
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let bar = PciBaseAddress::Memory64(self.pci_base_64 + self.offset_64);
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let host = self.host_base_64.add(self.offset_64 as usize);
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self.offset_64 += size as u64;
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(bar, host)
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}
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PciRangeType::Configuration => unimplemented!(),
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}
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}
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}
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#[derive(Debug)]
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pub struct PciSegmentInfo {
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pub segment_number: u8,
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pub bus_number_start: u8,
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pub bus_number_end: u8,
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pub ecam_phys_base: Option<PhysicalAddress>,
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pub irq_translation_map: BTreeMap<PciInterrupt, PciInterruptRoute>,
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pub has_msi: bool,
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}
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/// Represents a single PCIe bus segment
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pub struct PciBusSegment {
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allocator: Option<BusAddressAllocator>,
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info: Arc<PciSegmentInfo>,
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devices: Vec<Arc<KObject<IrqSafeSpinlock<PciBusDevice>>>>,
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}
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#[derive(Debug)]
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pub enum PciRangeType {
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Configuration,
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Io,
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Memory32,
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Memory64,
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}
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pub struct PciAddressRange {
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pub ty: PciRangeType,
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pub bus_number: u8,
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pub pci_base: u64,
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pub host_base: PhysicalAddress,
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pub size: usize,
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}
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/// Manager struct to store and control all PCI devices in the system
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pub struct PciBusManager {
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segments: Vec<PciBusSegment>,
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}
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impl PciBaseAddress {
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pub fn as_memory(self) -> Option<PhysicalAddress> {
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match self {
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Self::Memory32(address) => Some(PhysicalAddress::from_u64(address as u64)),
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Self::Memory64(address) => Some(PhysicalAddress::from_u64(address)),
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_ => None,
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}
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}
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pub fn is_zero(&self) -> bool {
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match *self {
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Self::Memory32(base) => base == 0,
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Self::Memory64(base) => base == 0,
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Self::Io(base) => base == 0,
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}
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}
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}
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impl PciBusSegment {
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fn probe_config_space(&self, address: PciAddress) -> Result<Option<PciConfigSpace>, Error> {
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match self.info.ecam_phys_base {
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Some(ecam_phys_base) => Ok(unsafe {
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PciEcam::probe_raw_parts(ecam_phys_base, self.info.bus_number_start, address)?
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}
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.map(PciConfigSpace::Ecam)),
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None => Ok(PciLegacyConfigurationSpace::probe(address)?.map(PciConfigSpace::Legacy)),
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}
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}
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fn enumerate_function(&mut self, address: PciAddress) -> Result<(), Error> {
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let Some(config) = self.probe_config_space(address)? else {
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return Ok(());
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};
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let header_type = config.header_type();
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// Enumerate multi-function devices
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if address.function == 0 && header_type & 0x80 != 0 {
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for function in 1..8 {
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self.enumerate_function(address.with_function(function))?;
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}
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}
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// PCI-to-PCI bridge
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// if config.class_code() == 0x06 && config.subclass() == 0x04 {
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// let secondary_bus = config.secondary_bus();
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// // TODO
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// }
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if let Some(allocator) = self.allocator.as_mut() {
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log::debug!("Remapping BARs for {}", address);
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// Find valid BARs
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let mut i = 0;
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let mut bar_mask = 0;
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while i < 6 {
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let w0 = config.read_u32(0x10 + i * 4);
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let bar_width = match w0 & 1 == 0 {
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// Memory BAR
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true => match (w0 >> 1) & 3 {
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// 32-bit BAR
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0 => 1,
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// Reserved
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1 => unimplemented!(),
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// 64-bit BAR
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2 => 2,
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// Unknown
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_ => unreachable!(),
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},
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false => 1,
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};
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bar_mask |= 1 << i;
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i += bar_width;
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}
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for i in 0..6 {
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if (1 << i) & bar_mask != 0 {
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let orig_value = config.bar(i).unwrap();
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let size = unsafe { config.bar_size(i) };
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if size != 0 {
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log::debug!("BAR{}: size={:#x}", i, size);
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match orig_value {
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PciBaseAddress::Io(_) => (),
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PciBaseAddress::Memory64(_) => {
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let (bar, host) = allocator.allocate(PciRangeType::Memory64, size);
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let bar_address = bar.as_memory().unwrap();
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unsafe {
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config.set_bar(i, bar);
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}
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log::debug!(
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"Mapped BAR{} -> pci {:#x} host {:#x}",
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i,
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bar_address,
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host
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);
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// TODO Don't yet differentiate between Host/PCI addresses, lol
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assert_eq!(bar_address, host);
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}
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PciBaseAddress::Memory32(_) => {
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let (bar, host) = allocator.allocate(PciRangeType::Memory32, size);
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let bar_address = bar.as_memory().unwrap();
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unsafe {
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config.set_bar(i, bar);
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}
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log::debug!(
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"Mapped BAR{} -> pci {:#x} host {:#x}",
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i,
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bar_address,
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host
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);
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// TODO Don't yet differentiate between Host/PCI addresses, lol
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assert_eq!(bar_address, host);
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}
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}
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}
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}
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}
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}
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let vendor_id = config.vendor_id();
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let device_id = config.device_id();
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let class = config.class_code();
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let subclass = config.subclass();
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let prog_if = config.prog_if();
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let info = PciDeviceInfo {
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address,
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vendor_id,
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device_id,
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class,
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subclass,
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prog_if,
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segment: self.info.clone(),
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config_space: config,
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interrupt_config: Arc::new(OneTimeInit::new()),
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};
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let object = nodes::make_sysfs_object(PciBusDevice {
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info,
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driver_name: None,
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device: None,
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});
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let pci_object = PCI_SYSFS_NODE.or_init_with(|| {
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let bus_object = sysfs::bus().unwrap();
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let pci_object = KObject::new(());
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bus_object.add_object("pci", pci_object.clone()).ok();
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pci_object
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});
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let name = format!("{address}");
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pci_object.add_object(name, object.clone()).ok();
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self.devices.push(object);
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Ok(())
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}
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fn enumerate_bus(&mut self, bus: u8) -> Result<(), Error> {
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let address = PciAddress::for_bus(self.info.segment_number, bus);
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for i in 0..32 {
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let device_address = address.with_device(i);
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self.enumerate_function(device_address)?;
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}
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Ok(())
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}
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/// Enumerates the bus segment, placing found devices into the manager
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pub fn enumerate(&mut self) -> Result<(), Error> {
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for bus in self.info.bus_number_start..self.info.bus_number_end {
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self.enumerate_bus(bus)?;
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}
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Ok(())
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}
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}
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impl PciBusManager {
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const fn new() -> Self {
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Self {
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segments: Vec::new(),
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}
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}
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/// Walks the bus device list and calls init/init_irq functions on any devices with associated
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/// drivers
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pub fn setup_bus_devices() -> Result<(), Error> {
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log::info!("Setting up bus devices");
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Self::walk_bus_devices(|device| {
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log::info!("Set up {}", device.info.address);
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setup_bus_device(device)?;
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Ok(true)
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})
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}
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/// Iterates over the bus devices, calling the function on each of them until either an error
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/// or `Ok(false)` is returned
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pub fn walk_bus_devices<F: FnMut(&mut PciBusDevice) -> Result<bool, Error>>(
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mut f: F,
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) -> Result<(), Error> {
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let mut this = PCI_MANAGER.lock();
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for segment in this.segments.iter_mut() {
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for device in segment.devices.iter_mut() {
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let mut device = device.lock();
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if !f(&mut *device)? {
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return Ok(());
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}
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}
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}
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Ok(())
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}
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pub fn add_legacy_segment(access: &'static dyn LegacyPciAccess) -> Result<(), Error> {
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legacy::PCI.init(access);
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let mut bus_segment = PciBusSegment {
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info: Arc::new(PciSegmentInfo {
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segment_number: 0,
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bus_number_start: 0,
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bus_number_end: 255,
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ecam_phys_base: None,
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irq_translation_map: BTreeMap::new(),
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has_msi: false,
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}),
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allocator: None,
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devices: Vec::new(),
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};
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let mut this = PCI_MANAGER.lock();
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bus_segment.enumerate()?;
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this.segments.push(bus_segment);
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Ok(())
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}
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/// Enumerates a bus segment provided by ACPI MCFG table entry
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#[cfg(target_arch = "x86_64")]
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pub fn add_segment_from_mcfg(entry: &McfgEntry) -> Result<(), Error> {
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let mut bus_segment = PciBusSegment {
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info: Arc::new(PciSegmentInfo {
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segment_number: entry.pci_segment_group as u8,
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bus_number_start: entry.bus_number_start,
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bus_number_end: entry.bus_number_end,
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ecam_phys_base: Some(PhysicalAddress::from_u64(entry.base_address)),
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// TODO obtain this from ACPI SSDT
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irq_translation_map: BTreeMap::new(),
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has_msi: true,
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}),
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// Firmware done this for us
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allocator: None,
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devices: Vec::new(),
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};
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let mut this = PCI_MANAGER.lock();
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bus_segment.enumerate()?;
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this.segments.push(bus_segment);
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Ok(())
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}
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#[cfg(any(target_arch = "aarch64", target_arch = "riscv64", rust_analyzer))]
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pub fn add_segment_from_device_tree(
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cfg_base: PhysicalAddress,
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bus_range: core::ops::Range<u8>,
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ranges: Vec<PciAddressRange>,
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interrupt_map: BTreeMap<PciInterrupt, PciInterruptRoute>,
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) -> Result<(), Error> {
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let mut bus_segment = PciBusSegment {
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info: Arc::new(PciSegmentInfo {
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segment_number: 0,
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bus_number_start: bus_range.start,
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bus_number_end: bus_range.end,
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ecam_phys_base: Some(cfg_base),
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irq_translation_map: interrupt_map,
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has_msi: false,
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}),
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allocator: Some(BusAddressAllocator::from_ranges(&ranges)),
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devices: Vec::new(),
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};
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let mut this = PCI_MANAGER.lock();
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bus_segment.enumerate()?;
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this.segments.push(bus_segment);
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Ok(())
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}
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}
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impl fmt::Display for PciAddress {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
|
write!(f, "{}:{}:{}", self.bus, self.device, self.function)
|
|
}
|
|
}
|
|
|
|
impl PciAddress {
|
|
/// Constructs a [PciAddress] representing a bus
|
|
pub const fn for_bus(segment: u8, bus: u8) -> Self {
|
|
Self {
|
|
segment,
|
|
bus,
|
|
device: 0,
|
|
function: 0,
|
|
}
|
|
}
|
|
|
|
/// Constructs a [PciAddress] representing a specific function
|
|
pub const fn for_function(segment: u8, bus: u8, device: u8, function: u8) -> Self {
|
|
Self {
|
|
segment,
|
|
bus,
|
|
device,
|
|
function,
|
|
}
|
|
}
|
|
|
|
/// Constructs a [PciAddress] representing a device on a given bus
|
|
pub const fn with_device(self, device: u8) -> Self {
|
|
Self {
|
|
device,
|
|
function: 0,
|
|
..self
|
|
}
|
|
}
|
|
|
|
/// Constructs a [PciAddress] representing a function of a given bus device
|
|
pub const fn with_function(self, function: u8) -> Self {
|
|
Self { function, ..self }
|
|
}
|
|
}
|
|
|
|
impl PciConfigurationSpace for PciConfigSpace {
|
|
fn read_u32(&self, offset: usize) -> u32 {
|
|
match self {
|
|
Self::Ecam(ecam) => ecam.read_u32(offset),
|
|
Self::Legacy(legacy) => legacy.read_u32(offset),
|
|
}
|
|
}
|
|
|
|
fn write_u32(&self, offset: usize, value: u32) {
|
|
match self {
|
|
Self::Ecam(ecam) => ecam.write_u32(offset, value),
|
|
Self::Legacy(legacy) => legacy.write_u32(offset, value),
|
|
}
|
|
}
|
|
}
|
|
|
|
fn setup_bus_device(device: &mut PciBusDevice) -> Result<(), Error> {
|
|
if device.device.is_some() {
|
|
return Ok(());
|
|
}
|
|
|
|
log::debug!(
|
|
"{}: {:04x}:{:04x}",
|
|
device.info.address,
|
|
device.info.vendor_id,
|
|
device.info.device_id
|
|
);
|
|
|
|
let drivers = PCI_DRIVERS.lock();
|
|
for driver in drivers.iter() {
|
|
if driver.check.check_device(&device.info) {
|
|
// TODO add the device to the bus
|
|
log::debug!(" -> {:?}", driver.name);
|
|
let instance = (driver.probe)(&device.info)?;
|
|
|
|
unsafe { instance.clone().init() }?;
|
|
|
|
device.device.replace(instance);
|
|
device.driver_name.replace(driver.name);
|
|
break;
|
|
}
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
|
|
impl PciMatch {
|
|
pub fn check_device(&self, info: &PciDeviceInfo) -> bool {
|
|
match self {
|
|
Self::Generic(f) => f(info),
|
|
&Self::Vendor(vendor_, device_) => {
|
|
info.vendor_id == vendor_ && info.device_id == device_
|
|
}
|
|
&Self::Class(class_, Some(subclass_), Some(prog_if_)) => {
|
|
class_ == info.class && subclass_ == info.subclass && prog_if_ == info.prog_if
|
|
}
|
|
&Self::Class(class_, Some(subclass_), _) => {
|
|
class_ == info.class && subclass_ == info.subclass
|
|
}
|
|
&Self::Class(class_, _, _) => class_ == info.class,
|
|
}
|
|
}
|
|
}
|
|
|
|
pub fn register_class_driver(
|
|
name: &'static str,
|
|
class: u8,
|
|
subclass: Option<u8>,
|
|
prog_if: Option<u8>,
|
|
probe: fn(&PciDeviceInfo) -> Result<Arc<dyn Device>, Error>,
|
|
) {
|
|
PCI_DRIVERS.lock().push(PciDriver {
|
|
name,
|
|
check: PciMatch::Class(class, subclass, prog_if),
|
|
probe,
|
|
});
|
|
}
|
|
|
|
pub fn register_vendor_driver(
|
|
name: &'static str,
|
|
vendor_id: u16,
|
|
device_id: u16,
|
|
probe: fn(&PciDeviceInfo) -> Result<Arc<dyn Device>, Error>,
|
|
) {
|
|
PCI_DRIVERS.lock().push(PciDriver {
|
|
name,
|
|
check: PciMatch::Vendor(vendor_id, device_id),
|
|
probe,
|
|
});
|
|
}
|
|
|
|
pub fn register_generic_driver(
|
|
name: &'static str,
|
|
check: fn(&PciDeviceInfo) -> bool,
|
|
probe: fn(&PciDeviceInfo) -> Result<Arc<dyn Device>, Error>,
|
|
) {
|
|
PCI_DRIVERS.lock().push(PciDriver {
|
|
name,
|
|
check: PciMatch::Generic(check),
|
|
probe,
|
|
});
|
|
}
|
|
|
|
static PCI_DRIVERS: IrqSafeSpinlock<Vec<PciDriver>> = IrqSafeSpinlock::new(Vec::new());
|
|
static PCI_MANAGER: IrqSafeSpinlock<PciBusManager> = IrqSafeSpinlock::new(PciBusManager::new());
|
|
static PCI_SYSFS_NODE: OneTimeInit<Arc<KObject<()>>> = OneTimeInit::new();
|