141 lines
2.9 KiB
ArmAsm
141 lines
2.9 KiB
ArmAsm
// vi:ft=a64asm:
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.macro EXC_VECTOR el, ht, bits, kind
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.p2align 7
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b __aa\bits\()_el\el\ht\()_\kind
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.endm
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.macro EXC_HANDLER el, ht, bits, kind
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__aa\bits\()_el\el\ht\()_\kind:
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.if \bits == 32
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// TODO 32-bit support
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b .
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.endif
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EXC_SAVE_STATE
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mov x0, sp
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mov lr, xzr
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bl __aa64_el\el\()_\kind\()_handler
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EXC_RESTORE_STATE
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eret
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.endm
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// 32 gp regs + 3 special regs
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.set PT_REGS_SIZE, (16 * 16 + 16 * 2)
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.macro EXC_SAVE_STATE
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isb sy
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sub sp, sp, #PT_REGS_SIZE
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stp x0, x1, [sp, #16 * 0]
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stp x2, x3, [sp, #16 * 1]
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stp x4, x5, [sp, #16 * 2]
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stp x6, x7, [sp, #16 * 3]
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stp x8, x9, [sp, #16 * 4]
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stp x10, x11, [sp, #16 * 5]
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stp x12, x13, [sp, #16 * 6]
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stp x14, x15, [sp, #16 * 7]
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stp x16, x17, [sp, #16 * 8]
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stp x18, x19, [sp, #16 * 9]
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stp x20, x21, [sp, #16 * 10]
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stp x22, x23, [sp, #16 * 11]
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stp x24, x25, [sp, #16 * 12]
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stp x26, x27, [sp, #16 * 13]
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stp x28, x29, [sp, #16 * 14]
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stp x30, x31, [sp, #16 * 15]
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mrs x0, spsr_el1
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mrs x1, elr_el1
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mrs x2, sp_el0
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mrs x3, mdscr_el1
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stp x0, x1, [sp, #16 * 16]
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stp x2, x3, [sp, #16 * 17]
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dsb ish
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isb sy
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.endm
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.macro EXC_RESTORE_STATE
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dsb ishst
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ldp x0, x1, [sp, #16 * 16]
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ldp x2, x3, [sp, #16 * 17]
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msr spsr_el1, x0
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msr elr_el1, x1
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msr sp_el0, x2
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msr mdscr_el1, x3
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ldp x0, x1, [sp, #16 * 0]
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ldp x2, x3, [sp, #16 * 1]
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ldp x4, x5, [sp, #16 * 2]
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ldp x6, x7, [sp, #16 * 3]
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ldp x8, x9, [sp, #16 * 4]
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ldp x10, x11, [sp, #16 * 5]
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ldp x12, x13, [sp, #16 * 6]
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ldp x14, x15, [sp, #16 * 7]
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ldp x16, x17, [sp, #16 * 8]
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ldp x18, x19, [sp, #16 * 9]
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ldp x20, x21, [sp, #16 * 10]
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ldp x22, x23, [sp, #16 * 11]
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ldp x24, x25, [sp, #16 * 12]
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ldp x26, x27, [sp, #16 * 13]
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ldp x28, x29, [sp, #16 * 14]
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ldp x30, x31, [sp, #16 * 15]
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add sp, sp, #PT_REGS_SIZE
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ic iallu
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isb sy
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.endm
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.section .text.vectors
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.global __aarch64_el1_vectors
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.p2align 12
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__aarch64_el1_vectors:
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EXC_VECTOR 1, t, 64, sync
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EXC_VECTOR 1, t, 64, irq
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EXC_VECTOR 1, t, 64, fiq
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EXC_VECTOR 1, t, 64, serror
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EXC_VECTOR 1, h, 64, sync
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EXC_VECTOR 1, h, 64, irq
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EXC_VECTOR 1, h, 64, fiq
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EXC_VECTOR 1, h, 64, serror
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EXC_VECTOR 0, t, 64, sync
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EXC_VECTOR 0, t, 64, irq
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EXC_VECTOR 0, t, 64, fiq
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EXC_VECTOR 0, t, 64, serror
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EXC_VECTOR 0, t, 32, sync
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EXC_VECTOR 0, t, 32, irq
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EXC_VECTOR 0, t, 32, fiq
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EXC_VECTOR 0, t, 32, serror
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.section .text
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.p2align 7
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EXC_HANDLER 1, t, 64, sync
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EXC_HANDLER 1, t, 64, irq
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EXC_HANDLER 1, t, 64, fiq
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EXC_HANDLER 1, t, 64, serror
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EXC_HANDLER 1, h, 64, sync
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EXC_HANDLER 1, h, 64, irq
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EXC_HANDLER 1, h, 64, fiq
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EXC_HANDLER 1, h, 64, serror
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EXC_HANDLER 0, t, 64, sync
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EXC_HANDLER 0, t, 64, irq
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EXC_HANDLER 0, t, 64, fiq
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EXC_HANDLER 0, t, 64, serror
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EXC_HANDLER 0, t, 32, sync
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EXC_HANDLER 0, t, 32, irq
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EXC_HANDLER 0, t, 32, fiq
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EXC_HANDLER 0, t, 32, serror
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