Make arch/riscv64.zig one struct

src/arch.zig

@@ -3,7 +3,7 @@ pub fn arch() type {
 
     switch (comptime builtin.cpu.arch) {
         .riscv64 => {
-            return @import("arch/riscv64.zig").arch();
+            return @import("arch/riscv64.zig");
         },
         else => {
             @panic("Architecture is not supported");

src/arch/riscv64.zig

@@ -8,16 +8,14 @@ const Arena = @import("../arena.zig").Arena;
 
 export const _ = boot.rv64BspLowerEntry;
 
-extern fn __rv64_enter_task(cx: *arch().Context) callconv(.C) noreturn;
-extern fn __rv64_switch_task(dcx: *arch().Context, scx: *arch().Context) callconv(.C) void;
+extern fn __rv64_enter_task(cx: *Context) callconv(.C) noreturn;
+extern fn __rv64_switch_task(dcx: *Context, scx: *Context) callconv(.C) void;
 extern fn __rv64_task_enter_kernel() callconv(.C) noreturn;
 
 fn idleFunction() callconv(.naked) noreturn {
     asm volatile ("j .");
 }
 
-pub fn arch() type {
-    return struct {
 pub threadlocal var tHartId: u32 = 0;
 
 pub const Context = extern struct {
@@ -53,9 +51,7 @@ pub fn arch() type {
         ks.push(0); // x4/gp
         ks.push(entry); // x1/ra return address
 
-                return .{
-                    .kstack = ks
-                };
+        return .{ .kstack = ks };
     }
 
     pub fn enter(self: *@This()) noreturn {
@@ -114,7 +110,9 @@ pub fn arch() type {
 }
 
 pub inline fn setThreadPointer(tp: usize) void {
-            asm volatile ("mv tp, %[tp]"::[tp]"r"(tp):"memory");
-        }
-    };
+    asm volatile ("mv tp, %[tp]"
+        :
+        : [tp] "r" (tp),
+        : "memory"
+    );
 }