WIP: WIP, WIP

src/arch/riscv64.zig

@@ -1,4 +1,7 @@
 const boot = @import("riscv64/boot.zig");
+const regs = @import("riscv64/regs.zig");
+const std = @import("std");
+const builtin = @import("builtin");
 export const _ = boot.rv64BspLowerEntry;
 
 pub fn arch() type {
@@ -6,18 +9,47 @@ pub fn arch() type {
         pub inline fn halt() noreturn {
             while (true) {
                 _ = setInterruptMask(true);
-                pause();
+                waitForInterrupt();
             }
         }
 
         pub inline fn setInterruptMask(mask: bool) bool {
-            // TODO
-            _ = mask;
-            return true;
+            const old = interruptMask();
+            if (mask) {
+                regs.SSTATUS.modify(.{}, .{ .SIE = true });
+            } else {
+                regs.SSTATUS.modify(.{ .SIE = true }, .{});
+            }
+            return old;
         }
 
-        pub inline fn pause() void {
+        pub fn interruptMask() bool {
+            return regs.SSTATUS.read().SIE;
+        }
+
+        pub inline fn waitForInterrupt() void {
             asm volatile ("wfi");
         }
+
+        pub inline fn spinHint() void {
+            // Don't want to explicitly enable Zihintpause ext, so just paste this as raw opcode
+            asm volatile (".word 0x0100000f");
+        }
+
+        pub inline fn barrier(comptime ordering: std.builtin.AtomicOrder) void {
+            switch (ordering) {
+                .acquire => {
+                    asm volatile ("fence rw, w");
+                },
+                .release => {
+                    asm volatile ("fence w, rw");
+                },
+                .acq_rel, .seq_cst => {
+                    asm volatile ("fence rw, rw");
+                },
+                .unordered, .monotonic => {},
+            }
+            asm volatile ("":::"memory");
+        }
     };
 }