diff --git a/src/arch.zig b/src/arch.zig
index f495a23..5778ba2 100644
--- a/src/arch.zig
+++ b/src/arch.zig
@@ -1,6 +1,7 @@
 //! Helper module to select architecture-specific modules depending on what platform is
 //! being targeted.
 
+const std = @import("std");
 const builtin = @import("builtin");
 
 const impl = switch (builtin.cpu.arch) {
@@ -9,4 +10,41 @@ const impl = switch (builtin.cpu.arch) {
     else => @compileError("Unsupported architecture"),
 };
 
-pub usingnamespace impl;
+/// Halts the CPU execution indefinitely, without ever returning.
+pub inline fn halt() noreturn {
+    impl.halt();
+}
+
+/// Returns the current state of IRQ masking.
+pub inline fn interruptMask() bool {
+    return impl.interruptMask();
+}
+
+/// Modifies the interrupt mask to either allow or block IRQs from being delivered to the CPU.
+/// Returns the old IRQ mask.
+pub inline fn setInterruptMask(masked: bool) bool {
+    impl.setInterruptMask(masked);
+}
+
+/// Suspends the CPU until an interrupt is signalled.
+pub inline fn waitForInterrupt() void {
+    impl.waitForInterrupt();
+}
+
+/// Hint to the CPU that the code is executing a "busy-wait" or a "spin-wait" loop.
+pub inline fn spinHint() void {
+    impl.spinHint();
+}
+
+/// Set the CPU's thread pointer to some value.
+pub inline fn setThreadPointer(value: usize) void {
+    impl.setThreadPointer(value);
+}
+
+/// Combined memory/compiler fence to ensure specific ordering of instructions and memory accesses.
+pub inline fn barrier(ordering: std.builtin.AtomicOrder) void {
+    impl.barrier(ordering);
+}
+
+/// Platform-specific task context implementation
+pub const Context = impl.Context;
diff --git a/src/arch/riscv64.zig b/src/arch/riscv64.zig
index 6900aad..0535021 100644
--- a/src/arch/riscv64.zig
+++ b/src/arch/riscv64.zig
@@ -71,7 +71,6 @@ pub const Context = extern struct {
     }
 };
 
-/// Halts the CPU execution indefinitely, without ever returning.
 pub inline fn halt() noreturn {
     while (true) {
         _ = setInterruptMask(true);
@@ -79,8 +78,6 @@ pub inline fn halt() noreturn {
     }
 }
 
-/// Modifies the interrupt mask to either allow or block IRQs from being delivered to the CPU.
-/// Returns the old IRQ mask.
 pub inline fn setInterruptMask(mask: bool) bool {
     const old = interruptMask();
     if (mask) {
@@ -91,23 +88,19 @@ pub inline fn setInterruptMask(mask: bool) bool {
     return old;
 }
 
-/// Returns the current state of IRQ masking.
 pub fn interruptMask() bool {
     return regs.SSTATUS.read().SIE;
 }
 
-/// Suspends the CPU until an interrupt is signalled.
 pub inline fn waitForInterrupt() void {
     asm volatile ("wfi");
 }
 
-/// Hint to the CPU that the code is executing a "busy-wait" or a "spin-wait" loop.
 pub inline fn spinHint() void {
     // Don't want to explicitly enable Zihintpause ext, so just paste this as raw opcode
     asm volatile (".word 0x0100000f");
 }
 
-/// Combined memory/compiler fence to ensure specific ordering of instructions and memory accesses.
 pub inline fn barrier(comptime ordering: std.builtin.AtomicOrder) void {
     switch (ordering) {
         .acquire => {
@@ -124,7 +117,6 @@ pub inline fn barrier(comptime ordering: std.builtin.AtomicOrder) void {
     asm volatile ("" ::: "memory");
 }
 
-/// Set the CPU's thread pointer to some value.
 pub inline fn setThreadPointer(tp: usize) void {
     asm volatile ("mv tp, %[tp]"
         :