69 lines
1.6 KiB
Zig
69 lines
1.6 KiB
Zig
//! RISC-V 64-bit platform-specific implementations.
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const boot = @import("riscv64/boot.zig");
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const regs = @import("riscv64/regs.zig");
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const std = @import("std");
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const builtin = @import("builtin");
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export const _ = boot.rv64_bsp_lower_entry;
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/// This CPU's HART (HARdware Thread) ID.
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pub threadlocal var t_hart_id: u32 = 0;
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/// RISC-V task context
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pub const Context = @import("riscv64/context.zig").Context;
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pub inline fn halt() noreturn {
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while (true) {
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_ = set_interrupt_mask(true);
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wait_for_interrupt();
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}
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}
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pub inline fn set_interrupt_mask(mask: bool) bool {
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const old = interrupt_mask();
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if (mask) {
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regs.SSTATUS.modify(.{}, .{ .SIE = true });
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} else {
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regs.SSTATUS.modify(.{ .SIE = true }, .{});
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}
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return old;
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}
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pub fn interrupt_mask() bool {
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return regs.SSTATUS.read().SIE;
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}
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pub inline fn wait_for_interrupt() void {
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asm volatile ("wfi");
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}
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pub inline fn spin_hint() void {
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// Don't want to explicitly enable Zihintpause ext, so just paste this as raw opcode
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asm volatile (".word 0x0100000f");
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}
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pub inline fn barrier(comptime ordering: std.builtin.AtomicOrder) void {
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switch (ordering) {
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.acquire => {
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asm volatile ("fence rw, w");
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},
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.release => {
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asm volatile ("fence w, rw");
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},
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.acq_rel, .seq_cst => {
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asm volatile ("fence rw, rw");
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},
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.unordered, .monotonic => {},
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}
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asm volatile ("" ::: "memory");
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}
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pub inline fn set_thread_pointer(tp: usize) void {
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asm volatile ("mv tp, %[tp]"
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:
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: [tp] "r" (tp),
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: "memory"
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);
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}
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