From 043c4e7eff4cf01a5d31db7a834686e599fb072f Mon Sep 17 00:00:00 2001
From: Mark <alnyan@airmail.cc>
Date: Tue, 28 Jan 2020 12:22:17 +0200
Subject: [PATCH] Allow IRQs during early initialization

---
 include/sys/amd64/asm/asm_irq.h | 3 +++
 sys/amd64/hw/irq.c              | 4 +---
 sys/amd64/hw/irq0.S             | 4 ++--
 sys/amd64/kernel.c              | 6 +++++-
 sys/amd64/smp/smp.c             | 6 +-----
 5 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/include/sys/amd64/asm/asm_irq.h b/include/sys/amd64/asm/asm_irq.h
index 90b5b9a..b82d164 100644
--- a/include/sys/amd64/asm/asm_irq.h
+++ b/include/sys/amd64/asm/asm_irq.h
@@ -117,6 +117,7 @@ amd64_irq\n:
 .endm
 #else
 // Externs for C code
+extern void amd64_irq0_early();
 extern void amd64_irq0();
 extern void amd64_irq1();
 extern void amd64_irq2();
@@ -138,4 +139,6 @@ extern void amd64_irq15();
 extern void amd64_irq_ipi();
 extern void amd64_irq_ipi_panic();
 #endif
+
+extern void amd64_irq_msi0();
 #endif
diff --git a/sys/amd64/hw/irq.c b/sys/amd64/hw/irq.c
index 28b2895..6787a27 100644
--- a/sys/amd64/hw/irq.c
+++ b/sys/amd64/hw/irq.c
@@ -141,8 +141,6 @@ int irq_has_handler(uint8_t gsi) {
     return !!handler_list[0].func;
 }
 
-extern void amd64_irq_msi0();
-
 int irq_add_msi_handler(irq_handler_func_t handler, void *ctx, uint8_t *vector) {
     for (size_t i = 0; i < MSI_MAX_HANDLERS; ++i) {
         if (!msi_handlers[i].func) {
@@ -171,7 +169,7 @@ void amd64_msi_handle(uint64_t vector) {
 
 void irq_init(int cpu) {
     // Special entry
-    amd64_idt_set(cpu, 32, (uintptr_t) amd64_irq0, 0x08, IDT_FLG_P | IDT_FLG_R0 | IDT_FLG_INT32);
+    amd64_idt_set(cpu, 32, (uintptr_t) amd64_irq0_early, 0x08, IDT_FLG_P | IDT_FLG_R0 | IDT_FLG_INT32);
 
     amd64_idt_set(cpu, 33, (uintptr_t) amd64_irq1, 0x08, IDT_FLG_P | IDT_FLG_R0 | IDT_FLG_INT32);
     amd64_idt_set(cpu, 34, (uintptr_t) amd64_irq2, 0x08, IDT_FLG_P | IDT_FLG_R0 | IDT_FLG_INT32);
diff --git a/sys/amd64/hw/irq0.S b/sys/amd64/hw/irq0.S
index b6e436b..4098505 100644
--- a/sys/amd64/hw/irq0.S
+++ b/sys/amd64/hw/irq0.S
@@ -3,9 +3,9 @@
 .section .text
 .global amd64_irq0
 .global amd64_irq2_counting
-.global amd64_irq0_dummy
+.global amd64_irq0_early
 
-amd64_irq0_dummy:
+amd64_irq0_early:
     cli
     pushq %rax
     irq_eoi_lapic 0
diff --git a/sys/amd64/kernel.c b/sys/amd64/kernel.c
index 25e39a1..828ffee 100644
--- a/sys/amd64/kernel.c
+++ b/sys/amd64/kernel.c
@@ -1,6 +1,8 @@
 #include "sys/debug.h"
 #include "sys/amd64/loader/multiboot.h"
+#include "sys/amd64/asm/asm_irq.h"
 #include "sys/amd64/hw/gdt.h"
+#include "sys/amd64/cpu.h"
 #include "sys/amd64/hw/vesa.h"
 #include "sys/amd64/syscall.h"
 #include "sys/amd64/hw/idt.h"
@@ -57,7 +59,6 @@ void kernel_main(struct amd64_loader_data *data) {
     pseudo_init();
     ps2_register_device();
 
-
     amd64_acpi_init();
 #if defined(VESA_ENABLE)
     amd64_vesa_init(multiboot_info);
@@ -100,6 +101,9 @@ void kernel_main(struct amd64_loader_data *data) {
 
     amd64_syscall_init();
 
+    // Ready to enter multitasking, disable early timer handler
+    amd64_idt_set(get_cpu()->processor_id, 32, (uintptr_t) amd64_irq0, 0x08, IDT_FLG_P | IDT_FLG_R0 | IDT_FLG_INT32);
+
     while (1) {
         asm ("sti; hlt");
     }
diff --git a/sys/amd64/smp/smp.c b/sys/amd64/smp/smp.c
index 613d6d5..2262d10 100644
--- a/sys/amd64/smp/smp.c
+++ b/sys/amd64/smp/smp.c
@@ -59,11 +59,6 @@ static void amd64_ap_code_entry(void) {
     // Setup IDT for this AP
     amd64_idt_init(cpu->processor_id);
 
-    // Setup temporary timer IRQ redirection for the AP so we don't enter threading
-    // too early (when scheduler hasn't at least prepared idle tasks)
-    extern void amd64_irq0_dummy(void);
-    amd64_idt_set(cpu->processor_id, 32, (uintptr_t) amd64_irq0_dummy, 0x08, IDT_FLG_P | IDT_FLG_R0 | IDT_FLG_INT32);
-
     // Enable LAPIC.SVR.SoftwareEnable bit
     // And set spurious interrupt mapping to 0xFF
     LAPIC(LAPIC_REG_SVR) |= (1 << 8) | (0xFF);
@@ -82,6 +77,7 @@ static void amd64_ap_code_entry(void) {
         asm volatile ("sti; hlt; cli");
     } while (!sched_ready);
 
+    // Set a real irq0 to perform context switches
     amd64_idt_set(cpu->processor_id, 32, (uintptr_t) amd64_irq0, 0x08, IDT_FLG_P | IDT_FLG_R0 | IDT_FLG_INT32);
 
     while (1) {