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Get rid of old AHCI/IDE drivers

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This commit is contained in:
Mark
2020-01-22 15:38:56 +02:00
parent f648cd2b94
commit 28aa749956
9 changed files with 0 additions and 1290 deletions
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include/sys/amd64/hw/ide/ahci.h
-233
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@@ -1,233 +0,0 @@
#pragma once
#include "sys/types.h"
#define AHCI_PORT_SSTS_DET_OK 0x3
#define AHCI_PORT_SSTS_IPM_ACTIVE 0x1
#define AHCI_PORT_SIG_SATA 0x00000101
#define AHCI_PORT_SIG_SATAPI 0xEB140101
#define AHCI_PORT_IS_TFES (1 << 30)
#define AHCI_PORT_CMD_ST (1 << 0)
#define AHCI_PORT_CMD_FRE (1 << 4)
#define AHCI_PORT_CMD_FR (1 << 14)
#define AHCI_PORT_CMD_CR (1 << 15)
enum ahci_fis_type {
FIS_REG_H2D = 0x27,
FIS_REG_D2H = 0x34,
FIS_DMA_ACT = 0x39,
FIS_DMA_SETUP = 0x41,
FIS_DATA = 0x46,
FIS_BIST = 0x58,
FIS_PIO_SETUP = 0x5F,
FIS_DEV_BITS = 0xA1
};
struct ahci_registers {
// Generic host control
uint32_t cap; // 0x00
uint32_t ghc; // 0x04
uint32_t is; // 0x08
uint32_t pi; // 0x0C
uint32_t vs; // 0x10
uint32_t ccc_ctl; // 0x14
uint32_t ccc_ports; // 0x18
uint32_t em_loc; // 0x1C
uint32_t em_ctl; // 0x20
uint32_t cap2; // 0x24
uint32_t bohc; // 0x28
// Reserved
uint32_t __res0[13];
// Reserved for NVMHCI
// Also vendor specific settings
uint32_t __res1[40];
// Port control registers
struct ahci_port_registers {
uint32_t p_clb;
uint32_t p_clbu;
uint32_t p_fb;
uint32_t p_fbu;
uint32_t p_is;
uint32_t p_ie;
uint32_t p_cmd;
uint32_t __res0;
uint32_t p_tfd;
uint32_t p_sig;
uint32_t p_ssts;
uint32_t p_sctl;
uint32_t p_serr;
uint32_t p_sact;
uint32_t p_ci;
uint32_t p_sntf;
uint32_t p_fbs;
uint32_t p_devslp;
uint32_t __res1[14];
} __attribute__((packed)) ports[32];
} __attribute__((packed));
struct ahci_fis_reg_h2d {
uint8_t type;
uint8_t cmd_port;
uint8_t cmd;
uint8_t feature_low;
uint8_t lba0;
uint8_t lba1;
uint8_t lba2;
uint8_t dev;
uint8_t lba3;
uint8_t lba4;
uint8_t lba5;
uint8_t feature_high;
uint8_t countl;
uint8_t counth;
uint8_t icc;
uint8_t control;
uint8_t __res0[4];
};
struct ahci_fis_reg_d2h {
uint8_t type;
uint8_t cmd_port;
uint8_t status;
uint8_t error;
uint8_t lba0;
uint8_t lba1;
uint8_t lba2;
uint8_t dev;
uint8_t lba3;
uint8_t lba4;
uint8_t lba5;
uint8_t __res0;
uint8_t countl;
uint8_t counth;
uint8_t __res1[6];
};
struct ahci_fis_dma_setup {
uint8_t type;
uint8_t cmd_port;
uint8_t __res0[2];
uint64_t dma_buffer_id;
uint32_t __res1;
uint32_t dma_buffer_offset;
uint32_t transfer_count;
uint32_t __res2;
};
struct ahci_fis_pio_setup {
uint8_t type;
uint8_t cmd_port;
uint8_t status;
uint8_t error;
uint8_t lba0;
uint8_t lba1;
uint8_t lba2;
uint8_t device;
uint8_t lba3;
uint8_t lba4;
uint8_t lba5;
uint8_t __res0;
uint8_t countl;
uint8_t counth;
uint8_t __res1;
uint8_t e_status;
uint16_t tc;
uint8_t __res2[2];
};
struct ahci_fis_data {
uint8_t type;
uint8_t cmd_port;
uint8_t __res0[2];
uint32_t data[];
};
struct ahci_recv_fis {
union {
// DMA setup FIS
struct ahci_fis_dma_setup dsfis;
char __block0[0x20];
};
union {
// PIO setup FIS
struct ahci_fis_pio_setup psfis;
char __block1[0x20];
};
union {
// Register FIS
struct ahci_fis_reg_d2h rfis;
char __block2[0x18];
};
union {
// Set device bits FIS
char __block3[0x2];
};
union {
// Unknown FIS
char __block4[0x40];
};
};
struct ahci_command_header {
// Bits:
// 0..4 Command length in dwords
// 5 ATAPI
uint16_t attr;
uint16_t prdtl;
volatile uint32_t prdbc;
uint32_t ctba;
uint32_t ctbau;
uint32_t __res0[4];
} __attribute__((packed));
struct ahci_prdt_entry {
uint32_t dba;
uint32_t dbau;
uint32_t __res0;
// Bits:
// 0 1
// 1..21 Data byte count
// 22..30 Reserved
// 31 Interrupt
uint32_t dbc;
} __attribute__((packed));
struct ahci_command_table_entry {
union {
struct ahci_fis_reg_h2d fis_reg_h2d;
uint8_t __cmd_fis[64];
} __attribute__((packed));
uint8_t acmd[16];
uint8_t __res0[48];
struct ahci_prdt_entry prdt[];
} __attribute__((packed));
#define AHCI_PORT_CMD_LIST(p) (struct ahci_command_header *) MM_VIRTUALIZE(((uintptr_t) (p)->p_clbu << 32) | ((p)->p_clb))
#define AHCI_CMD_TABLE_ENTRY(l, i) (struct ahci_command_table_entry *) MM_VIRTUALIZE(((uintptr_t) (l)[i].ctbau << 32) | ((l)[i].ctba))
uint32_t ahci_irq(void *ctx);
void ahci_sata_read(struct ahci_port_registers *port, void *buf, uint32_t nsect, uint64_t lba);
void ahci_sata_write(struct ahci_port_registers *port, const void *buf, uint32_t nsect, uint64_t lba);
void ahci_port_start(struct ahci_port_registers *port);
void ahci_port_stop(struct ahci_port_registers *port);
void ahci_port_init(uint8_t n, struct ahci_port_registers *port);
void ahci_init(struct ahci_registers *regs);
include/sys/amd64/hw/ide/ata.h
-44
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#pragma once
#define ATA_REG_DATA 0x00
#define ATA_REG_ERROR 0x01
#define ATA_REG_FEATURES 0x01
#define ATA_REG_SECCOUNT0 0x02
#define ATA_REG_LBA0 0x03
#define ATA_REG_LBA1 0x04
#define ATA_REG_LBA2 0x05
#define ATA_REG_HDDEVSEL 0x06
#define ATA_REG_COMMAND 0x07
#define ATA_REG_STATUS 0x07
#define ATA_REG_SECCOUNT1 0x08
#define ATA_REG_LBA3 0x09
#define ATA_REG_LBA4 0x0A
#define ATA_REG_LBA5 0x0B
#define ATA_REG_CONTROL 0x0C
#define ATA_REG_ALTSTATUS 0x0C
#define ATA_REG_DEVADDRESS 0x0D
#define ATA_CONTROL_NO_INT (1 << 1)
#define ATA_CMD_IDENTIFY 0xEC
#define ATA_CMD_IDENTIFY_PACKET 0xA1
#define ATA_CMD_READ_PIO 0x20
#define ATA_CMD_READ_PIO_EX 0x24
#define ATA_CMD_READ_DMA 0xC8
#define ATA_CMD_READ_DMA_EX 0x25
#define ATA_CMD_WRITE_DMA_EX 0x35
#define ATA_SR_BUSY (1 << 7)
#define ATA_SR_DRQ (1 << 3)
#define ATA_SR_ERR (1 << 0)
#define ATA_IDENT_DEVICE_TYPE 0x00
#define ATA_IDENT_CYLINDERS 0x02
#define ATA_IDENT_HEADS 0x06
#define ATA_IDENT_SECTORS 0x0C
#define ATA_IDENT_SERIAL 0x14
#define ATA_IDENT_MODEL 0x36
#define ATA_IDENT_CAPS 0x62
#define ATA_IDENT_MAX_LBA 0x78
#define ATA_IDENT_CMD_SETS 0xA4
#define ATA_IDENT_MAX_LBAEXT 0xC8
include/sys/amd64/hw/ide/ide.h
-52
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@@ -1,52 +0,0 @@
#pragma once
#include "sys/types.h"
#define IDE_DEFAULT_BAR0 0x1F0
#define IDE_DEFAULT_BAR1 0x3F6
#define IDE_DEFAULT_BAR2 0x170
#define IDE_DEFAULT_BAR3 0x376
struct ide_prdt_entry {
uint32_t addr;
uint16_t size;
uint16_t attr;
} __attribute__((packed));
struct ide_controller {
uint16_t bar0; // Primary channel
uint16_t bar1; // Primary control port
uint16_t bar2; // Secondary channel
uint16_t bar3; // Secondary control port
uint16_t bar4; // Bus master control
uint8_t irq0, irq1;
uintptr_t dma_page;
struct ide_channel {
uint16_t base;
uint16_t ctrl;
uint16_t bmide;
uint8_t no_int;
} channels[2];
struct ide_device {
// Bits:
// 0 1 if device is present here
// 1 0 if on primary channel
// 2 1 if slave device
// 3 1 if device is ATAPI (ATA otherwise)
// ...
struct ide_controller *ide;
uint8_t attr;
uint16_t signature;
uint16_t caps;
uint32_t cmd_sets;
size_t size;
char model[41];
} devices[4];
};
int ide_ata_read_pio(struct ide_device *dev, void *buf, size_t nsect, uint64_t lba);
int ide_ata_read_dma(struct ide_device *dev, void *buf, size_t nsect, uint64_t lba);
void ide_init(struct ide_controller *ide);
include/sys/amd64/hw/pci/ahci.h
-9
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#pragma once
#include "pci.h"
#include "sys/amd64/hw/ide/ahci.h"
struct pci_ahci {
pci_addr_t addr;
uint32_t abar_phys;
struct ahci_registers *volatile regs;
};