diff --git a/include/sys/amd64/hw/timer.h b/include/sys/amd64/hw/timer.h
new file mode 100644
index 0000000..fcf8751
--- /dev/null
+++ b/include/sys/amd64/hw/timer.h
@@ -0,0 +1,4 @@
+#pragma once
+#include "sys/types.h"
+
+void amd64_timer_init(uint32_t fq);
diff --git a/sys/amd64/conf.mk b/sys/amd64/conf.mk
index 223fb17..85340a5 100644
--- a/sys/amd64/conf.mk
+++ b/sys/amd64/conf.mk
@@ -17,7 +17,8 @@ OBJS+=$(O)/sys/amd64/hw/rs232.o \
 	  $(O)/sys/amd64/hw/exc_s.o \
 	  $(O)/sys/amd64/hw/irq0.o \
 	  $(O)/sys/amd64/hw/ap_code_blob.o \
-	  $(O)/sys/amd64/hw/con.o
+	  $(O)/sys/amd64/hw/con.o \
+	  $(O)/sys/amd64/hw/timer.o
 
 ### From config
 ifdef AMD64_TRACE_IRQ
diff --git a/sys/amd64/hw/apic.c b/sys/amd64/hw/apic.c
index a5ef0e9..02553d2 100644
--- a/sys/amd64/hw/apic.c
+++ b/sys/amd64/hw/apic.c
@@ -1,4 +1,5 @@
 #include "sys/amd64/hw/apic.h"
+#include "sys/amd64/hw/timer.h"
 #include "sys/amd64/hw/gdt.h"
 #include "sys/amd64/hw/idt.h"
 #include "sys/amd64/mm/mm.h"
@@ -14,12 +15,6 @@
 #define IA32_LAPIC_REG_EOI          0xB0
 #define IA32_LAPIC_REG_SVR          0xF0
 
-#define IA32_LAPIC_REG_LVTT         0x320
-
-#define IA32_LAPIC_REG_TMRINITCNT   0x380
-#define IA32_LAPIC_REG_TMRCURRCNT   0x390
-#define IA32_LAPIC_REG_TMRDIV       0x3E0
-
 #define IA32_LAPIC_REG_CMD0         0x300
 #define IA32_LAPIC_REG_CMD1         0x310
 
@@ -101,16 +96,14 @@ static void amd64_ap_code_entry(void) {
     ++started_up_aps;
     // }}}
 
-    // Enable LAPIC timer
     kdebug("AP %d startup\n", started_up_aps);
 
     // Enable LAPIC.SVR.SoftwareEnable bit
     // And set spurious interrupt mapping to 0xFF
     *(uint32_t *) (lapic_base + IA32_LAPIC_REG_SVR) |= (1 << 8) | (0xFF);
 
-    *(uint32_t *) (lapic_base + IA32_LAPIC_REG_LVTT) = 32 | 0x20000;
-    *(uint32_t *) (lapic_base + IA32_LAPIC_REG_TMRDIV) = 1;
-    *(uint32_t *) (lapic_base + IA32_LAPIC_REG_TMRINITCNT) = 0xFFFFFFF;
+    // Enable LAPIC timer
+    amd64_timer_init(1000);
 
     while (1) {
         asm ("sti; hlt");
@@ -218,8 +211,5 @@ void amd64_apic_init(struct acpi_madt *madt) {
         offset += ent_hdr->length;
     }
 
-    // Enable LAPIC timer
-    *(uint32_t *) (lapic_base + IA32_LAPIC_REG_LVTT) = 32 | 0x20000;
-    *(uint32_t *) (lapic_base + IA32_LAPIC_REG_TMRDIV) = 1;
-    *(uint32_t *) (lapic_base + IA32_LAPIC_REG_TMRINITCNT) = 0xFFFFFFF;
+    amd64_timer_init(1000);
 }
diff --git a/sys/amd64/hw/timer.c b/sys/amd64/hw/timer.c
new file mode 100644
index 0000000..40daef0
--- /dev/null
+++ b/sys/amd64/hw/timer.c
@@ -0,0 +1,19 @@
+#include "sys/amd64/hw/timer.h"
+#include "sys/debug.h"
+
+#define IA32_LAPIC_REG_LVTT         0x320
+
+#define IA32_LAPIC_REG_TMRINITCNT   0x380
+#define IA32_LAPIC_REG_TMRCURRCNT   0x390
+#define IA32_LAPIC_REG_TMRDIV       0x3E0
+
+void amd64_timer_init(uint32_t fq) {
+    // XXX: Frequency is ignore for now:
+    //      Once I set the I/O APIC up,
+    //      PIT will be used for proper
+    //      timer calibration
+
+    *(uint32_t *) (0xFFFFFF00FEE00000 + IA32_LAPIC_REG_TMRDIV) = 0x3;
+    *(uint32_t *) (0xFFFFFF00FEE00000 + IA32_LAPIC_REG_TMRINITCNT) = 10000000;
+    *(uint32_t *) (0xFFFFFF00FEE00000 + IA32_LAPIC_REG_LVTT) = 32 | (1 << 17);
+}