Add a test module

This commit is contained in:
Mark 2020-05-29 15:36:03 +03:00
parent 21ddacc451
commit 4df8f04583
4 changed files with 121 additions and 1 deletions

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@ -20,7 +20,9 @@ STAGE_BIN=$(STAGE)/init \
$(STAGE)/bin/mount \
$(STAGE)/bin/umount \
$(STAGE)/bin/date \
$(STAGE)/bin/login
$(STAGE)/bin/login \
$(STAGE)/bin/insmod \
$(STAGE)/test.ko
# TODO
# newlib: gettimeofday is broken?
@ -98,6 +100,18 @@ $(STAGE)/bin/vsh: $(vsh_OBJS)
$(STAGE)/bin/ase: $(ase_OBJS)
$(CC) -o $@ $(usr_LDFLAGS) $(ase_OBJS)
$(STAGE)/test.ko: module.c module.ld
$(CC) \
-I ../kernel/include \
-r \
-O0 \
-g \
-mcmodel=large \
-Tmodule.ld \
-nostdlib \
-ffreestanding \
-o $@ module.c
$(O)/vsh/%.o: vsh/%.c $(shell find vsh -name "*.h")
$(CC) -c -o $@ $(usr_CFLAGS) $<
$(O)/vsh/%.o: vsh/%.S

63
core/bin/insmod.c Normal file
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@ -0,0 +1,63 @@
#include <ygg/syscall.h>
#include <unistd.h>
#include <string.h>
#include <stdio.h>
static __attribute__((optimize("-O0"))) int ygg_module_load(const char *file, const char *args) {
register uintptr_t rdi asm("rdi") = (uintptr_t) file;
register uintptr_t rsi asm("rsi") = (uintptr_t) args;
register uintptr_t rax asm("rax") = SYSCALL_NRX_MODULE_LOAD;
asm volatile ("syscall":::"rax","rdi","rsi");
(void) rdi;
(void) rsi;
return (int) rax;
}
static __attribute__((optimize("-O0"))) int ygg_module_unload(const char *name) {
register uintptr_t rdi asm("rdi") = (uintptr_t) name;
register uintptr_t rax asm("rax") = SYSCALL_NRX_MODULE_UNLOAD;
asm volatile ("syscall":::"rax","rdi");
(void) rdi;
return (int) rax;
}
static const char *usage = "Usage: insmod <module path>\n"
" OR insmod -r <module name>\n";
int main(int argc, char **argv) {
int res;
if (argc > 3 || argc < 2) {
fprintf(stderr, usage);
return -1;
}
if (getuid() != 0) {
fprintf(stderr, "Only root can do that\n");
return -1;
}
if (argc == 2) {
if (access(argv[1], F_OK) != 0) {
perror(argv[1]);
return -1;
}
if ((res = ygg_module_load(argv[1], NULL)) < 0) {
fprintf(stderr, "%s: %s\n", argv[1], strerror(-res));
return -1;
}
} else {
if (strcmp(argv[1], "-r")) {
fprintf(stderr, usage);
return -1;
}
if ((res = ygg_module_unload(argv[2])) < 0) {
fprintf(stderr, "%s: %s\n", argv[2], strerror(-res));
return -1;
}
}
return 0;
}

16
module.c Normal file
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@ -0,0 +1,16 @@
#include <ygg/module.h>
#include <sys/debug.h>
#include <stdint.h>
MODULE_DESC("test-mod", 0x00010000);
extern uint64_t system_time;
void MODULE_EXIT(void) {
kinfo("Exiting the module!\n");
}
int MODULE_ENTRY(void) {
kinfo("This should work, I guess: %s, %d\n", "a string", 123);
return 0;
}

27
module.ld Normal file
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@ -0,0 +1,27 @@
ENTRY(_mod_entry);
SECTIONS {
/*
* Modules are linked with 0x0 base virtual address
* and are position independent
*/
. = 0x100000000;
.text : ALIGN(4K) {
*(.text*)
}
.rodata : {
*(.rodata)
*(.eh_frame)
}
.data : ALIGN(4K) {
*(.data*)
}
.bss : {
*(COMMON)
*(.bss*)
}
}