2021-10-22 16:42:04 +08:00
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/* LoongArch assembler/disassembler support.
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2024-01-04 22:22:08 +10:30
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Copyright (C) 2021-2024 Free Software Foundation, Inc.
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2021-10-22 16:42:04 +08:00
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Contributed by Loongson Ltd.
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This file is part of GNU Binutils.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the license, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; see the file COPYING3. If not,
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see <http://www.gnu.org/licenses/>. */
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#ifndef _LOONGARCH_H_
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#define _LOONGARCH_H_
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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2022-12-01 14:34:10 +08:00
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#define LARCH_NOP 0x03400000
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2023-09-24 14:53:28 +08:00
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#define LARCH_B 0x50000000
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/* BCEQZ/BCNEZ. */
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#define LARCH_FLOAT_BRANCH 0x48000000
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#define LARCH_BRANCH_OPCODE_MASK 0xfc000000
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#define LARCH_BRANCH_INVERT_BIT 0x04000000
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#define LARCH_FLOAT_BRANCH_INVERT_BIT 0x00000100
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#define ENCODE_BRANCH16_IMM(x) (((x) >> 2) << 10)
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#define OUT_OF_RANGE(value, bits, align) \
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((value) < (-(1 << ((bits) - 1) << align)) \
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|| (value) > ((((1 << ((bits) - 1)) - 1) << align)))
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2022-12-01 14:34:10 +08:00
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LoongArch: Add tls transition support.
Transitions between DESC->IE/LE and IE->LE are supported now.
1. For DESC -> LE:
pcalau12i $a0,%desc_pc_hi20(var) => lu12i.w $a0,%le_hi20(var)
addi.d $a0,$a0,%desc_pc_lo12(var) => ori $a0,$a0,%le_lo12(var)
ld.d $a1,$a0,%desc_ld(var) => NOP
jirl $ra,$a1,%desc_call(var) => NOP
add.d $a0,$a0,$tp
2. For DESC -> IE:
pcalau12i $a0,%desc_pc_hi20(var) => pcalau12i $a0,%ie_pc_hi20(var)
addi.d $a0,$a0,%desc_pc_lo12(var) => ld.d $a0,$a0,%ie_pc_lo12(var)
ld.d $a1,$a0,%desc_ld(var) => NOP
jirl $ra,$a1,%desc_call(var) => NOP
add.d $a0,$a0,$tp
3. For IE -> LE:
pcalau12i $a0,%ie_pc_hi20(var) => lu12i.w $a0,%le_hi20(var)
ld.d $a0,$a0,%ie_pc_lo12(var) => ori $a0,$a0,%le_lo12(var)
add.d $a0,$a0,$tp
4. When a tls variable is accessed using both DESC and IE, DESC transitions
to IE and uses the same GOT entry as IE.
2023-11-26 14:25:26 +08:00
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#define LARCH_LU12I_W 0x14000000
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#define LARCH_ORI 0x03800000
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#define LARCH_LD_D 0x28c00000
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#define LARCH_RD_A0 0x04
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#define LARCH_RD_RJ_A0 0x084
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2021-10-22 16:42:04 +08:00
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typedef uint32_t insn_t;
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struct loongarch_opcode
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{
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const insn_t match;
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const insn_t mask; /* High 1 byte is main opcode and it must be 0xf. */
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#define LARCH_INSN_OPC(insn) ((insn & 0xf0000000) >> 28)
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const char *const name;
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/* ACTUAL PARAMETER:
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// BNF with regular expression.
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args : token* end
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// just few char separate 'iden'
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token : ','
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| '('
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| ')'
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| iden // maybe a label (include at least one alphabet),
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maybe a number, maybe a expr
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| regname
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regname : '$' iden
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iden : [a-zA-Z0-9\.\+\-]+
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end : '\0'
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FORMAT: A string to describe the format of actual parameter including
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bit field infomation. For example, "r5:5,r0:5,sr10:16<<2" matches
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"$12,$13,12345" and "$4,$7,a_label". That 'sr' means the instruction
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may need relocate. '10:16' means bit field of instruction.
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In a 'format', every 'escape's can be replaced to 'iden' or 'regname'
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acrroding to its meaning. We fill all information needed by
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disassembing and assembing to 'format'.
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// BNF with regular expression.
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format : escape (literal+ escape)* literal* end
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| (literal+ escape)* literal* end
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end : '\0' // Get here means parse end.
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// The intersection between any two among FIRST (end), FIRST
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// (literal) and FIRST (escape) must be empty.
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// So we can build a simple parser.
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literal : ','
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| '('
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| ')'
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// Double '<'s means the real number is the immediate after shifting left.
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escape : esc_ch bit_field '<' '<' dec2
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| esc_ch bit_field
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| esc_ch // for MACRO. non-macro format must indicate 'bit_field'
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// '|' means to concatenate nonadjacent bit fields
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// For example, "10:16|0:4" means
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// "16 bits starting from the 10th bit concatenating with 4 bits
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// starting from the 0th bit".
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// This is to say "[25..10]||[3..0]" (little endian).
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b_field : dec2 ':' dec2
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| dec2 ':' dec2 '|' bit_field
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esc_ch : 's' 'r' // signed immediate or label need relocate
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| 's' // signed immediate no need relocate
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| 'u' // unsigned immediate
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| 'l' // label needed relocate
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| 'r' // general purpose registers
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| 'f' // FPU registers
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| 'v' // 128 bit SIMD register
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| 'x' // 256 bit SIMD register
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dec2 : [1-9][0-9]?
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| 0
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*/
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const char *const format;
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/* MACRO: Indicate how a macro instruction expand for assembling.
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The main is to replace the '%num'(means the 'num'th 'escape' in
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'format') in 'macro' string to get the real instruction.
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Maybe need
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*/
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const char *const macro;
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const int *include;
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const int *exclude;
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const unsigned long pinfo;
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#define USELESS 0x0l
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LoongArch: support disassembling certain pseudo-instructions
Add a flag in the pinfo field for being able to mark certain specialized
matchers as disassembler-only, so some degree of isolation between
assembler-side and disassembler-side can be achieved.
This isolation is necessary, firstly because some pseudo-instructions
cannot be fully described in the opcode table, like `li.[wd]`, so the
corresponding opcode entry cannot have meaningful match/mask values.
Secondly, some of these pseudo-instructions can be realized in more than
one plausible ways; e.g. `li.w rd, <something between 0 and 0x7ff>` can
be realized on LA64 with any of `addi.w`, `addi.d` or `ori`. If we tie
disassembly of such aliases with the corresponding GAS support, only one
canonical form among the above would be recognized as `li.w`, and it
would mildly impact the readability of disassembly output.
People wanting the exact disassembly can always set `-M no-aliases` to
get the original behavior back.
In addition, in certain cases, information is irreversibly lost after
assembling, so perfect round-trip would not be possible in such cases.
For example, `li.w` and `li.d` of immediates within int32_t range
produce the same code; in this patch, `addi.d rd, $zero, imm` is treated
as `li.d`, while `addi.w` and `ori` immediate loads are shown as `li.w`,
due to the expressible value range well within 32 bits.
gas/ChangeLog:
* config/tc-loongarch.c (get_loongarch_opcode): Ignore
disassembler-only aliases.
* testsuite/gas/loongarch/64_pcrel.d: Update test case.
* testsuite/gas/loongarch/imm_ins.d: Likewise.
* testsuite/gas/loongarch/imm_ins_32.d: Likewise.
* testsuite/gas/loongarch/jmp_op.d: Likewise.
* testsuite/gas/loongarch/li.d: Likewise.
* testsuite/gas/loongarch/macro_op.d: Likewise.
* testsuite/gas/loongarch/macro_op_32.d: Likewise.
* testsuite/gas/loongarch/macro_op_large_abs.d: Likewise.
* testsuite/gas/loongarch/macro_op_large_pc.d: Likewise.
* testsuite/gas/loongarch/nop.d: Likewise.
* testsuite/gas/loongarch/relax_align.d: Likewise.
* testsuite/gas/loongarch/reloc.d: Likewise.
include/ChangeLog:
* opcode/loongarch.h (INSN_DIS_ALIAS): Add.
ld/ChangeLog:
* testsuite/ld-loongarch-elf/jmp_op.d: Update test case.
* testsuite/ld-loongarch-elf/macro_op.d: Likewise.
* testsuite/ld-loongarch-elf/macro_op_32.d: Likewise.
* testsuite/ld-loongarch-elf/relax-align.dd: Likewise.
opcodes/ChangeLog:
* loongarch-dis.c: Move register name map declarations to top.
(get_loongarch_opcode_by_binfmt): Consider aliases when
disassembling without the no-aliases option.
(parse_loongarch_dis_option): Support the no-aliases option.
* loongarch-opc.c: Collect pseudo instructions into a new
dedicated table.
Signed-off-by: WANG Xuerui <git@xen0n.name>
2023-06-30 00:34:58 +08:00
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/* Instruction is a simple alias only for disassembler use. */
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#define INSN_DIS_ALIAS 0x00000001l
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2021-10-22 16:42:04 +08:00
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};
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struct hash_control;
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struct loongarch_ase
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{
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const int *enabled;
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struct loongarch_opcode *const opcodes;
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const int *include;
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const int *exclude;
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/* For disassemble to create main opcode hash table. */
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const struct loongarch_opcode *opc_htab[16];
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unsigned char opc_htab_inited;
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/* For GAS to create hash table. */
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struct htab *name_hash_entry;
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};
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extern int is_unsigned (const char *);
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extern int is_signed (const char *);
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extern int is_branch_label (const char *);
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extern int loongarch_get_bit_field_width (const char *bit_field, char **end);
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extern int32_t loongarch_decode_imm (const char *bit_field, insn_t insn,
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int si);
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#define MAX_ARG_NUM_PLUS_2 9
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extern size_t loongarch_split_args_by_comma (char *args,
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const char *arg_strs[]);
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extern char *loongarch_cat_splited_strs (const char *arg_strs[]);
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extern insn_t loongarch_foreach_args (
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const char *format, const char *arg_strs[],
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int32_t (*helper) (char esc1, char esc2, const char *bit_field,
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const char *arg, void *context),
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void *context);
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extern int loongarch_check_format (const char *format);
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extern int loongarch_check_macro (const char *format, const char *macro);
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extern char *loongarch_expand_macro_with_format_map (
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const char *format, const char *macro, const char *const arg_strs[],
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const char *(*map) (char esc1, char esc2, const char *arg),
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char *(*helper) (const char *const arg_strs[], void *context),
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2022-03-20 09:18:00 +08:00
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void *context, size_t len_str);
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2021-10-22 16:42:04 +08:00
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extern char *loongarch_expand_macro (
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const char *macro, const char *const arg_strs[],
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char *(*helper) (const char *const arg_strs[], void *context),
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2022-03-20 09:18:00 +08:00
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void *context, size_t len_str);
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2021-10-22 16:42:04 +08:00
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extern size_t loongarch_bits_imm_needed (int64_t imm, int si);
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extern void loongarch_eliminate_adjacent_repeat_char (char *dest, char c);
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extern const char *const loongarch_r_normal_name[32];
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2023-10-30 17:07:08 +08:00
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extern const char *const loongarch_r_alias[32];
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2024-01-26 10:50:57 +00:00
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extern const char *const loongarch_r_alias_1[32];
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2023-10-30 17:07:08 +08:00
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extern const char *const loongarch_r_alias_deprecated[32];
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2021-10-22 16:42:04 +08:00
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extern const char *const loongarch_f_normal_name[32];
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2023-10-30 17:07:08 +08:00
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extern const char *const loongarch_f_alias[32];
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extern const char *const loongarch_f_alias_deprecated[32];
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2023-06-16 11:16:10 +08:00
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extern const char *const loongarch_fc_normal_name[4];
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extern const char *const loongarch_fc_numeric_name[4];
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2021-10-22 16:42:04 +08:00
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extern const char *const loongarch_c_normal_name[8];
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extern const char *const loongarch_cr_normal_name[4];
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extern const char *const loongarch_v_normal_name[32];
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extern const char *const loongarch_x_normal_name[32];
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extern struct loongarch_ase loongarch_ASEs[];
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extern struct loongarch_ASEs_option
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{
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struct opt_abi
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{
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int elf_abi;
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} abi;
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#define ase_abi abi.elf_abi
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struct opt_isa
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{
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int use_ilp32;
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int use_lp64;
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int use_soft_float;
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int use_single_float;
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int use_double_float;
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int use_lsx;
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int use_lasx;
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2023-06-30 17:04:15 +08:00
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int use_lvz;
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int use_lbt;
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2021-10-22 16:42:04 +08:00
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int use_la_local_with_abs;
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int use_la_global_with_pcrel;
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int use_la_global_with_abs;
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} isa;
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#define ase_ilp32 isa.use_ilp32
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#define ase_lp64 isa.use_lp64
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#define ase_nf isa.use_soft_float
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#define ase_sf isa.use_single_float
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#define ase_df isa.use_double_float
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#define ase_lsx isa.use_lsx
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#define ase_lasx isa.use_lasx
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2023-06-30 17:04:15 +08:00
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#define ase_lvz isa.use_lvz
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#define ase_lbt isa.use_lbt
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2021-10-22 16:42:04 +08:00
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#define ase_labs isa.use_la_local_with_abs
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#define ase_gpcr isa.use_la_global_with_pcrel
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#define ase_gabs isa.use_la_global_with_abs
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2022-12-01 14:34:10 +08:00
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int relax;
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2023-09-28 16:01:52 +08:00
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int thin_add_sub;
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2021-10-22 16:42:04 +08:00
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} LARCH_opts;
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extern size_t loongarch_insn_length (insn_t insn);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _LOONGARCH_H_ */
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