RISC-V: don't disassemble unrecognized insns as .byte
Insn width granularity being 16 bits, producing byte granular output isn't very useful. With there being a way to specific otherwise unknown insns to the assembler, use that same representation (to be precise: its <length>,<encoding> flavor) for disassembly.
This commit is contained in:
Jan Beulich
parent
96e034530e
commit
0655669b86
@ -1,11 +1,11 @@
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#as: -march=rv32ic
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#objdump: -d
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# Test the disassembly of unknown instruction encodings, specifically,
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# ensure that we generate a .?byte opcode.
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# ensure that we generate a .insn directive.
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#...
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Disassembly of section \.text:
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[0-9a-f]+ <\.text>:
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[0-9a-f]+: 0052018b \.4byte 0x52018b
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[0-9a-f]+: 9c45 \.2byte 0x9c45
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[0-9a-f]+: 0052018b \.insn 4, 0x0052018b
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[0-9a-f]+: 9c45 \.insn 2, 0x9c45
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@ -73,11 +73,11 @@ Disassembly of section .text:
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[^:]+:[ ]+007f 0000 0000 0000 0000[ ]+[._a-z].*
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[^:]+:[ ]+0000107f 00000000 00000000[ ]+[._a-z].*
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[^:]+:[ ]+607f 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000[ ]+[._a-z].*
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[^:]+:[ ]+007f 0000 0000 0000 8000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80
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[^:]+:[ ]+007f 0000 0000 0000 8000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80
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[^:]+:[ ]+607f 89ab 4567 0123 3210 7654 ba98 fedc 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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[^:]+:[ ]+607f 89ab 4567 0123 3210 7654 ba98 fedc 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 00dc[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00
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[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 00dc[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00
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[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 fedc[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe
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[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 fedc[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe
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[^:]+:[ ]+007f 0000 0000 0000 8000[ ]+\.insn[ ]+10, +0x8000000000000000007f
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[^:]+:[ ]+007f 0000 0000 0000 8000[ ]+\.insn[ ]+10, +0x8000000000000000007f
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[^:]+:[ ]+607f 89ab 4567 0123 3210 7654 ba98 fedc 0000 0000 0000[ ]+\.insn[ ]+22, 0xfedcba98765432100123456789ab607f
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[^:]+:[ ]+607f 89ab 4567 0123 3210 7654 ba98 fedc 0000 0000 0000[ ]+\.insn[ ]+22, 0xfedcba98765432100123456789ab607f
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[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 00dc[ ]+\.insn[ ]+22, 0x00dcba98765432100123456789abcdef55aa33cc607f
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[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 00dc[ ]+\.insn[ ]+22, 0x00dcba98765432100123456789abcdef55aa33cc607f
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[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 fedc[ ]+\.insn[ ]+22, 0xfedcba98765432100123456789abcdef55aa33cc607f
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[^:]+:[ ]+607f 33cc 55aa cdef 89ab 4567 0123 3210 7654 ba98 fedc[ ]+\.insn[ ]+22, 0xfedcba98765432100123456789abcdef55aa33cc607f
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@ -92,25 +92,25 @@ Disassembly of section .text:
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[^:]+:[ ]+607f 0000 0000 0000[ ]+[._a-z].*
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[^:]+:[ ]+0000 0000 0000 0000 ?
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[^:]+:[ ]+0000 0000 0000 ?
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[^:]+:[ ]+007f 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80
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[^:]+:[ ]+007f 0000 0000 0000[ ]+\.insn[ ]+10, +0x8000000000000000007f
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[^:]+:[ ]+8000 ?
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[^:]+:[ ]+007f 0000 0000 0000[ ]+\.byte[ ]+0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80
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[^:]+:[ ]+007f 0000 0000 0000[ ]+\.insn[ ]+10, +0x8000000000000000007f
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[^:]+:[ ]+8000 ?
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[^:]+:[ ]+607f 89ab 4567 0123[ ]+\.byte[ ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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[^:]+:[ ]+607f 89ab 4567 0123[ ]+\.insn[ ]+22, 0xfedcba98765432100123456789ab607f
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[^:]+:[ ]+3210 7654 ba98 fedc ?
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[^:]+:[ ]+0000 0000 0000 ?
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[^:]+:[ ]+607f 89ab 4567 0123[ ]+\.byte[ ]+0x7f, 0x60, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
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[^:]+:[ ]+607f 89ab 4567 0123[ ]+\.insn[ ]+22, 0xfedcba98765432100123456789ab607f
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[^:]+:[ ]+3210 7654 ba98 fedc ?
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[^:]+:[ ]+0000 0000 0000 ?
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[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00
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[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.insn[ ]+22, 0x00dcba98765432100123456789abcdef55aa33cc607f
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[^:]+:[ ]+89ab 4567 0123 3210 ?
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[^:]+:[ ]+7654 ba98 00dc ?
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[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0x00
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[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.insn[ ]+22, 0x00dcba98765432100123456789abcdef55aa33cc607f
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[^:]+:[ ]+89ab 4567 0123 3210 ?
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[^:]+:[ ]+7654 ba98 00dc ?
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[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe
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[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.insn[ ]+22, 0xfedcba98765432100123456789abcdef55aa33cc607f
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[^:]+:[ ]+89ab 4567 0123 3210 ?
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[^:]+:[ ]+7654 ba98 fedc ?
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[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.byte[ ]+0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe
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[^:]+:[ ]+607f 33cc 55aa cdef[ ]+\.insn[ ]+22, 0xfedcba98765432100123456789abcdef55aa33cc607f
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[^:]+:[ ]+89ab 4567 0123 3210 ?
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[^:]+:[ ]+7654 ba98 fedc ?
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@ -650,7 +650,8 @@ riscv_disassemble_insn (bfd_vma memaddr,
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static bool init = false;
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static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
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struct riscv_private_data *pd;
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int insnlen;
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int insnlen, i;
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bool printed;
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#define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP))
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@ -666,8 +667,6 @@ riscv_disassemble_insn (bfd_vma memaddr,
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if (info->private_data == NULL)
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{
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int i;
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pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data));
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pd->gp = 0;
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pd->print_addr = 0;
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@ -783,37 +782,28 @@ riscv_disassemble_insn (bfd_vma memaddr,
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}
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}
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/* We did not find a match, so just print the instruction bits. */
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/* We did not find a match, so just print the instruction bits in
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the shape of an assembler .insn directive. */
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info->insn_type = dis_noninsn;
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switch (insnlen)
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(*info->fprintf_styled_func)
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(info->stream, dis_style_assembler_directive, ".insn");
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(*info->fprintf_styled_func) (info->stream, dis_style_text, "\t");
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(*info->fprintf_styled_func) (info->stream, dis_style_immediate,
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"%d", insnlen);
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(*info->fprintf_styled_func) (info->stream, dis_style_text, ", ");
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(*info->fprintf_styled_func) (info->stream, dis_style_immediate, "0x");
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for (i = insnlen, printed = false; i >= 2; )
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{
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case 2:
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case 4:
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case 8:
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(*info->fprintf_styled_func)
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(info->stream, dis_style_assembler_directive, ".%dbyte", insnlen);
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(*info->fprintf_styled_func) (info->stream, dis_style_text, "\t");
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i -= 2;
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word = bfd_get_bits (packet + i, 16, false);
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if (!word && !printed)
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continue;
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(*info->fprintf_styled_func) (info->stream, dis_style_immediate,
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"0x%llx", (unsigned long long) word);
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break;
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default:
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{
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int i;
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(*info->fprintf_styled_func)
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(info->stream, dis_style_assembler_directive, ".byte");
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(*info->fprintf_styled_func) (info->stream, dis_style_text, "\t");
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for (i = 0; i < insnlen; ++i)
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{
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if (i > 0)
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(*info->fprintf_styled_func) (info->stream, dis_style_text,
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", ");
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(*info->fprintf_styled_func) (info->stream, dis_style_immediate,
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"0x%02x",
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(unsigned int) (*packet++));
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}
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}
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break;
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"%04x", (unsigned int) word);
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printed = true;
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}
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return insnlen;
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}
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