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RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard

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According to the riscv psabi, R_RISCV_SUB6 only allows 6 least significant
bits are valid, but since binutils implementation, we usually get 8 bits
field for it.  That means, the high 2 bits could be other field and have
different purpose.  Therefore, we should filter the 8 bits to 6 bits before
calculate, and then only encode the valid 6 bits back.  By the way, we also
need the out-of-range check for R_RISCV_SUB6, and the overflow checks for
all R_RISCV_ADD/SUB/SET relocations, but we can add them in the future patches.

Passing riscv-gnu-toolchain regressions.

bfd/ChangeLog:

        * elfnn-riscv.c (riscv_elf_relocate_section): Take the R_RISCV_SUB6
	lower 6 bits as the significant bit.
        * elfxx-riscv.c (riscv_elf_add_sub_reloc): Likewise.
This commit is contained in:
Xiao Zeng 2022-11-21 20:00:37 +08:00 committed by Nelson Chu
parent ba64682044
commit 06f0a892a5
2 changed files with 13 additions and 0 deletions
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9
bfd/elfnn-riscv.c
View File

@ -2427,6 +2427,15 @@ riscv_elf_relocate_section (bfd *output_bfd,
break;
case R_RISCV_SUB6:
{
bfd_vma old_value = bfd_get (howto->bitsize, input_bfd,
contents + rel->r_offset);
relocation = (old_value & ~howto->dst_mask)
| (((old_value & howto->dst_mask) - relocation)
& howto->dst_mask);
}
break;
case R_RISCV_SUB8:
case R_RISCV_SUB16:
case R_RISCV_SUB32:

4
bfd/elfxx-riscv.c
View File

@ -994,6 +994,10 @@ riscv_elf_add_sub_reloc (bfd *abfd,
relocation = old_value + relocation;
break;
case R_RISCV_SUB6:
relocation = (old_value & ~howto->dst_mask)
| (((old_value & howto->dst_mask) - relocation)
& howto->dst_mask);
break;
case R_RISCV_SUB8:
case R_RISCV_SUB16:
case R_RISCV_SUB32: