Add ARM v5t, v5te and XScale support
This commit is contained in:
Nick Clifton
parent
49425d281c
commit
077b8428ab
@ -1,3 +1,9 @@
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2000-11-24 Nick Clifton <nickc@redhat.com>
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* configure.in (xscale-elf): Add target.
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(xscale-coff): Add target.
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(c4x, c5x, tic54x): Move after ARM targets.
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2000-11-23 Alexandre Oliva <aoliva@redhat.com>
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* ltcf-gcj.sh: Added file, required by 2000-11-18 merge.
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@ -1,3 +1,21 @@
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2000-11-24 Nick Clifton <nickc@redhat.com>
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* archures.c (bfd_mach_arm_5TE): Define.
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(bfd_mach_arm+XScale): Define.
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* bfd-in2.h: Regenerate.
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* coff-arm.c (coff_arm_reloc_type_lookup): Accept
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BFD_RELOC_ARM_PCREL_BLX.
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* coffcode.h (coff_set_flags): Set flags for 5t, 5te and
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XScale machine numbers.
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* config.bfd (xscale-elf): Add target.
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(xscale-coff): Add target.
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* cpu-arm.c: Add xscale machine name.
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Add v5t, v5te and XScale machine numbers.
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2000-11-23 Kazu Hirata <kazu@hxi.com>
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* aix386-core.c: Fix formatting.
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@ -205,6 +205,8 @@ DESCRIPTION
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.#define bfd_mach_arm_4T 6
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.#define bfd_mach_arm_5 7
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.#define bfd_mach_arm_5T 8
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.#define bfd_mach_arm_5TE 9
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.#define bfd_mach_arm_XScale 10
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. bfd_arch_ns32k, {* National Semiconductors ns32000 *}
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. bfd_arch_w65, {* WDC 65816 *}
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. bfd_arch_tic30, {* Texas Instruments TMS320C30 *}
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@ -1471,6 +1471,8 @@ enum bfd_architecture
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#define bfd_mach_arm_4T 6
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#define bfd_mach_arm_5 7
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#define bfd_mach_arm_5T 8
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#define bfd_mach_arm_5TE 9
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#define bfd_mach_arm_XScale 10
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bfd_arch_ns32k, /* National Semiconductors ns32000 */
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bfd_arch_w65, /* WDC 65816 */
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bfd_arch_tic30, /* Texas Instruments TMS320C30 */
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@ -845,6 +845,7 @@ coff_arm_reloc_type_lookup (abfd, code)
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ASTD (BFD_RELOC_16, ARM_16);
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ASTD (BFD_RELOC_32, ARM_32);
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ASTD (BFD_RELOC_ARM_PCREL_BRANCH, ARM_26);
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ASTD (BFD_RELOC_ARM_PCREL_BLX, ARM_26);
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ASTD (BFD_RELOC_8_PCREL, ARM_DISP8);
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ASTD (BFD_RELOC_16_PCREL, ARM_DISP16);
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ASTD (BFD_RELOC_32_PCREL, ARM_DISP32);
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@ -2596,7 +2596,10 @@ coff_set_flags (abfd, magicp, flagsp)
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case bfd_mach_arm_4: * flagsp |= F_ARM_4; break;
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case bfd_mach_arm_4T: * flagsp |= F_ARM_4T; break;
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case bfd_mach_arm_5: * flagsp |= F_ARM_5; break;
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case bfd_mach_arm_5T: * flagsp |= F_ARM_5; break; /* XXX - we do not have an F_ARM_5T */
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/* FIXME: we do not have F_ARM vaues greater than F_ARM_5. */
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case bfd_mach_arm_5T: * flagsp |= F_ARM_5; break;
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case bfd_mach_arm_5TE: * flagsp |= F_ARM_5; break;
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case bfd_mach_arm_XScale: * flagsp |= F_ARM_5; break;
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}
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return true;
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#endif
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@ -32,6 +32,7 @@ alpha*) targ_archs=bfd_alpha_arch ;;
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arm*) targ_archs=bfd_arm_arch ;;
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strongarm*) targ_archs=bfd_arm_arch ;;
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thumb*) targ_archs=bfd_arm_arch ;;
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xscale*) targ_archs=bfd_arm_arch ;;
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c30*) targ_archs=bfd_tic30_arch ;;
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c54x*) targ_archs=bfd_tic54x_arch ;;
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hppa*) targ_archs=bfd_hppa_arch ;;
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@ -182,6 +183,15 @@ case "${targ}" in
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targ_selvecs=armcoff_big_vec
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targ_underscore=yes
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;;
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xscale-*-elf)
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targ_defvec=bfd_elf32_littlearm_vec
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targ_selvecs=bfd_elf32_bigarm_vec
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;;
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xscale-*-coff)
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targ_defvec=armcoff_little_vec
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targ_selvecs=armcoff_big_vec
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targ_underscore=yes
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;;
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a29k-*-ebmon* | a29k-*-udi* | a29k-*-coff* | a29k-*-sym1* | \
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a29k-*-vxworks* | a29k-*-sysv*)
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@ -93,6 +93,7 @@ processors[] =
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{ bfd_mach_arm_4, "strongarm"},
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{ bfd_mach_arm_4, "strongarm110" },
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{ bfd_mach_arm_4, "strongarm1100" },
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{ bfd_mach_arm_XScale, "xscale" }
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};
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static boolean
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@ -135,7 +136,9 @@ static const bfd_arch_info_type arch_info_struct[] =
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N( bfd_mach_arm_4, "armv4", false, & arch_info_struct[5] ),
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N( bfd_mach_arm_4T, "armv4t", false, & arch_info_struct[6] ),
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N( bfd_mach_arm_5, "armv5", false, & arch_info_struct[7] ),
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N( bfd_mach_arm_5T, "armv5t", false, NULL )
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N( bfd_mach_arm_5T, "armv5t", false, & arch_info_struct[8] ),
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N( bfd_mach_arm_5TE, "armv5te", false, & arch_info_struct[9] ),
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N( bfd_mach_arm_XScale, "xscale", false, NULL )
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};
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const bfd_arch_info_type bfd_arm_arch =
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@ -1,3 +1,7 @@
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2000-11-24 Nick Clifton <nickc@redhat.com>
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* NEWS: Announce support for v5t, v5te and XScale.
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2000-11-22 Nick Clifton <nickc@redhat.com>
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* readelf.c (get_machine_name): Add EM_JAVELIN, EM_FIREPATH,
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@ -1,7 +1,10 @@
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-*- text -*-
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* Add --srec-len and --srec-forceS3 command line switch to objcopy. By Luciano
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Gemme.
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* Add support for ARM v5t and v5te architectures and Intel's XScale ARM
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extenstions.
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* Add --srec-len and --srec-forceS3 command line switch to objcopy.
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By Luciano Gemme.
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* Support for the MIPS32, by Anders Norlander.
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24
configure.in
24
configure.in
@ -628,12 +628,6 @@ case "${target}" in
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arm-*-oabi*)
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noconfigdirs="$noconfigdirs target-libgloss target-libffi"
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;;
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c4x-*-*)
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noconfigdirs="$noconfigdirs ${libstdcxx_version} target-libgloss target-libffi"
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;;
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c54x*-*-* | tic54x-*-*)
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noconfigdirs="$noconfigdirs ${libstdcxx_version} target-libgloss target-libffi gcc gdb newlib"
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;;
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thumb-*-coff)
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noconfigdirs="$noconfigdirs target-libgloss target-libffi"
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;;
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@ -655,12 +649,30 @@ case "${target}" in
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target_configdirs="${target_configdirs} target-bsp target-cygmon"
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fi
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;;
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xscale-*-elf)
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noconfigdirs="$noconfigdirs target-libgloss target-libffi"
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if [ x${is_cross_compiler} != xno ] ; then
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target_configdirs="${target_configdirs} target-bsp target-cygmon"
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fi
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;;
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xscale-*-coff)
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noconfigdirs="$noconfigdirs target-libgloss target-libffi"
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if [ x${is_cross_compiler} != xno ] ; then
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target_configdirs="${target_configdirs} target-bsp target-cygmon"
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fi
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;;
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thumb-*-pe)
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noconfigdirs="$noconfigdirs target-libgloss target-libffi"
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;;
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arm-*-riscix*)
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noconfigdirs="$noconfigdirs ld target-libgloss target-libffi"
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;;
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c4x-*-*)
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noconfigdirs="$noconfigdirs ${libstdcxx_version} target-libgloss target-libffi"
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;;
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c54x*-*-* | tic54x-*-*)
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noconfigdirs="$noconfigdirs ${libstdcxx_version} target-libgloss target-libffi gcc gdb newlib"
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;;
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d10v-*-*)
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noconfigdirs="$noconfigdirs ${libstdcxx_version} target-libgloss target-libffi"
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;;
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@ -1,3 +1,45 @@
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2000-11-24 Nick Clifton <nickc@redhat.com>
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* configure.in (xscale-elf): Add target.
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(xscale-coff): Add target.
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* configure: Regenerate.
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* config/tc-arm.c (ARM_EXT_V5E): New ARM architecture
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extenstion.
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(ARM_EXT_XSCALE): New ARM architecture extension.
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(ARM_LONGMUL): Rename to ARM_EXT_LONGMUL.
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(ARM_HALFWORD): Rename to ARM_EXT_HALFWORD.
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(ARM_THUMB): Rename to ARM_EXT_THUMB.
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(ARM_ARCH_V4): Remove processor from architecture.
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(ARM_ARCH_3M): New architecutre definition.
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(ARM_ARCH_V5TE): New architecutre definition.
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(ARM_ARCH_XSCALE): New architecutre definition.
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(CPU_DEFAULT): Allow to be defaulted to XScale.
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(atpcs): New boolean variable.
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(ldr_flags): Support 'd' flag for double word loads.
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(str_flags): Support 'd' flag for double word stored.
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(do_mia): New function.
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(do_mar): New function.
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(do_mra): New function.
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(do_pld): New function.
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(do_ldrd): New function.
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(do_blx): New function.
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(do_bkpt): New function.
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(do_clz): New function.
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(do_lstc2): New function.
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(do_cdp2): New function.
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(do_t_blx): New function.
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(do_t_bkpt): New function.
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(do_smla): New function.
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(do_smlal): New function.
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(do_smul): New function.
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(do_qadd): New function.
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(do_co_reg2c): New function.
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(LONGEST_INSN): Redefine to 7.
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* doc/c-arm.texi: Document -mxscale, -mmarmv5te and -matpcs
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command line switches.
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2000-11-22 Jim Wilson <wilson@redhat.com>
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* config/tc-ia64.c (pseudo_func): Add missing initializers.
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1437
gas/config/tc-arm.c
1437
gas/config/tc-arm.c
File diff suppressed because it is too large
Load Diff
341
gas/configure
vendored
341
gas/configure
vendored
File diff suppressed because it is too large
Load Diff
@ -117,6 +117,7 @@ changequote([,])dnl
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armb*) cpu_type=arm endian=little ;;
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armv*l) cpu_type=arm endian=little ;;
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armv*b) cpu_type=arm endian=big ;;
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xscale*) cpu_type=arm endian=little ;;
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strongarm*) cpu_type=arm endian=little ;;
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thumb*) cpu_type=arm endian=little ;;
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hppa*) cpu_type=hppa ;;
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@ -406,6 +407,8 @@ changequote([,])dnl
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strongarm-*-coff) fmt=coff ;;
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strongarm-*-elf) fmt=elf ;;
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xscale-*-coff) fmt=coff ;;
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xscale-*-elf) fmt=elf ;;
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tic30-*-*aout*) fmt=aout bfd_gas=yes ;;
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tic30-*-*coff*) fmt=coff bfd_gas=yes ;;
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@ -32,15 +32,18 @@
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@cindex @code{-marm} command line option, ARM
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@item -marm@code{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]}
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@itemx -mxscale
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This option specifies the target processor. The assembler will issue an
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error message if an attempt is made to assemble an instruction which
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will not execute on the target processor.
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@cindex @code{-marmv} command line option, ARM
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@item -marmv@code{[2|2a|3|3m|4|4t|5|5t]}
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@item -marmv@code{[2|2a|3|3m|4|4t|5|5t|5te]}
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This option specifies the target architecture. The assembler will issue
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an error message if an attempt is made to assemble an instruction which
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will not execute on the target architecture.
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The option @code{-marmv5te} specifies that v5t architecture should be
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used with the El Segundo extensions enabled.
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@cindex @code{-mthumb} command line option, ARM
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@item -mthumb
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@ -74,6 +77,14 @@ This option specifies that the output generated by the assembler should
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be marked as supporting the indicated version of the Arm Procedure.
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Calling Standard.
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@cindex @code{-matpcs} command line option, ARM
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@item -matpcs
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This option specifies that the output generated by the assembler should
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be marked as supporting the Arm/Thumb Procedure Calling Standard. If
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enabled this option will cause the assembler to create an empty
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debugging section in the object file called .arm.atpcs. Debuggers can
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use this to determine the ABI being used by.
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@cindex @code{-mapcs-float} command line option, ARM
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@item -mapcs-float
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This indicates the the floating point variant of the APCS should be
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@ -1,3 +1,11 @@
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2000-11-24 Nick Clifton <nickc@redhat.com>
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* arm.exp: Run tests for xscale as well as arm.
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Run xscale tests.
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* xscale.s: New file: XScale instruction tests.
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* xscale.d: New file: Expected XScale instruction results.
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2000-11-20 H.J. Lu <hjl@gnu.org>
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* gas/i386/intel.d: Add 3 "nop"s for the a.out assembler.
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@ -1,7 +1,7 @@
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#
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# Some ARM tests
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#
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if [istarget *arm*-*-*] then {
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if {[istarget *arm*-*-*] || [istarget "xscale-*-*"]} then {
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run_dump_test "inst"
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gas_test "arm3.s" "" $stdoptlist "Arm 3 instructions"
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@ -21,6 +21,8 @@ if [istarget *arm*-*-*] then {
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gas_test "immed.s" "" $stdoptlist "immediate expressions"
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gas_test "float.s" "" $stdoptlist "Core floating point instructions"
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run_dump_test "xscale"
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}
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# Not all arm targets are bi-endian, so only run this test on ones
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38
gas/testsuite/gas/arm/xscale.d
Normal file
38
gas/testsuite/gas/arm/xscale.d
Normal file
@ -0,0 +1,38 @@
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#objdump: -dr --prefix-addresses --show-raw-insn
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#name: XScale instructions
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#as: -mxscale -EL
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# Test the XScale instructions:
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.*: +file format .*arm.*
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Disassembly of section .text:
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00000000 <foo> ee201010 mia acc0, r0, r1
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00000004 <[^>]*> be20d01e mialt acc0, lr, sp
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00000008 <[^>]*> ee284012 miaph acc0, r2, r4
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0000000c <[^>]*> 1e286015 miaphne acc0, r5, r6
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00000010 <[^>]*> ee2c8017 miaBB acc0, r7, r8
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00000014 <[^>]*> ee2da019 miaBT acc0, r9, sl
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00000018 <[^>]*> ee2eb01c miaTB acc0, ip, fp
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0000001c <[^>]*> ee2f0010 miaTT acc0, r0, r0
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00000020 <[^>]*> ec411000 mar acc0, r1, r1
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00000024 <[^>]*> cc4c2000 margt acc0, r2, ip
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00000028 <[^>]*> ec543000 mra r3, r4, acc0
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0000002c <[^>]*> ec585000 mra r5, r8, acc0
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00000030 <[^>]*> f5d0f000 pld \[r0\]
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00000034 <[^>]*> f5d1f789 pld \[r1, #1929\]
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00000038 <[^>]*> f7d2f003 pld \[r2, r3\]
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0000003c <[^>]*> f754f285 pld \[r4, -r5, lsl #5\]
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00000040 <[^>]*> f456f456 pld \[r6\], -#1110
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00000044 <[^>]*> f6d7f008 pld \[r7\], r8
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00000048 <[^>]*> f659f06a pld \[r9\], -sl, rrx
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0000004c <[^>]*> e1c100d0 ldrd r0, \[r1\]
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00000050 <[^>]*> 01c327d8 ldreqd r2, \[r3, #120\]
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00000054 <[^>]*> b10540d6 ldrltd r4, \[r5, -r6\]
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00000058 <[^>]*> e16a88f9 strd r8, \[sl, -#137\]!
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0000005c <[^>]*> e1ac00fd strd r0, \[ip, sp\]!
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00000060 <[^>]*> 30ce21f0 strccd r2, \[lr\], #16
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00000064 <[^>]*> 708640f8 strvcd r4, \[r6\], r8
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00000068 <[^>]*> e5910000 ldr r0, \[r1\]
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0000006c <[^>]*> e5832000 str r2, \[r3\]
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00000070 <[^>]*> e321f011 msr CPSR_c, #17 ; 0x11
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40
gas/testsuite/gas/arm/xscale.s
Normal file
40
gas/testsuite/gas/arm/xscale.s
Normal file
@ -0,0 +1,40 @@
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.text
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.global foo
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foo:
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mia acc0, r0, r1
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mialt acc0, r14, r13
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miaph acc0, r2, r4
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miaphne acc0, r5, r6
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miaBB acc0, r7, r8
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miaBT acc0, r9, r10
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miaTB acc0, r12, r11
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miaTT acc0, r0, r0
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mar acc0, r1, r1
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margt acc0, r2, r12
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mra r3, r4, acc0
|
||||
mra r5, r8, acc0
|
||||
|
||||
pld [r0]
|
||||
pld [r1, #0x789]
|
||||
pld [r2, r3]
|
||||
pld [r4, -r5, lsl #5]
|
||||
pld [r6], #-0x456
|
||||
pld [r7], +r8
|
||||
pld [r9], -r10, RRX
|
||||
|
||||
ldrd r0, [r1]
|
||||
ldreqd r2, [r3, #0x78]
|
||||
ldrltd r4, [r5, -r6]
|
||||
strd r8, [r10,#-0x89]!
|
||||
strald r0, [r12, +r13]!
|
||||
strlod r2, [r14], #+0x010
|
||||
strvcd r4, [r6], r8
|
||||
|
||||
ldr r0, [r1]
|
||||
str r2, [r3]
|
||||
|
||||
msr cpsr_ctl, #0x11
|
||||
@ -1,3 +1,8 @@
|
||||
2000-11-24 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* configure.tgt (xscale-coff): Add target.
|
||||
(xscale-elf): Add target.
|
||||
|
||||
2000-11-24 Fred Fish <fnf@be.com>
|
||||
|
||||
* ldmain.c (main): Remove redundant init of config.make_executable
|
||||
|
||||
@ -178,6 +178,8 @@ thumb-epoc-pe) targ_emul=arm_epoc_pe ;
|
||||
targ_extra_ofiles="deffilep.o pe-dll.o" ;;
|
||||
thumb-*-pe) targ_emul=armpe ;
|
||||
targ_extra_ofiles="deffilep.o pe-dll.o" ;;
|
||||
xscale-*-coff) targ_emul=armcoff ;;
|
||||
xscale-*-elf) targ_emul=armelf ;;
|
||||
h8300-*-hms* | h8300-*-coff*)
|
||||
targ_emul=h8300; targ_extra_emuls="h8300h h8300s"
|
||||
;;
|
||||
|
||||
@ -1,3 +1,13 @@
|
||||
2000-11-24 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* arm-opc.h: Add new opcode formatting parameter 'B'.
|
||||
(arm_opcodes): Add XScale, v5, and v5te instructions.
|
||||
(thumb_opcodes): Add v5t instructions.
|
||||
|
||||
* arm-dis.c (print_insn_arm): Handle new 'B' format
|
||||
parameter.
|
||||
(print_insn_thumb): Decode BLX(1) instruction.
|
||||
|
||||
2000-11-21 Chris Demetriou <cgd@sibyte.com>
|
||||
|
||||
* mips-opc.c: Fix file header comment.
|
||||
|
||||
@ -421,6 +421,29 @@ print_insn_arm (pc, info, given)
|
||||
}
|
||||
break;
|
||||
|
||||
case 'B':
|
||||
/* Print ARM V5 BLX(1) address: pc+25 bits. */
|
||||
{
|
||||
bfd_vma address;
|
||||
bfd_vma offset = 0;
|
||||
|
||||
if (given & 0x00800000)
|
||||
/* Is signed, hi bits should be ones. */
|
||||
offset = (-1) ^ 0x00ffffff;
|
||||
|
||||
/* Offset is (SignExtend(offset field)<<2). */
|
||||
offset += given & 0x00ffffff;
|
||||
offset <<= 2;
|
||||
address = offset + pc + 8;
|
||||
|
||||
if (given & 0x01000000)
|
||||
/* H bit allows addressing to 2-byte boundaries. */
|
||||
address += 2;
|
||||
|
||||
info->print_address_func (address, info);
|
||||
}
|
||||
break;
|
||||
|
||||
case 'C':
|
||||
func (stream, "_");
|
||||
if (given & 0x80000)
|
||||
@ -648,6 +671,9 @@ print_insn_thumb (pc, info, given)
|
||||
info->bytes_per_chunk = 4;
|
||||
info->bytes_per_line = 4;
|
||||
|
||||
if ((given & 0x10000000) == 0)
|
||||
func (stream, "blx\t");
|
||||
else
|
||||
func (stream, "bl\t");
|
||||
|
||||
info->print_address_func (BDISP23 (given) * 2 + pc + 4, info);
|
||||
|
||||
@ -51,6 +51,7 @@ struct thumb_opcode
|
||||
%a print address for ldr/str instruction
|
||||
%s print address for ldr/str halfword/signextend instruction
|
||||
%b print branch destination
|
||||
%B print arm BLX(1) destination
|
||||
%A print address for ldc/stc/ldf/stf instruction
|
||||
%m print register mask for ldm/stm instruction
|
||||
%C print the PSR sub type.
|
||||
@ -75,7 +76,7 @@ Thumb specific format options:
|
||||
|
||||
static struct arm_opcode arm_opcodes[] =
|
||||
{
|
||||
/* ARM instructions */
|
||||
/* ARM instructions. */
|
||||
{0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
|
||||
{0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
|
||||
{0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
|
||||
@ -83,6 +84,59 @@ static struct arm_opcode arm_opcodes[] =
|
||||
{0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
|
||||
{0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
|
||||
{0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
|
||||
|
||||
/* XScale instructions. */
|
||||
{0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
|
||||
{0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
|
||||
{0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
|
||||
{0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
|
||||
{0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
|
||||
{0xf450f000, 0xfc70f000, "pld\t%a"},
|
||||
|
||||
/* V5 Instructions. */
|
||||
{0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
|
||||
{0xfa000000, 0xfe000000, "blx\t%B"},
|
||||
{0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
|
||||
{0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"},
|
||||
{0xfc100000, 0xfe100000, "ldc2%22'l\t%8-11d, cr%12-15d, %A"},
|
||||
{0xfc000000, 0xfe100000, "stc2%22'l\t%8-11d, cr%12-15d, %A"},
|
||||
{0xfe000000, 0xff000010, "cdp2\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
|
||||
{0xfe000010, 0xff100010, "mcr2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
|
||||
{0xfe100010, 0xff100010, "mrc2\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
|
||||
|
||||
/* V5E "El Segundo" Instructions. */
|
||||
{0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"},
|
||||
{0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"},
|
||||
{0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
|
||||
{0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
|
||||
{0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
|
||||
{0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
|
||||
|
||||
{0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
|
||||
{0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
|
||||
|
||||
{0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
|
||||
{0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
|
||||
{0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
|
||||
{0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
|
||||
|
||||
{0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"},
|
||||
{0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"},
|
||||
{0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"},
|
||||
{0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"},
|
||||
|
||||
{0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"},
|
||||
{0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"},
|
||||
|
||||
{0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"},
|
||||
{0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
|
||||
{0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"},
|
||||
{0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
|
||||
|
||||
{0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
|
||||
{0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
|
||||
|
||||
/* ARM Instructions. */
|
||||
{0x00000090, 0x0e100090, "str%c%6's%h\t%12-15r, %s"},
|
||||
{0x00100090, 0x0e100090, "ldr%c%6's%h\t%12-15r, %s"},
|
||||
{0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
|
||||
@ -174,10 +228,21 @@ static struct arm_opcode arm_opcodes[] =
|
||||
|
||||
static struct thumb_opcode thumb_opcodes[] =
|
||||
{
|
||||
/* Thumb instructions */
|
||||
{0x46C0, 0xFFFF, "nop\t\t\t(mov r8,r8)"}, /* format 5 instructions do not update the PSR */
|
||||
/* Thumb instructions. */
|
||||
|
||||
/* ARM V5 ISA extends Thumb. */
|
||||
{0xbe00, 0xff00, "bkpt\t%0-7x"},
|
||||
{0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */
|
||||
/* Note: this is BLX(2). BLX(1) is done in arm-dis.c/print_insn_thumb()
|
||||
as an extension of the special processing there for Thumb BL.
|
||||
BL and BLX(1) involve 2 successive 16-bit instructions, which must
|
||||
always appear together in the correct order. So, the empty
|
||||
string is put in this table, and the string interpreter takes <empty>
|
||||
to mean it has a pair of BL-ish instructions. */
|
||||
{0x46C0, 0xFFFF, "nop\t\t\t(mov r8, r8)"},
|
||||
/* Format 5 instructions do not update the PSR. */
|
||||
{0x1C00, 0xFFC0, "mov\t%0-2r, %3-5r\t\t(add %0-2r, %3-5r, #%6-8d)"},
|
||||
/* format 4 */
|
||||
/* Format 4. */
|
||||
{0x4000, 0xFFC0, "and\t%0-2r, %3-5r"},
|
||||
{0x4040, 0xFFC0, "eor\t%0-2r, %3-5r"},
|
||||
{0x4080, 0xFFC0, "lsl\t%0-2r, %3-5r"},
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user