RISC-V: Add load/store instructions for T-Head VECTOR vendor extension

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds load/store instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension are
documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	load/store instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VLBV): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.

include/opcode/riscv-opc.h

@@ -2648,6 +2648,39 @@
 #define MASK_TH_SYNC_IS 0xffffffff
 #define MATCH_TH_SYNC_S 0x0190000b
 #define MASK_TH_SYNC_S 0xffffffff
+/* Vendor-specific (T-Head) XTheadVector instructions.  */
+#define MATCH_TH_VLBV  0x10000007
+#define MASK_TH_VLBV   0xfdf0707f
+#define MATCH_TH_VLHV  0x10005007
+#define MASK_TH_VLHV   0xfdf0707f
+#define MATCH_TH_VLWV  0x10006007
+#define MASK_TH_VLWV   0xfdf0707f
+#define MATCH_TH_VLSBV    0x18000007
+#define MASK_TH_VLSBV     0xfc00707f
+#define MATCH_TH_VLSHV    0x18005007
+#define MASK_TH_VLSHV     0xfc00707f
+#define MATCH_TH_VLSWV    0x18006007
+#define MASK_TH_VLSWV     0xfc00707f
+#define MATCH_TH_VLXBV    0x1c000007
+#define MASK_TH_VLXBV     0xfc00707f
+#define MATCH_TH_VLXHV    0x1c005007
+#define MASK_TH_VLXHV     0xfc00707f
+#define MATCH_TH_VLXWV    0x1c006007
+#define MASK_TH_VLXWV     0xfc00707f
+#define MATCH_TH_VSUXBV   0x1c000027
+#define MASK_TH_VSUXBV    0xfc00707f
+#define MATCH_TH_VSUXHV   0x1c005027
+#define MASK_TH_VSUXHV    0xfc00707f
+#define MATCH_TH_VSUXWV   0x1c006027
+#define MASK_TH_VSUXWV    0xfc00707f
+#define MATCH_TH_VSUXEV   0x1c007027
+#define MASK_TH_VSUXEV    0xfc00707f
+#define MATCH_TH_VLBFFV  0x11000007
+#define MASK_TH_VLBFFV   0xfdf0707f
+#define MATCH_TH_VLHFFV  0x11005007
+#define MASK_TH_VLHFFV   0xfdf0707f
+#define MATCH_TH_VLWFFV  0x11006007
+#define MASK_TH_VLWFFV   0xfdf0707f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f