RISC-V: Always generate mapping symbols at the start of the sections.

Before figuring out the suppress rule of mapping symbol with architecture
(changed back to $x), always generate them at the start of the sections.

gas/
    * config/tc-riscv.c (need_arch_map_symbol): Removed.
    (riscv_mapping_state): Updated.
    (riscv_check_mapping_symbols): Updated.
    * testsuite/gas/riscv/mapping-non-arch.d: Removed.
    * testsuite/gas/riscv/mapping-non-arch.s: Likewise.
This commit is contained in:
Nelson Chu 2022-10-29 11:34:10 +08:00
parent 541b65e4bc
commit 0ce50fc900
3 changed files with 0 additions and 41 deletions

View File

@ -470,11 +470,6 @@ static char *expr_end;
#define OPCODE_MATCHES(OPCODE, OP) \
(((OPCODE) & MASK_##OP) == MATCH_##OP)
/* Indicate if .option directives do affect instructions. Set to true means
we need to add $x+arch at somewhere; Otherwise just add $x for instructions
should be enough. */
static bool need_arch_map_symbol = false;
/* Create a new mapping symbol for the transition to STATE. */
static void
@ -579,7 +574,6 @@ riscv_mapping_state (enum riscv_seg_mstate to_state,
S_GET_NAME (seg_arch_symbol) + 2) != 0)
{
reset_seg_arch_str = true;
need_arch_map_symbol = true;
}
else if (from_state == to_state)
return;
@ -634,13 +628,6 @@ riscv_check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED,
if (seginfo == NULL || seginfo->frchainP == NULL)
return;
/* If we don't set any .option arch directive, then the arch_map_symbol
in each segment must be the first instruction, and we don't need to
add $x+arch for them. */
if (!need_arch_map_symbol
&& seginfo->tc_segment_info_data.arch_map_symbol != 0)
S_SET_NAME (seginfo->tc_segment_info_data.arch_map_symbol, "$x");
for (fragp = seginfo->frchainP->frch_root;
fragp != NULL;
fragp = fragp->fr_next)

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@ -1,17 +0,0 @@
#as:
#source: mapping-non-arch.s
#objdump: --syms --special-syms
.*file format.*riscv.*
SYMBOL TABLE:
00+00 l d .text 00+00 .text
00+00 l d .data 00+00 .data
00+00 l d .bss 00+00 .bss
00+00 l .text 00+00 \$x
00+08 l .text 00+00 \$d
00+0c l .text 00+00 \$x
00+00 l d text.A 00+00 text.A
00+00 l text.A 00+00 \$x
00+02 l text.A 00+00 \$d
00+00 l d .riscv.attributes 00+00 .riscv.attributes

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@ -1,11 +0,0 @@
.attribute arch, "rv32i"
.option arch, +c
.text
addi a0, zero, 1
.align 3
.word 0x1
addi a0, zero, 2
.section text.A, "ax"
addi a0, zero, 3
.word 0x2