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aarch64: Mark PMSIDR_EL1 as read-only

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We were incorrectly allowing writes to PMSIDR_EL1, which is
a read-only register.
[https://developer.arm.com/documentation/ddi0595/2021-09/AArch64-Registers/PMSIDR-EL1--Sampling-Profiling-ID-Register?lang=en]

opcodes/
	* aarch64-opc.c (aarch64_sys_regs): Make pmsidr_el1 as F_REG_READ.

gas/
	* testsuite/gas/aarch64/msr.s: Remove write to pmsidr_el1.
	* testsuite/gas/aarch64/msr.d: Update accordingly.
	* testsuite/gas/aarch64/illegal-sysreg-2.s,
	* testsuite/gas/aarch64/illegal-sysreg-2.d,
	* testsuite/gas/aarch64/illegal-sysreg-2.l: New test.
This commit is contained in:
Richard Sandiford 2021-11-30 17:50:24 +00:00
parent 31a8056f2f
commit 1864b6578b
6 changed files with 9 additions and 4 deletions
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2
gas/testsuite/gas/aarch64/illegal-sysreg-2.d Normal file
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@ -0,0 +1,2 @@
#source: illegal-sysreg-2.s
#warning_output: illegal-sysreg-2.l

2
gas/testsuite/gas/aarch64/illegal-sysreg-2.l Normal file
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@ -0,0 +1,2 @@
.*: Assembler messages:
.*: Warning: specified register cannot be written to at operand 1 -- `msr pmsidr_el1,x0'

3
gas/testsuite/gas/aarch64/illegal-sysreg-2.s Normal file
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@ -0,0 +1,3 @@
/* Write to R/O system registers. */
.arch armv8.2-a+profile
msr pmsidr_el1, x0

3
gas/testsuite/gas/aarch64/msr.d
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@ -24,5 +24,4 @@ Disassembly of section \.text:
3c: d5300040 mrs x0, osdtrrx_el1
40: d5100340 msr osdtrtx_el1, x0
44: d5300340 mrs x0, osdtrtx_el1
48: d51899e0 msr pmsidr_el1, x0
4c: d53899e0 mrs x0, pmsidr_el1
48: d53899e0 mrs x0, pmsidr_el1

1
gas/testsuite/gas/aarch64/msr.s
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@ -47,5 +47,4 @@ func:
msr osdtrtx_el1, x0
mrs x0, osdtrtx_el1
msr pmsidr_el1, x0
mrs x0, pmsidr_el1

2
opcodes/aarch64-opc.c
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@ -4346,7 +4346,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
SR_PROFILE ("pmsfcr_el1", CPENC (3,0,C9,C9,4), 0),
SR_PROFILE ("pmsevfr_el1", CPENC (3,0,C9,C9,5), 0),
SR_PROFILE ("pmslatfr_el1", CPENC (3,0,C9,C9,6), 0),
SR_PROFILE ("pmsidr_el1", CPENC (3,0,C9,C9,7), 0),
SR_PROFILE ("pmsidr_el1", CPENC (3,0,C9,C9,7), F_REG_READ),
SR_PROFILE ("pmscr_el2", CPENC (3,4,C9,C9,0), 0),
SR_PROFILE ("pmscr_el12", CPENC (3,5,C9,C9,0), 0),
SR_CORE ("pmcr_el0", CPENC (3,3,C9,C12,0), 0),