opcodes/
* sparc-opc.c (asi_table): Add UltraSPARC and Niagara extended values. (prefetch_table): Add missing values. gas/ * config/tc-sparc.c (v9a_asr_table): Add missing 'stick' and 'stick_cmpr', and document ordering rules of table. (tc_gen_reloc): Accept BFD_RELOC_SPARC_PC22 and BFD_RELOC_SPARC_PC10. * doc/c-sparc.texi: New section on Sparc constants. Add documentation for %stick and %stick_cmpr. gas/testsuite/ * gas/sparc/pc2210.d: New file. * gas/sparc/pc2210.d: Likewise. * gas/sparc/sparc.exp: Run new %pc22/%pc10 relocation test.
This commit is contained in:
David S. Miller
parent
b863bf13fe
commit
1a6b486f73
@ -1,3 +1,13 @@
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2008-04-23 David S. Miller <davem@davemloft.net>
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* config/tc-sparc.c (v9a_asr_table): Add missing
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'stick' and 'stick_cmpr', and document ordering rules
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of table.
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(tc_gen_reloc): Accept BFD_RELOC_SPARC_PC22 and
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BFD_RELOC_SPARC_PC10.
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* doc/c-sparc.texi: New section on Sparc constants.
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Add documentation for %stick and %stick_cmpr.
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2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (md_assemble): Don't check SSE instructions
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@ -768,13 +768,16 @@ struct priv_reg_entry hpriv_reg_table[] =
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{"", -1}, /* End marker. */
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};
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/* v9a specific asrs. */
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/* v9a specific asrs. This table is ordered by initial
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letter, in reverse. */
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struct priv_reg_entry v9a_asr_table[] =
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{
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{"tick_cmpr", 23},
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{"sys_tick_cmpr", 25},
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{"sys_tick", 24},
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{"stick_cmpr", 25},
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{"stick", 24},
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{"softint", 22},
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{"set_softint", 20},
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{"pic", 17},
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@ -3398,6 +3401,8 @@ tc_gen_reloc (section, fixp)
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case BFD_RELOC_32_PCREL_S2:
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case BFD_RELOC_SPARC13:
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case BFD_RELOC_SPARC22:
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case BFD_RELOC_SPARC_PC22:
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case BFD_RELOC_SPARC_PC10:
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case BFD_RELOC_SPARC_BASE13:
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case BFD_RELOC_SPARC_WDISP16:
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case BFD_RELOC_SPARC_WDISP19:
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@ -121,6 +121,7 @@ for their UltraSPARC and Niagara line of processors.
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@menu
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* Sparc-Chars:: Special Characters
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* Sparc-Regs:: Register Names
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* Sparc-Constants:: Constant Names
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* Sparc-Relocs:: Relocations
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@end menu
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@ -185,10 +186,14 @@ processors:
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The tick compare register is referred to as @samp{%tick_cmpr}.
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@item
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The system tick register is referred to as @samp{%sys_tick}.
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The system tick register is referred to as @samp{%stick}. An alias,
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@samp{%sys_tick}, exists but is deprecated and should not be used
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by new software.
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@item
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The system tick compare register is referred to as @samp{%sys_tick_cmpr}.
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The system tick compare register is referred to as @samp{%stick_cmpr}.
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An alias, @samp{%sys_tick_cmpr}, exists but is deprecated and should
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not be used by new software.
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@item
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The software interrupt register is referred to as @samp{%softint}.
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@ -334,7 +339,138 @@ to as @samp{%hver}.
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@item
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The hyperprivileged system tick compare register is referred
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to as @samp{%hstick_cmpr}.
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to as @samp{%hstick_cmpr}. Note that there is no @samp{%hstick}
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register, the normal @samp{%stick} is used.
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@end itemize
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@node Sparc-Constants
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@subsection Constants
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@cindex Sparc constants
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@cindex constants, Sparc
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Several Sparc instructions take an immediate operand field for
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which mnemonic names exist. Two such examples are @samp{membar}
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and @samp{prefetch}. Another example are the set of V9
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memory access instruction that allow specification of an
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address space identifier.
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The @samp{membar} instruction specifies a memory barrier that is
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the defined by the operand which is a bitmask. The supported
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mask mnemonics are:
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@itemize @bullet
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@item
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@samp{#Sync} requests that all operations (including nonmemory
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reference operations) appearing prior to the @code{membar} must have
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been performed and the effects of any exceptions become visible before
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any instructions after the @code{membar} may be initiated. This
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corresponds to @code{membar} cmask field bit 2.
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@item
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@samp{#MemIssue} requests that all memory reference operations
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appearing prior to the @code{membar} must have been performed before
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any memory operation after the @code{membar} may be initiated. This
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corresponds to @code{membar} cmask field bit 1.
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@item
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@samp{#Lookaside} requests that a store appearing prior to the
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@code{membar} must complete before any load following the
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@code{membar} referencing the same address can be initiated. This
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corresponds to @code{membar} cmask field bit 0.
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@item
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@samp{#StoreStore} defines that the effects of all stores appearing
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prior to the @code{membar} instruction must be visible to all
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processors before the effect of any stores following the
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@code{membar}. Equivalent to the deprecated @code{stbar} instruction.
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This corresponds to @code{membar} mmask field bit 3.
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@item
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@samp{#LoadStore} defines all loads appearing prior to the
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@code{membar} instruction must have been performed before the effect
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of any stores following the @code{membar} is visible to any other
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processor. This corresponds to @code{membar} mmask field bit 2.
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@item
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@samp{#StoreLoad} defines that the effects of all stores appearing
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prior to the @code{membar} instruction must be visible to all
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processors before loads following the @code{membar} may be performed.
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This corresponds to @code{membar} mmask field bit 1.
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@item
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@samp{#LoadLoad} defines that all loads appearing prior to the
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@code{membar} instruction must have been performed before any loads
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following the @code{membar} may be performed. This corresponds to
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@code{membar} mmask field bit 0.
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@end itemize
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These values can be ored together, for example:
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@example
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membar #Sync
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membar #StoreLoad | #LoadLoad
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membar #StoreLoad | #StoreStore
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@end example
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The @code{prefetch} and @code{prefetcha} instructions take a prefetch
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function code. The following prefetch function code constant
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mnemonics are available:
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@itemize @bullet
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@item
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@samp{#n_reads} requests a prefetch for several reads, and corresponds
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to a prefetch function code of 0.
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@samp{#one_read} requests a prefetch for one read, and corresponds
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to a prefetch function code of 1.
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@samp{#n_writes} requests a prefetch for several writes (and possibly
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reads), and corresponds to a prefetch function code of 2.
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@samp{#one_write} requests a prefetch for one write, and corresponds
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to a prefetch function code of 3.
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@samp{#page} requests a prefetch page, and corresponds to a prefetch
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function code of 4.
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@samp{#invalidate} requests a prefetch invalidate, and corresponds to
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a prefetch function code of 16.
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@samp{#unified} requests a prefetch to the nearest unified cache, and
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corresponds to a prefetch function code of 17.
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@samp{#n_reads_strong} requests a strong prefetch for several reads,
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and corresponds to a prefetch function code of 20.
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@samp{#one_read_strong} requests a strong prefetch for one read,
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and corresponds to a prefetch function code of 21.
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@samp{#n_writes_strong} requests a strong prefetch for several writes,
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and corresponds to a prefetch function code of 22.
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@samp{#one_write_strong} requests a strong prefetch for one write,
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and corresponds to a prefetch function code of 23.
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Onle one prefetch code may be specified. Here are some examples:
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@example
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prefetch [%l0 + %l2], #one_read
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prefetch [%g2 + 8], #n_writes
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prefetcha [%g1] 0x8, #unified
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prefetcha [%o0 + 0x10] %asi, #n_reads
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@end example
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The actual behavior of a given prefetch function code is processor
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specific. If a processor does not implement a given prefetch
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function code, it will treat the prefetch instruction as a nop.
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For instructions that accept an immediate address space identifier,
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@code{@value{AS}} provides many mnemonics corresponding to
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V9 defined as well as UltraSPARC and Niagara extended values.
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For example, @samp{#ASI_P} and @samp{#ASI_BLK_INIT_QUAD_LDD_AIUS}.
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See the V9 and processor specific manuals for details.
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@end itemize
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@node Sparc-Relocs
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@ -1,3 +1,9 @@
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2008-04-23 David S. Miller <davem@davemloft.net>
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* gas/sparc/pc2210.d: New file.
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* gas/sparc/pc2210.d: Likewise.
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* gas/sparc/sparc.exp: Run new %pc22/%pc10 relocation test.
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2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/arch-10.d: Updated.
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13
gas/testsuite/gas/sparc/pc2210.d
Normal file
13
gas/testsuite/gas/sparc/pc2210.d
Normal file
@ -0,0 +1,13 @@
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#as: -Av7
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#objdump: -dr
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#name: pc2210
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.*: +file format .*sparc.*
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Disassembly of section .text:
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0+ <.text>:
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0: 13 00 00 00 sethi %hi\(0\), %o1
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0: R_SPARC_PC22 .data
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4: 92 12 60 00 mov %o1, %o1 ! 0 <.text>
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4: R_SPARC_PC10 .data
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6
gas/testsuite/gas/sparc/pc2210.s
Normal file
6
gas/testsuite/gas/sparc/pc2210.s
Normal file
@ -0,0 +1,6 @@
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# Test R_SPARC_PC22 and R_SPARC_PC10 relocations
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.data
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sym: .word 0
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.text
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sethi %pc22(sym), %o1
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or %o1, %pc10(sym), %o1
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@ -55,6 +55,7 @@ if [istarget sparc*-*-*] {
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run_dump_test "v9branch3"
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run_dump_test "v9branch4"
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run_dump_test "v9branch5"
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run_dump_test "pc2210"
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run_list_test "pr4587" ""
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}
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@ -1,3 +1,9 @@
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2008-04-23 David S. Miller <davem@davemloft.net>
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* sparc-opc.c (asi_table): Add UltraSPARC and Niagara
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extended values.
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(prefetch_table): Add missing values.
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2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (opcode_modifiers): Add NoAVX.
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@ -1899,9 +1899,134 @@ static arg asi_table[] =
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{ 0x89, "#ASI_SECONDARY_LITTLE" },
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{ 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" },
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{ 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" },
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/* These are UltraSPARC extensions. */
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/* FIXME: There are dozens of them. Not sure we want them all.
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Most are for kernel building but some are for vis type stuff. */
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/* These are UltraSPARC and Niagara extensions. */
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{ 0x14, "#ASI_PHYS_USE_EC" },
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{ 0x15, "#ASI_PHYS_BYPASS_EC_E" },
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{ 0x16, "#ASI_BLK_AIUP_4V" },
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{ 0x17, "#ASI_BLK_AIUS_4V" },
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{ 0x1c, "#ASI_PHYS_USE_EC_L" },
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{ 0x1d, "#ASI_PHYS_BYPASS_EC_E_L" },
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{ 0x1e, "#ASI_BLK_AIUP_L_4V" },
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{ 0x1f, "#ASI_BLK_AIUS_L_4V" },
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{ 0x20, "#ASI_SCRATCHPAD" },
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{ 0x21, "#ASI_MMU" },
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{ 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS" },
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{ 0x24, "#ASI_NUCLEUS_QUAD_LDD" },
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{ 0x25, "#ASI_QUEUE" },
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{ 0x26, "#ASI_QUAD_LDD_PHYS_4V" },
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{ 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L" },
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{ 0x30, "#ASI_PCACHE_DATA_STATUS" },
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{ 0x31, "#ASI_PCACHE_DATA" },
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{ 0x32, "#ASI_PCACHE_TAG" },
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{ 0x33, "#ASI_PCACHE_SNOOP_TAG" },
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{ 0x34, "#ASI_QUAD_LDD_PHYS" },
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{ 0x38, "#ASI_WCACHE_VALID_BITS" },
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{ 0x39, "#ASI_WCACHE_DATA" },
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{ 0x3a, "#ASI_WCACHE_TAG" },
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{ 0x3b, "#ASI_WCACHE_SNOOP_TAG" },
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{ 0x3c, "#ASI_QUAD_LDD_PHYS_L" },
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{ 0x40, "#ASI_SRAM_FAST_INIT" },
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{ 0x41, "#ASI_CORE_AVAILABLE" },
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{ 0x41, "#ASI_CORE_ENABLE_STAT" },
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{ 0x41, "#ASI_CORE_ENABLE" },
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{ 0x41, "#ASI_XIR_STEERING" },
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{ 0x41, "#ASI_CORE_RUNNING_RW" },
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{ 0x41, "#ASI_CORE_RUNNING_W1S" },
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{ 0x41, "#ASI_CORE_RUNNING_W1C" },
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{ 0x41, "#ASI_CORE_RUNNING_STAT" },
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{ 0x41, "#ASI_CMT_ERROR_STEERING" },
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{ 0x41, "#ASI_DCACHE_INVALIDATE" },
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{ 0x41, "#ASI_DCACHE_UTAG" },
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{ 0x41, "#ASI_DCACHE_SNOOP_TAG" },
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{ 0x42, "#ASI_DCACHE_INVALIDATE" },
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{ 0x43, "#ASI_DCACHE_UTAG" },
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{ 0x44, "#ASI_DCACHE_SNOOP_TAG" },
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{ 0x45, "#ASI_LSU_CONTROL_REG" },
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{ 0x45, "#ASI_DCU_CONTROL_REG" },
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{ 0x46, "#ASI_DCACHE_DATA" },
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{ 0x47, "#ASI_DCACHE_TAG" },
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{ 0x48, "#ASI_INTR_DISPATCH_STAT" },
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{ 0x49, "#ASI_INTR_RECEIVE" },
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{ 0x4a, "#ASI_UPA_CONFIG" },
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{ 0x4a, "#ASI_JBUS_CONFIG" },
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{ 0x4a, "#ASI_SAFARI_CONFIG" },
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{ 0x4a, "#ASI_SAFARI_ADDRESS" },
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{ 0x4b, "#ASI_ESTATE_ERROR_EN" },
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{ 0x4c, "#ASI_AFSR" },
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{ 0x4d, "#ASI_AFAR" },
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{ 0x4e, "#ASI_EC_TAG_DATA" },
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{ 0x50, "#ASI_IMMU" },
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{ 0x51, "#ASI_IMMU_TSB_8KB_PTR" },
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{ 0x52, "#ASI_IMMU_TSB_16KB_PTR" },
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{ 0x54, "#ASI_ITLB_DATA_IN" },
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{ 0x55, "#ASI_ITLB_DATA_ACCESS" },
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{ 0x56, "#ASI_ITLB_TAG_READ" },
|
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{ 0x57, "#ASI_IMMU_DEMAP" },
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{ 0x58, "#ASI_DMMU" },
|
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{ 0x59, "#ASI_DMMU_TSB_8KB_PTR" },
|
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{ 0x5a, "#ASI_DMMU_TSB_64KB_PTR" },
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{ 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR" },
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{ 0x5c, "#ASI_DTLB_DATA_IN" },
|
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{ 0x5d, "#ASI_DTLB_DATA_ACCESS" },
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{ 0x5e, "#ASI_DTLB_TAG_READ" },
|
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{ 0x5f, "#ASI_DMMU_DEMAP" },
|
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{ 0x60, "#ASI_IIU_INST_TRAP" },
|
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{ 0x63, "#ASI_INTR_ID" },
|
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{ 0x63, "#ASI_CORE_ID" },
|
||||
{ 0x63, "#ASI_CESR_ID" },
|
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{ 0x66, "#ASI_IC_INSTR" },
|
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{ 0x67, "#ASI_IC_TAG" },
|
||||
{ 0x68, "#ASI_IC_STAG" },
|
||||
{ 0x6e, "#ASI_IC_PRE_DECODE" },
|
||||
{ 0x6f, "#ASI_IC_NEXT_FIELD" },
|
||||
{ 0x6f, "#ASI_BRPRED_ARRAY" },
|
||||
{ 0x70, "#ASI_BLK_AIUP" },
|
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{ 0x71, "#ASI_BLK_AIUS" },
|
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{ 0x72, "#ASI_MCU_CTRL_REG" },
|
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{ 0x74, "#ASI_EC_DATA" },
|
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{ 0x75, "#ASI_EC_CTRL" },
|
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{ 0x76, "#ASI_EC_W" },
|
||||
{ 0x77, "#ASI_UDB_ERROR_W" },
|
||||
{ 0x77, "#ASI_UDB_CONTROL_W" },
|
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{ 0x77, "#ASI_INTR_W" },
|
||||
{ 0x77, "#ASI_INTR_DATAN_W" },
|
||||
{ 0x77, "#ASI_INTR_DISPATCH_W" },
|
||||
{ 0x78, "#ASI_BLK_AIUPL" },
|
||||
{ 0x79, "#ASI_BLK_AIUSL" },
|
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{ 0x7e, "#ASI_EC_R" },
|
||||
{ 0x7f, "#ASI_UDBH_ERROR_R" },
|
||||
{ 0x7f, "#ASI_UDBL_ERROR_R" },
|
||||
{ 0x7f, "#ASI_UDBH_CONTROL_R" },
|
||||
{ 0x7f, "#ASI_UDBL_CONTROL_R" },
|
||||
{ 0x7f, "#ASI_INTR_R" },
|
||||
{ 0x7f, "#ASI_INTR_DATAN_R" },
|
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{ 0xc0, "#ASI_PST8_P" },
|
||||
{ 0xc1, "#ASI_PST8_S" },
|
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{ 0xc2, "#ASI_PST16_P" },
|
||||
{ 0xc3, "#ASI_PST16_S" },
|
||||
{ 0xc4, "#ASI_PST32_P" },
|
||||
{ 0xc5, "#ASI_PST32_S" },
|
||||
{ 0xc8, "#ASI_PST8_PL" },
|
||||
{ 0xc9, "#ASI_PST8_SL" },
|
||||
{ 0xca, "#ASI_PST16_PL" },
|
||||
{ 0xcb, "#ASI_PST16_SL" },
|
||||
{ 0xcc, "#ASI_PST32_PL" },
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||||
{ 0xcd, "#ASI_PST32_SL" },
|
||||
{ 0xd0, "#ASI_FL8_P" },
|
||||
{ 0xd1, "#ASI_FL8_S" },
|
||||
{ 0xd2, "#ASI_FL16_P" },
|
||||
{ 0xd3, "#ASI_FL16_S" },
|
||||
{ 0xd8, "#ASI_FL8_PL" },
|
||||
{ 0xd9, "#ASI_FL8_SL" },
|
||||
{ 0xda, "#ASI_FL16_PL" },
|
||||
{ 0xdb, "#ASI_FL16_SL" },
|
||||
{ 0xe0, "#ASI_BLK_COMMIT_P", },
|
||||
{ 0xe1, "#ASI_BLK_COMMIT_S", },
|
||||
{ 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P" },
|
||||
{ 0xf0, "#ASI_BLK_P", },
|
||||
{ 0xf1, "#ASI_BLK_S", },
|
||||
{ 0xf8, "#ASI_BLK_PL", },
|
||||
{ 0xf9, "#ASI_BLK_SL", },
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
@ -1961,6 +2086,11 @@ static arg prefetch_table[] =
|
||||
{ 3, "#one_write" },
|
||||
{ 4, "#page" },
|
||||
{ 16, "#invalidate" },
|
||||
{ 17, "#unified", },
|
||||
{ 20, "#n_reads_strong", },
|
||||
{ 21, "#one_read_strong", },
|
||||
{ 22, "#n_writes_strong", },
|
||||
{ 23, "#one_write_strong", },
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user