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sim: msp430: invert sim_cpu storage

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This commit is contained in:
Mike Frysinger 2016-08-13 00:28:11 +08:00
parent 6780d3731e
commit 1c867d708c
3 changed files with 106 additions and 120 deletions
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210
sim/msp430/msp430-sim.c
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@ -36,32 +36,37 @@
static sim_cia static sim_cia
msp430_pc_fetch (SIM_CPU *cpu) msp430_pc_fetch (SIM_CPU *cpu)
{ {
return cpu->state.regs[0]; struct msp430_cpu_state *msp430_cpu = MSP430_SIM_CPU (cpu);
return msp430_cpu->regs[0];
} }
static void static void
msp430_pc_store (SIM_CPU *cpu, sim_cia newpc) msp430_pc_store (SIM_CPU *cpu, sim_cia newpc)
{ {
cpu->state.regs[0] = newpc; struct msp430_cpu_state *msp430_cpu = MSP430_SIM_CPU (cpu);
msp430_cpu->regs[0] = newpc;
} }
static int static int
msp430_reg_fetch (SIM_CPU *cpu, int regno, void *buf, int len) msp430_reg_fetch (SIM_CPU *cpu, int regno, void *buf, int len)
{ {
struct msp430_cpu_state *msp430_cpu = MSP430_SIM_CPU (cpu);
unsigned char *memory = buf; unsigned char *memory = buf;
if (0 <= regno && regno < 16) if (0 <= regno && regno < 16)
{ {
if (len == 2) if (len == 2)
{ {
int val = cpu->state.regs[regno]; int val = msp430_cpu->regs[regno];
memory[0] = val & 0xff; memory[0] = val & 0xff;
memory[1] = (val >> 8) & 0xff; memory[1] = (val >> 8) & 0xff;
return 0; return 0;
} }
else if (len == 4) else if (len == 4)
{ {
int val = cpu->state.regs[regno]; int val = msp430_cpu->regs[regno];
memory[0] = val & 0xff; memory[0] = val & 0xff;
memory[1] = (val >> 8) & 0xff; memory[1] = (val >> 8) & 0xff;
memory[2] = (val >> 16) & 0x0f; /* Registers are only 20 bits wide. */ memory[2] = (val >> 16) & 0x0f; /* Registers are only 20 bits wide. */
@ -78,19 +83,20 @@ msp430_reg_fetch (SIM_CPU *cpu, int regno, void *buf, int len)
static int static int
msp430_reg_store (SIM_CPU *cpu, int regno, const void *buf, int len) msp430_reg_store (SIM_CPU *cpu, int regno, const void *buf, int len)
{ {
struct msp430_cpu_state *msp430_cpu = MSP430_SIM_CPU (cpu);
const unsigned char *memory = buf; const unsigned char *memory = buf;
if (0 <= regno && regno < 16) if (0 <= regno && regno < 16)
{ {
if (len == 2) if (len == 2)
{ {
cpu->state.regs[regno] = (memory[1] << 8) | memory[0]; msp430_cpu->regs[regno] = (memory[1] << 8) | memory[0];
return len; return len;
} }
if (len == 4) if (len == 4)
{ {
cpu->state.regs[regno] = ((memory[2] << 16) & 0xf0000) msp430_cpu->regs[regno] = ((memory[2] << 16) & 0xf0000)
| (memory[1] << 8) | memory[0]; | (memory[1] << 8) | memory[0];
return len; return len;
} }
@ -99,12 +105,6 @@ msp430_reg_store (SIM_CPU *cpu, int regno, const void *buf, int len)
return -1; return -1;
} }
static inline void
msp430_initialize_cpu (SIM_DESC sd, SIM_CPU *cpu)
{
memset (&cpu->state, 0, sizeof (cpu->state));
}
SIM_DESC SIM_DESC
sim_open (SIM_OPEN_KIND kind, sim_open (SIM_OPEN_KIND kind,
struct host_callback_struct *callback, struct host_callback_struct *callback,
@ -112,6 +112,7 @@ sim_open (SIM_OPEN_KIND kind,
char * const *argv) char * const *argv)
{ {
SIM_DESC sd = sim_state_alloc (kind, callback); SIM_DESC sd = sim_state_alloc (kind, callback);
struct msp430_cpu_state *msp430_cpu;
char c; char c;
/* Initialise the simulator. */ /* Initialise the simulator. */
@ -119,7 +120,8 @@ sim_open (SIM_OPEN_KIND kind,
/* Set default options before parsing user options. */ /* Set default options before parsing user options. */
current_target_byte_order = BFD_ENDIAN_LITTLE; current_target_byte_order = BFD_ENDIAN_LITTLE;
if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK) if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct msp430_cpu_state))
!= SIM_RC_OK)
{ {
sim_state_free (sd); sim_state_free (sd);
return 0; return 0;
@ -137,22 +139,22 @@ sim_open (SIM_OPEN_KIND kind,
return 0; return 0;
} }
CPU_PC_FETCH (MSP430_CPU (sd)) = msp430_pc_fetch; CPU_PC_FETCH (STATE_CPU (sd, 0)) = msp430_pc_fetch;
CPU_PC_STORE (MSP430_CPU (sd)) = msp430_pc_store; CPU_PC_STORE (STATE_CPU (sd, 0)) = msp430_pc_store;
CPU_REG_FETCH (MSP430_CPU (sd)) = msp430_reg_fetch; CPU_REG_FETCH (STATE_CPU (sd, 0)) = msp430_reg_fetch;
CPU_REG_STORE (MSP430_CPU (sd)) = msp430_reg_store; CPU_REG_STORE (STATE_CPU (sd, 0)) = msp430_reg_store;
/* Allocate memory if none specified by user. /* Allocate memory if none specified by user.
Note - these values match the memory regions in the libgloss/msp430/msp430[xl]-sim.ld scripts. */ Note - these values match the memory regions in the libgloss/msp430/msp430[xl]-sim.ld scripts. */
if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x2, 1) == 0) if (sim_core_read_buffer (sd, STATE_CPU (sd, 0), read_map, &c, 0x2, 1) == 0)
sim_do_commandf (sd, "memory-region 0,0x20"); /* Needed by the GDB testsuite. */ sim_do_commandf (sd, "memory-region 0,0x20"); /* Needed by the GDB testsuite. */
if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x500, 1) == 0) if (sim_core_read_buffer (sd, STATE_CPU (sd, 0), read_map, &c, 0x500, 1) == 0)
sim_do_commandf (sd, "memory-region 0x500,0xfac0"); /* RAM and/or ROM */ sim_do_commandf (sd, "memory-region 0x500,0xfac0"); /* RAM and/or ROM */
if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0xfffe, 1) == 0) if (sim_core_read_buffer (sd, STATE_CPU (sd, 0), read_map, &c, 0xfffe, 1) == 0)
sim_do_commandf (sd, "memory-region 0xffc0,0x40"); /* VECTORS. */ sim_do_commandf (sd, "memory-region 0xffc0,0x40"); /* VECTORS. */
if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x10000, 1) == 0) if (sim_core_read_buffer (sd, STATE_CPU (sd, 0), read_map, &c, 0x10000, 1) == 0)
sim_do_commandf (sd, "memory-region 0x10000,0x80000"); /* HIGH FLASH RAM. */ sim_do_commandf (sd, "memory-region 0x10000,0x80000"); /* HIGH FLASH RAM. */
if (sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, &c, 0x90000, 1) == 0) if (sim_core_read_buffer (sd, STATE_CPU (sd, 0), read_map, &c, 0x90000, 1) == 0)
sim_do_commandf (sd, "memory-region 0x90000,0x70000"); /* HIGH ROM. */ sim_do_commandf (sd, "memory-region 0x90000,0x70000"); /* HIGH ROM. */
/* Check for/establish the a reference program image. */ /* Check for/establish the a reference program image. */
@ -177,12 +179,12 @@ sim_open (SIM_OPEN_KIND kind,
/* CPU specific initialization. */ /* CPU specific initialization. */
assert (MAX_NR_PROCESSORS == 1); assert (MAX_NR_PROCESSORS == 1);
msp430_initialize_cpu (sd, MSP430_CPU (sd));
MSP430_CPU (sd)->state.cio_breakpoint = trace_sym_value (sd, "C$$IO$$"); msp430_cpu = MSP430_SIM_CPU (STATE_CPU (sd, 0));
MSP430_CPU (sd)->state.cio_buffer = trace_sym_value (sd, "__CIOBUF__"); msp430_cpu->cio_breakpoint = trace_sym_value (sd, "C$$IO$$");
if (MSP430_CPU (sd)->state.cio_buffer == -1) msp430_cpu->cio_buffer = trace_sym_value (sd, "__CIOBUF__");
MSP430_CPU (sd)->state.cio_buffer = trace_sym_value (sd, "_CIOBUF_"); if (msp430_cpu->cio_buffer == -1)
msp430_cpu->cio_buffer = trace_sym_value (sd, "_CIOBUF_");
return sd; return sd;
} }
@ -198,15 +200,15 @@ sim_create_inferior (SIM_DESC sd,
int new_pc; int new_pc;
/* Set the PC to the default reset vector if available. */ /* Set the PC to the default reset vector if available. */
c = sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, resetv, 0xfffe, 2); c = sim_core_read_buffer (sd, STATE_CPU (sd, 0), read_map, resetv, 0xfffe, 2);
new_pc = resetv[0] + 256 * resetv[1]; new_pc = resetv[0] + 256 * resetv[1];
/* If the reset vector isn't initialized, then use the ELF entry. */ /* If the reset vector isn't initialized, then use the ELF entry. */
if (abfd != NULL && !new_pc) if (abfd != NULL && !new_pc)
new_pc = bfd_get_start_address (abfd); new_pc = bfd_get_start_address (abfd);
sim_pc_set (MSP430_CPU (sd), new_pc); sim_pc_set (STATE_CPU (sd, 0), new_pc);
msp430_pc_store (MSP430_CPU (sd), new_pc); msp430_pc_store (STATE_CPU (sd, 0), new_pc);
return SIM_RC_OK; return SIM_RC_OK;
} }
@ -224,12 +226,12 @@ msp430_getbyte (void *vld)
char buf[1]; char buf[1];
SIM_DESC sd = ld->sd; SIM_DESC sd = ld->sd;
sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, ld->gb_addr, 1); sim_core_read_buffer (sd, STATE_CPU (sd, 0), read_map, buf, ld->gb_addr, 1);
ld->gb_addr ++; ld->gb_addr ++;
return buf[0]; return buf[0];
} }
#define REG(N) MSP430_CPU (sd)->state.regs[(N)] #define REG(N) MSP430_SIM_CPU (STATE_CPU (sd, 0))->regs[N]
#define PC REG(MSR_PC) #define PC REG(MSR_PC)
#define SP REG(MSR_SP) #define SP REG(MSR_SP)
#define SR REG(MSR_SR) #define SR REG(MSR_SR)
@ -244,14 +246,14 @@ register_names[] =
static void static void
trace_reg_put (SIM_DESC sd, int n, unsigned int v) trace_reg_put (SIM_DESC sd, int n, unsigned int v)
{ {
TRACE_REGISTER (MSP430_CPU (sd), "PUT: %#x -> %s", v, register_names[n]); TRACE_REGISTER (STATE_CPU (sd, 0), "PUT: %#x -> %s", v, register_names[n]);
REG (n) = v; REG (n) = v;
} }
static unsigned int static unsigned int
trace_reg_get (SIM_DESC sd, int n) trace_reg_get (SIM_DESC sd, int n)
{ {
TRACE_REGISTER (MSP430_CPU (sd), "GET: %s -> %#x", register_names[n], REG (n)); TRACE_REGISTER (STATE_CPU (sd, 0), "GET: %s -> %#x", register_names[n], REG (n));
return REG (n); return REG (n);
} }
@ -326,16 +328,16 @@ get_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n)
switch (opc->size) switch (opc->size)
{ {
case 8: case 8:
sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 1); sim_core_read_buffer (sd, STATE_CPU (sd, 0), read_map, buf, addr, 1);
rv = buf[0]; rv = buf[0];
break; break;
case 16: case 16:
sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 2); sim_core_read_buffer (sd, STATE_CPU (sd, 0), read_map, buf, addr, 2);
rv = buf[0] | (buf[1] << 8); rv = buf[0] | (buf[1] << 8);
break; break;
case 20: case 20:
case 32: case 32:
sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, addr, 4); sim_core_read_buffer (sd, STATE_CPU (sd, 0), read_map, buf, addr, 4);
rv = buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24); rv = buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24);
break; break;
default: default:
@ -432,7 +434,7 @@ get_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n)
} }
} }
TRACE_MEMORY (MSP430_CPU (sd), "GET: [%#x].%d -> %#x", addr, opc->size, TRACE_MEMORY (STATE_CPU (sd, 0), "GET: [%#x].%d -> %#x", addr, opc->size,
rv); rv);
break; break;
@ -525,7 +527,7 @@ put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val)
} }
addr &= 0xfffff; addr &= 0xfffff;
TRACE_MEMORY (MSP430_CPU (sd), "PUT: [%#x].%d <- %#x", addr, opc->size, TRACE_MEMORY (STATE_CPU (sd, 0), "PUT: [%#x].%d <- %#x", addr, opc->size,
val); val);
#if 0 #if 0
/* Hack - MSP430X5438 serial port transmit register. */ /* Hack - MSP430X5438 serial port transmit register. */
@ -685,12 +687,12 @@ put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val)
{ {
case 8: case 8:
buf[0] = val; buf[0] = val;
sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 1); sim_core_write_buffer (sd, STATE_CPU (sd, 0), write_map, buf, addr, 1);
break; break;
case 16: case 16:
buf[0] = val; buf[0] = val;
buf[1] = val >> 8; buf[1] = val >> 8;
sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 2); sim_core_write_buffer (sd, STATE_CPU (sd, 0), write_map, buf, addr, 2);
break; break;
case 20: case 20:
case 32: case 32:
@ -698,7 +700,7 @@ put_op (SIM_DESC sd, MSP430_Opcode_Decoded *opc, int n, int val)
buf[1] = val >> 8; buf[1] = val >> 8;
buf[2] = val >> 16; buf[2] = val >> 16;
buf[3] = val >> 24; buf[3] = val >> 24;
sim_core_write_buffer (sd, MSP430_CPU (sd), write_map, buf, addr, 4); sim_core_write_buffer (sd, STATE_CPU (sd, 0), write_map, buf, addr, 4);
break; break;
default: default:
assert (! opc->size); assert (! opc->size);
@ -787,7 +789,8 @@ msp430_cio (SIM_DESC sd)
{ {
/* A block of data at __CIOBUF__ describes the I/O operation to /* A block of data at __CIOBUF__ describes the I/O operation to
perform. */ perform. */
sim_cpu *cpu = STATE_CPU (sd, 0);
struct msp430_cpu_state *msp430_cpu = MSP430_SIM_CPU (cpu);
unsigned char raw_parms[13]; unsigned char raw_parms[13];
unsigned char parms[8]; unsigned char parms[8];
long length; long length;
@ -796,16 +799,12 @@ msp430_cio (SIM_DESC sd)
long ret_buflen = 0; long ret_buflen = 0;
long fd, addr, len, rv; long fd, addr, len, rv;
sim_core_read_buffer (sd, MSP430_CPU (sd), 0, parms, sim_core_read_buffer (sd, cpu, 0, parms, msp430_cpu->cio_buffer, 5);
MSP430_CPU (sd)->state.cio_buffer, 5);
length = CIO_I (0); length = CIO_I (0);
command = parms[2]; command = parms[2];
sim_core_read_buffer (sd, MSP430_CPU (sd), 0, parms, sim_core_read_buffer (sd, cpu, 0, parms, msp430_cpu->cio_buffer + 3, 8);
MSP430_CPU (sd)->state.cio_buffer + 3, 8); sim_core_read_buffer (sd, cpu, 0, buffer, msp430_cpu->cio_buffer + 11, length);
sim_core_read_buffer (sd, MSP430_CPU (sd), 0, buffer,
MSP430_CPU (sd)->state.cio_buffer + 11, length);
switch (command) switch (command)
{ {
@ -820,11 +819,10 @@ msp430_cio (SIM_DESC sd)
break; break;
} }
sim_core_write_buffer (sd, MSP430_CPU (sd), 0, parms, sim_core_write_buffer (sd, cpu, 0, parms, msp430_cpu->cio_buffer + 4, 8);
MSP430_CPU (sd)->state.cio_buffer + 4, 8);
if (ret_buflen) if (ret_buflen)
sim_core_write_buffer (sd, MSP430_CPU (sd), 0, buffer, sim_core_write_buffer (sd, cpu, 0, buffer, msp430_cpu->cio_buffer + 12,
MSP430_CPU (sd)->state.cio_buffer + 12, ret_buflen); ret_buflen);
} }
#define SRC get_op (sd, opcode, 1) #define SRC get_op (sd, opcode, 1)
@ -836,7 +834,7 @@ msp430_cio (SIM_DESC sd)
int s1 = DSRC; \ int s1 = DSRC; \
int s2 = SRC; \ int s2 = SRC; \
int result = s1 OP s2 MORE; \ int result = s1 OP s2 MORE; \
TRACE_ALU (MSP430_CPU (sd), "ALU: %#x %s %#x %s = %#x", s1, SOP, \ TRACE_ALU (STATE_CPU (sd, 0), "ALU: %#x %s %#x %s = %#x", s1, SOP, \
s2, #MORE, result); \ s2, #MORE, result); \
DEST (result); \ DEST (result); \
} }
@ -900,10 +898,10 @@ do_flags (SIM_DESC sd,
new_f = f | (new_f & opcode->flags_set); new_f = f | (new_f & opcode->flags_set);
if (SR != new_f) if (SR != new_f)
TRACE_ALU (MSP430_CPU (sd), "FLAGS: %s -> %s", flags2string (SR), TRACE_ALU (STATE_CPU (sd, 0), "FLAGS: %s -> %s", flags2string (SR),
flags2string (new_f)); flags2string (new_f));
else else
TRACE_ALU (MSP430_CPU (sd), "FLAGS: %s", flags2string (new_f)); TRACE_ALU (STATE_CPU (sd, 0), "FLAGS: %s", flags2string (new_f));
SR = new_f; SR = new_f;
} }
@ -966,6 +964,9 @@ cond_string (int cond)
static int static int
maybe_perform_syscall (SIM_DESC sd, int call_addr) maybe_perform_syscall (SIM_DESC sd, int call_addr)
{ {
sim_cpu *cpu = STATE_CPU (sd, 0);
struct msp430_cpu_state *msp430_cpu = MSP430_SIM_CPU (cpu);
if (call_addr == 0x00160) if (call_addr == 0x00160)
{ {
int i; int i;
@ -974,13 +975,13 @@ maybe_perform_syscall (SIM_DESC sd, int call_addr)
{ {
if (i % 4 == 0) if (i % 4 == 0)
fprintf (stderr, "\t"); fprintf (stderr, "\t");
fprintf (stderr, "R%-2d %05x ", i, MSP430_CPU (sd)->state.regs[i]); fprintf (stderr, "R%-2d %05x ", i, msp430_cpu->regs[i]);
if (i % 4 == 3) if (i % 4 == 3)
{ {
int sp = SP + (3 - (i / 4)) * 2; int sp = SP + (3 - (i / 4)) * 2;
unsigned char buf[2]; unsigned char buf[2];
sim_core_read_buffer (sd, MSP430_CPU (sd), read_map, buf, sp, 2); sim_core_read_buffer (sd, cpu, read_map, buf, sp, 2);
fprintf (stderr, "\tSP%+d: %04x", sp - SP, fprintf (stderr, "\tSP%+d: %04x", sp - SP,
buf[0] + buf[1] * 256); buf[0] + buf[1] * 256);
@ -1012,22 +1013,21 @@ maybe_perform_syscall (SIM_DESC sd, int call_addr)
See slaa534.pdf distributed by TI. */ See slaa534.pdf distributed by TI. */
if (syscall_num == 2) if (syscall_num == 2)
{ {
arg1 = MSP430_CPU (sd)->state.regs[12]; arg1 = msp430_cpu->regs[12];
arg2 = mem_get_val (sd, SP, 16); arg2 = mem_get_val (sd, SP, 16);
arg3 = mem_get_val (sd, SP + 2, 16); arg3 = mem_get_val (sd, SP + 2, 16);
arg4 = mem_get_val (sd, SP + 4, 16); arg4 = mem_get_val (sd, SP + 4, 16);
} }
else else
{ {
arg1 = MSP430_CPU (sd)->state.regs[12]; arg1 = msp430_cpu->regs[12];
arg2 = MSP430_CPU (sd)->state.regs[13]; arg2 = msp430_cpu->regs[13];
arg3 = MSP430_CPU (sd)->state.regs[14]; arg3 = msp430_cpu->regs[14];
arg4 = MSP430_CPU (sd)->state.regs[15]; arg4 = msp430_cpu->regs[15];
} }
MSP430_CPU (sd)->state.regs[12] = sim_syscall (MSP430_CPU (sd), msp430_cpu->regs[12] = sim_syscall (cpu, syscall_num, arg1, arg2, arg3,
syscall_num, arg1, arg2, arg4);
arg3, arg4);
return 1; return 1;
} }
@ -1037,6 +1037,8 @@ maybe_perform_syscall (SIM_DESC sd, int call_addr)
static void static void
msp430_step_once (SIM_DESC sd) msp430_step_once (SIM_DESC sd)
{ {
sim_cpu *cpu = STATE_CPU (sd, 0);
struct msp430_cpu_state *msp430_cpu = MSP430_SIM_CPU (cpu);
Get_Byte_Local_Data ld; Get_Byte_Local_Data ld;
unsigned char buf[100]; unsigned char buf[100];
int i; int i;
@ -1059,32 +1061,27 @@ msp430_step_once (SIM_DESC sd)
if (opcode_pc < 0x10) if (opcode_pc < 0x10)
{ {
fprintf (stderr, "Fault: PC(%#x) is less than 0x10\n", opcode_pc); fprintf (stderr, "Fault: PC(%#x) is less than 0x10\n", opcode_pc);
sim_engine_halt (sd, MSP430_CPU (sd), NULL, sim_engine_halt (sd, cpu, NULL, msp430_cpu->regs[0], sim_exited, -1);
MSP430_CPU (sd)->state.regs[0],
sim_exited, -1);
return; return;
} }
if (PC == MSP430_CPU (sd)->state.cio_breakpoint if (PC == msp430_cpu->cio_breakpoint && STATE_OPEN_KIND (sd) != SIM_OPEN_DEBUG)
&& STATE_OPEN_KIND (sd) != SIM_OPEN_DEBUG)
msp430_cio (sd); msp430_cio (sd);
ld.sd = sd; ld.sd = sd;
ld.gb_addr = PC; ld.gb_addr = PC;
opsize = msp430_decode_opcode (MSP430_CPU (sd)->state.regs[0], opsize = msp430_decode_opcode (msp430_cpu->regs[0], opcode, msp430_getbyte,
opcode, msp430_getbyte, &ld); &ld);
PC += opsize; PC += opsize;
if (opsize <= 0) if (opsize <= 0)
{ {
fprintf (stderr, "Fault: undecodable opcode at %#x\n", opcode_pc); fprintf (stderr, "Fault: undecodable opcode at %#x\n", opcode_pc);
sim_engine_halt (sd, MSP430_CPU (sd), NULL, sim_engine_halt (sd, cpu, NULL, msp430_cpu->regs[0], sim_exited, -1);
MSP430_CPU (sd)->state.regs[0],
sim_exited, -1);
return; return;
} }
if (opcode->repeat_reg) if (opcode->repeat_reg)
n_repeats = (MSP430_CPU (sd)->state.regs[opcode->repeats] & 0x000f) + 1; n_repeats = (msp430_cpu->regs[opcode->repeats] & 0x000f) + 1;
else else
n_repeats = opcode->repeats + 1; n_repeats = opcode->repeats + 1;
@ -1103,11 +1100,11 @@ msp430_step_once (SIM_DESC sd)
break; break;
} }
if (TRACE_ANY_P (MSP430_CPU (sd))) if (TRACE_ANY_P (cpu))
trace_prefix (sd, MSP430_CPU (sd), NULL_CIA, opcode_pc, trace_prefix (sd, cpu, NULL_CIA, opcode_pc, TRACE_LINENUM_P (cpu), NULL,
TRACE_LINENUM_P (MSP430_CPU (sd)), NULL, 0, " "); 0, " ");
TRACE_DISASM (MSP430_CPU (sd), opcode_pc); TRACE_DISASM (cpu, opcode_pc);
carry_to_use = 0; carry_to_use = 0;
switch (opcode->id) switch (opcode->id)
@ -1127,10 +1124,8 @@ msp430_step_once (SIM_DESC sd)
{ {
/* This is the designated software breakpoint instruction. */ /* This is the designated software breakpoint instruction. */
PC -= opsize; PC -= opsize;
sim_engine_halt (sd, MSP430_CPU (sd), NULL, sim_engine_halt (sd, cpu, NULL, msp430_cpu->regs[0], sim_stopped,
MSP430_CPU (sd)->state.regs[0], SIM_SIGTRAP);
sim_stopped, SIM_SIGTRAP);
} }
else else
{ {
@ -1152,7 +1147,7 @@ msp430_step_once (SIM_DESC sd)
s2 = SX (u2); s2 = SX (u2);
uresult = u1 + u2 + carry_to_use; uresult = u1 + u2 + carry_to_use;
result = s1 + s2 + carry_to_use; result = s1 + s2 + carry_to_use;
TRACE_ALU (MSP430_CPU (sd), "ADDC: %#x + %#x + %d = %#x", TRACE_ALU (cpu, "ADDC: %#x + %#x + %d = %#x",
u1, u2, carry_to_use, uresult); u1, u2, carry_to_use, uresult);
DEST (result); DEST (result);
FLAGS (result, uresult != ZX (uresult)); FLAGS (result, uresult != ZX (uresult));
@ -1168,8 +1163,7 @@ msp430_step_once (SIM_DESC sd)
s2 = SX (u2); s2 = SX (u2);
uresult = u1 + u2; uresult = u1 + u2;
result = s1 + s2; result = s1 + s2;
TRACE_ALU (MSP430_CPU (sd), "ADD: %#x + %#x = %#x", TRACE_ALU (cpu, "ADD: %#x + %#x = %#x", u1, u2, uresult);
u1, u2, uresult);
DEST (result); DEST (result);
FLAGS (result, uresult != ZX (uresult)); FLAGS (result, uresult != ZX (uresult));
} }
@ -1185,7 +1179,7 @@ msp430_step_once (SIM_DESC sd)
s2 = SX (u2); s2 = SX (u2);
uresult = ZX (~u2) + u1 + carry_to_use; uresult = ZX (~u2) + u1 + carry_to_use;
result = s1 - s2 + (carry_to_use - 1); result = s1 - s2 + (carry_to_use - 1);
TRACE_ALU (MSP430_CPU (sd), "SUBC: %#x - %#x + %d = %#x", TRACE_ALU (cpu, "SUBC: %#x - %#x + %d = %#x",
u1, u2, carry_to_use, uresult); u1, u2, carry_to_use, uresult);
DEST (result); DEST (result);
FLAGS (result, uresult != ZX (uresult)); FLAGS (result, uresult != ZX (uresult));
@ -1201,7 +1195,7 @@ msp430_step_once (SIM_DESC sd)
s2 = SX (u2); s2 = SX (u2);
uresult = ZX (~u2) + u1 + 1; uresult = ZX (~u2) + u1 + 1;
result = SX (uresult); result = SX (uresult);
TRACE_ALU (MSP430_CPU (sd), "SUB: %#x - %#x = %#x", TRACE_ALU (cpu, "SUB: %#x - %#x = %#x",
u1, u2, uresult); u1, u2, uresult);
DEST (result); DEST (result);
FLAGS (result, uresult != ZX (uresult)); FLAGS (result, uresult != ZX (uresult));
@ -1217,7 +1211,7 @@ msp430_step_once (SIM_DESC sd)
s2 = SX (u2); s2 = SX (u2);
uresult = ZX (~u2) + u1 + 1; uresult = ZX (~u2) + u1 + 1;
result = s1 - s2; result = s1 - s2;
TRACE_ALU (MSP430_CPU (sd), "CMP: %#x - %#x = %x", TRACE_ALU (cpu, "CMP: %#x - %#x = %x",
u1, u2, uresult); u1, u2, uresult);
FLAGS (result, uresult != ZX (uresult)); FLAGS (result, uresult != ZX (uresult));
} }
@ -1231,7 +1225,7 @@ msp430_step_once (SIM_DESC sd)
u2 = SRC; u2 = SRC;
uresult = bcd_to_binary (u1) + bcd_to_binary (u2) + carry_to_use; uresult = bcd_to_binary (u1) + bcd_to_binary (u2) + carry_to_use;
result = binary_to_bcd (uresult); result = binary_to_bcd (uresult);
TRACE_ALU (MSP430_CPU (sd), "DADD: %#x + %#x + %d = %#x", TRACE_ALU (cpu, "DADD: %#x + %#x + %d = %#x",
u1, u2, carry_to_use, result); u1, u2, carry_to_use, result);
DEST (result); DEST (result);
FLAGS (result, uresult > ((opcode->size == 8) ? 99 : 9999)); FLAGS (result, uresult > ((opcode->size == 8) ? 99 : 9999));
@ -1244,7 +1238,7 @@ msp430_step_once (SIM_DESC sd)
u1 = DSRC; u1 = DSRC;
u2 = SRC; u2 = SRC;
uresult = u1 & u2; uresult = u1 & u2;
TRACE_ALU (MSP430_CPU (sd), "AND: %#x & %#x = %#x", TRACE_ALU (cpu, "AND: %#x & %#x = %#x",
u1, u2, uresult); u1, u2, uresult);
DEST (uresult); DEST (uresult);
FLAGS (uresult, uresult != 0); FLAGS (uresult, uresult != 0);
@ -1257,7 +1251,7 @@ msp430_step_once (SIM_DESC sd)
u1 = DSRC; u1 = DSRC;
u2 = SRC; u2 = SRC;
uresult = u1 & u2; uresult = u1 & u2;
TRACE_ALU (MSP430_CPU (sd), "BIT: %#x & %#x -> %#x", TRACE_ALU (cpu, "BIT: %#x & %#x -> %#x",
u1, u2, uresult); u1, u2, uresult);
FLAGS (uresult, uresult != 0); FLAGS (uresult, uresult != 0);
} }
@ -1269,7 +1263,7 @@ msp430_step_once (SIM_DESC sd)
u1 = DSRC; u1 = DSRC;
u2 = SRC; u2 = SRC;
uresult = u1 & ~ u2; uresult = u1 & ~ u2;
TRACE_ALU (MSP430_CPU (sd), "BIC: %#x & ~ %#x = %#x", TRACE_ALU (cpu, "BIC: %#x & ~ %#x = %#x",
u1, u2, uresult); u1, u2, uresult);
DEST (uresult); DEST (uresult);
} }
@ -1281,7 +1275,7 @@ msp430_step_once (SIM_DESC sd)
u1 = DSRC; u1 = DSRC;
u2 = SRC; u2 = SRC;
uresult = u1 | u2; uresult = u1 | u2;
TRACE_ALU (MSP430_CPU (sd), "BIS: %#x | %#x = %#x", TRACE_ALU (cpu, "BIS: %#x | %#x = %#x",
u1, u2, uresult); u1, u2, uresult);
DEST (uresult); DEST (uresult);
} }
@ -1294,7 +1288,7 @@ msp430_step_once (SIM_DESC sd)
u1 = DSRC; u1 = DSRC;
u2 = SRC; u2 = SRC;
uresult = u1 ^ u2; uresult = u1 ^ u2;
TRACE_ALU (MSP430_CPU (sd), "XOR: %#x & %#x = %#x", TRACE_ALU (cpu, "XOR: %#x & %#x = %#x",
u1, u2, uresult); u1, u2, uresult);
DEST (uresult); DEST (uresult);
FLAGSV (uresult, uresult != 0, (u1 & s1) && (u2 & s1)); FLAGSV (uresult, uresult != 0, (u1 & s1) && (u2 & s1));
@ -1314,7 +1308,7 @@ msp430_step_once (SIM_DESC sd)
RRUX, so the carry bit must be ignored. */ RRUX, so the carry bit must be ignored. */
if (opcode->zc == 0 && (SR & MSP430_FLAG_C)) if (opcode->zc == 0 && (SR & MSP430_FLAG_C))
uresult |= (1 << (opcode->size - 1)); uresult |= (1 << (opcode->size - 1));
TRACE_ALU (MSP430_CPU (sd), "RRC: %#x >>= %#x", TRACE_ALU (cpu, "RRC: %#x >>= %#x",
u1, uresult); u1, uresult);
DEST (uresult); DEST (uresult);
FLAGS (uresult, carry_to_use); FLAGS (uresult, carry_to_use);
@ -1326,7 +1320,7 @@ msp430_step_once (SIM_DESC sd)
{ {
u1 = SRC; u1 = SRC;
uresult = ((u1 >> 8) & 0x00ff) | ((u1 << 8) & 0xff00); uresult = ((u1 >> 8) & 0x00ff) | ((u1 << 8) & 0xff00);
TRACE_ALU (MSP430_CPU (sd), "SWPB: %#x -> %#x", TRACE_ALU (cpu, "SWPB: %#x -> %#x",
u1, uresult); u1, uresult);
DEST (uresult); DEST (uresult);
} }
@ -1339,7 +1333,7 @@ msp430_step_once (SIM_DESC sd)
c = u1 & 1; c = u1 & 1;
s1 = 1 << (opcode->size - 1); s1 = 1 << (opcode->size - 1);
uresult = (u1 >> 1) | (u1 & s1); uresult = (u1 >> 1) | (u1 & s1);
TRACE_ALU (MSP430_CPU (sd), "RRA: %#x >>= %#x", TRACE_ALU (cpu, "RRA: %#x >>= %#x",
u1, uresult); u1, uresult);
DEST (uresult); DEST (uresult);
FLAGS (uresult, c); FLAGS (uresult, c);
@ -1352,7 +1346,7 @@ msp430_step_once (SIM_DESC sd)
u1 = SRC; u1 = SRC;
c = u1 & 1; c = u1 & 1;
uresult = (u1 >> 1); uresult = (u1 >> 1);
TRACE_ALU (MSP430_CPU (sd), "RRU: %#x >>= %#x", TRACE_ALU (cpu, "RRU: %#x >>= %#x",
u1, uresult); u1, uresult);
DEST (uresult); DEST (uresult);
FLAGS (uresult, c); FLAGS (uresult, c);
@ -1367,8 +1361,7 @@ msp430_step_once (SIM_DESC sd)
uresult = u1 | 0xfff00; uresult = u1 | 0xfff00;
else else
uresult = u1 & 0x000ff; uresult = u1 & 0x000ff;
TRACE_ALU (MSP430_CPU (sd), "SXT: %#x -> %#x", TRACE_ALU (cpu, "SXT: %#x -> %#x", u1, uresult);
u1, uresult);
DEST (uresult); DEST (uresult);
FLAGS (uresult, c); FLAGS (uresult, c);
} }
@ -1416,7 +1409,7 @@ msp430_step_once (SIM_DESC sd)
REG_PUT (MSR_SP, REG_GET (MSR_SP) - op_bytes); REG_PUT (MSR_SP, REG_GET (MSR_SP) - op_bytes);
mem_put_val (sd, SP, PC, op_bits); mem_put_val (sd, SP, PC, op_bits);
TRACE_ALU (MSP430_CPU (sd), "CALL: func %#x ret %#x, sp %#x", TRACE_ALU (cpu, "CALL: func %#x ret %#x, sp %#x",
u1, PC, SP); u1, PC, SP);
REG_PUT (MSR_PC, u1); REG_PUT (MSR_PC, u1);
break; break;
@ -1432,8 +1425,7 @@ msp430_step_once (SIM_DESC sd)
8-bits of SR will have been written to the stack here, and will 8-bits of SR will have been written to the stack here, and will
have been read as 0. */ have been read as 0. */
PC |= (u1 & 0xF000) << 4; PC |= (u1 & 0xF000) << 4;
TRACE_ALU (MSP430_CPU (sd), "RETI: pc %#x sr %#x", TRACE_ALU (cpu, "RETI: pc %#x sr %#x", PC, SR);
PC, SR);
break; break;
/* Jumps. */ /* Jumps. */
@ -1470,14 +1462,14 @@ msp430_step_once (SIM_DESC sd)
if (u1) if (u1)
{ {
TRACE_BRANCH (MSP430_CPU (sd), "J%s: pc %#x -> %#x sr %#x, taken", TRACE_BRANCH (cpu, "J%s: pc %#x -> %#x sr %#x, taken",
cond_string (opcode->cond), PC, i, SR); cond_string (opcode->cond), PC, i, SR);
PC = i; PC = i;
if (PC == opcode_pc) if (PC == opcode_pc)
exit (0); exit (0);
} }
else else
TRACE_BRANCH (MSP430_CPU (sd), "J%s: pc %#x to %#x sr %#x, not taken", TRACE_BRANCH (cpu, "J%s: pc %#x to %#x sr %#x, not taken",
cond_string (opcode->cond), PC, i, SR); cond_string (opcode->cond), PC, i, SR);
break; break;

2
sim/msp430/msp430-sim.h
View File

@ -44,6 +44,6 @@ struct msp430_cpu_state
uint64_t hw32mult_result; uint64_t hw32mult_result;
}; };
#define HWMULT(SD, FIELD) MSP430_CPU (SD)->state.FIELD #define HWMULT(sd, field) MSP430_SIM_CPU (STATE_CPU (sd, 0))->field
#endif #endif

12
sim/msp430/sim-main.h
View File

@ -21,19 +21,13 @@
#ifndef _MSP430_MAIN_SIM_H_ #ifndef _MSP430_MAIN_SIM_H_
#define _MSP430_MAIN_SIM_H_ #define _MSP430_MAIN_SIM_H_
#define SIM_HAVE_COMMON_SIM_CPU
#include "sim-basics.h" #include "sim-basics.h"
#include "msp430-sim.h" #include "msp430-sim.h"
#include "sim-base.h" #include "sim-base.h"
struct _sim_cpu #define MSP430_SIM_CPU(cpu) ((struct msp430_cpu_state *) CPU_ARCH_DATA (cpu))
{
/* Simulator specific members. */
struct msp430_cpu_state state;
sim_cpu_base base;
};
#define MSP430_CPU(sd) (STATE_CPU ((sd), 0))
#define MSP430_CPU_STATE(sd) (MSP430_CPU ((sd)->state))
#include "sim-config.h" #include "sim-config.h"
#include "sim-types.h" #include "sim-types.h"