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sim: bfin: import testsuite

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Now that the common sim testsuite code supports .S and .c files, we
can import the Blackfin testsuite.  There are about ~800 tests here,
so I'm only attaching a compressed patch of them.  Other than adding
files to sim/testsuite/sim/bfin/, the sim/configure.tgt file was
updated to mark Blackfin as having a testsuite, and sim/configure
regenerated.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger 2011-06-04 17:44:22 +00:00
parent eb3243445a
commit 1d7b4a7037
816 changed files with 221152 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
sim/ChangeLog
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@ -1,3 +1,8 @@
2011-06-04 Mike Frysinger <vapier@gentoo.org>
* configure.tgt (bfin-*-*): Add sim_testsuite=yes.
* configure: Regenerate.
2011-05-04 Joseph Myers <joseph@codesourcery.com>
* configure.tgt (thumb*-*-* | strongarm*-*-* | xscale-*-*): Don't

1
sim/configure vendored
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@ -3646,6 +3646,7 @@ subdirs="$subdirs arm"
subdirs="$subdirs bfin"
sim_testsuite=yes
;;
cr16*-*-*)

1
sim/configure.tgt
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@ -25,6 +25,7 @@ case "${target}" in
;;
bfin-*-*)
SIM_ARCH(bfin)
sim_testsuite=yes
;;
cr16*-*-*)
SIM_ARCH(cr16)

51
sim/testsuite/sim/bfin/10272_small.s Normal file
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@ -0,0 +1,51 @@
# mach: bfin
.include "testutils.inc"
start
loadsym P5, tmp0;
r6=0xFF (Z);
W[p5+0x6] = r6;
r0.l=0x0808;
r0.h=0xffff;
R1 = W[P5 + 0x6 ] (X);
R0 = DEPOSIT(R1, R0);
W[P5+0x6] = R0;
R5=W[P5+0x6] (X);
DBGA(r5.l,0xffff);
/* This instruction order fails to successfully write R0 back */
r0.l=0x0808;
r0.h=0xffff;
loadsym P5, tmp0;
r6=0xFF (Z);
W[p5+0x6] = r6;
R1 = W[P5 + 0x6 ] (X);
R0 = DEPOSIT(R1, R0);
W[P5+0x6] = R0;
R5=W[P5+0x6] (X);
DBGA(r5.l,0xffff);
r4=1;
loadsym P5, tmp0;
r6=0xFF (Z);
W[p5+0x6] = r6;
R1 = W[P5 + 0x6 ] (X);
R0 = R1+R4;
W[P5+0x6] = R0;
R5=W[P5+0x6] (X);
DBGA(r5.l,0x100);
pass;
.data
tmp0:
.space (0x10);

39
sim/testsuite/sim/bfin/10436.s Normal file
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@ -0,0 +1,39 @@
# mach: bfin
.include "testutils.inc"
start
loadsym i0, tmp0;
r1 = i0;
b0=i0;
r3=4;
l0=0;
m0=0;
r5.l=0xdead;
r5.h=0xbeef;
l0=r3;
[i0++] = r5;
l0 = 0;
r0 = i0;
CC = R0 == R1;
if !CC JUMP _fail;
l0=r3;
r3=[i0--];
r0=i0;
CC = R0 == R1;
if !CC JUMP _fail;
pass
_fail:
fail
.data
tmp0:
.space (0x100);

21
sim/testsuite/sim/bfin/10622.s Normal file
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@ -0,0 +1,21 @@
# mach: bfin
.include "testutils.inc"
start
r2.l = 0x1234;
r2.h = 0xff90;
r4=8;
i2=r2;
m2 = 4;
a0 = 0;
r1.l = (a0 += r4.l *r4.l) (IS) || I2 += m2 || nop;
r0 = i2;
dbga(r0.l, 0x1238);
dbga(r0.h, 0xff90);
_halt0:
pass;

17
sim/testsuite/sim/bfin/10742.s Normal file
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@ -0,0 +1,17 @@
# mach: bfin
.include "testutils.inc"
start
r5.h=0x1234;
r5.l=0x5678;
p5 = r5;
p5.l = 0x1000;
r0 = p5;
dbga(r0.h, 0x1234);
dbga(r0.l, 0x1000);
pass

55
sim/testsuite/sim/bfin/10799.s Normal file
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@ -0,0 +1,55 @@
# mach: bfin
.include "testutils.inc"
start
fp = sp;
[--SP]=RETS;
loadsym R1, _b;
loadsym R2, _a;
R0 = R2;
SP += -12;
R2 = 4;
CALL _dot;
R1 = R0;
R0 = 30;
dbga( r1.l, 0x1e);
pass
_dot:
P0 = R1;
CC = R2 <= 0;
R3 = R0;
R0 = 0;
IF CC JUMP ._P1L1 (bp);
R0 = 1;
I0 = R3;
R0 = MAX (R0,R2) || R2 = [P0++] || NOP;
P1 = R0;
R0 = 0;
R1 = [I0++];
LSETUP (._P1L4 , ._P1L5) LC0=P1;
._P1L4:
R1 *= R2;
._P1L5:
R0= R0 + R1 (NS) || R2 = [P0++] || R1 = [I0++];
._P1L1:
RTS;
.data;
_a:
.db 0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x00,0x00,0x00;
.db 0x04,0x00,0x00,0x00;
_b:
.db 0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x03,0x00,0x00,0x00;
.db 0x04,0x00,0x00,0x00;

40
sim/testsuite/sim/bfin/11080.s Normal file
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@ -0,0 +1,40 @@
# Blackfin testcase for DISALGNEXCPT
# mach: bfin
.include "testutils.inc"
start
loadsym R0, foo;
R0 += 1;
I1 = R0;
M0 = 4 (z);
//dag0misalgn, dag1misalgn EXCAUSE value
R7 = 0x24 (z);
// Get just the EXCAUSE field before
R5=SEQSTAT;
R5 = R5 << 26;
R5 = R5 >> 26;
DISALGNEXCPT || R2 = [I1++M0]; // i1 = 0xff9004aa (misaligned)
// Get just the EXCAUSE field after
R6=SEQSTAT;
R6 = R6 << 26;
R6 = R6 >> 26;
// EXCAUSE of 0x24 == misaligned data memory access
CC = R6 == R7;
if CC jump _fail;
_pass:
pass;
_fail:
fail;
.data
foo:
.space 0x10

38
sim/testsuite/sim/bfin/7641.s Normal file
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@ -0,0 +1,38 @@
# Blackfin testcase for playing with TESTSET
# mach: bfin
.include "testutils.inc"
start
loadsym P0, element1
loadsym P1, element2
R0 = B [P0]; // R0 should get 00
R1 = B [P1]; // R1 should get 02
TESTSET(P0); // should set CC and MSB of memory byte
R0 = CC;
TESTSET(P1); // should clear CC and not change MSB of memory
R1 = CC;
R2 = B [P0]; // R2 should get 80
R3 = B [P1]; // R3 should get 02
dbga(R0.l,0x0001);
dbga(R0.h,0x0000);
dbga(R1.l,0x0000);
dbga(R1.h,0x0000);
dbga(R2.l,0x0080);
dbga(R2.h,0x0000);
dbga(R3.l,0x0082);
dbga(R3.h,0x0000);
pass
.data
.align 4;
element1: .long 0x0
element2: .long 0x2
element3: .long 0x4

243
sim/testsuite/sim/bfin/ChangeLog Normal file
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@ -0,0 +1,243 @@
2011-06-04 Mike Frysinger <vapier@gentoo.org>
* .gitignore, 10272_small.s, 10436.s, 10622.s, 10742.s, 10799.s,
11080.s, 7641.s, a0.s, a0shift.S, a10.s, a11.S, a12.s, a1.s, a20.S,
a21.s, a22.s, a23.s, a24.s, a25.s, a26.s, a2.s, a30.s, a3.s, a4.s,
a5.s, a6.s, a7.s, a8.s, a9.s, abs-2.S, abs-3.S, abs-4.S, abs_acc.s,
abs.S, acc-rot.s, acp5_19.s, acp5_4.s, add_imm7.s, add_shift.S,
add_sub_acc.s, addsub_flags.S, algnbug1.s, algnbug2.s, allinsn.exp,
argc.c, ashift_flags.s, ashift.s, b0.S, b1.s, b2.S, brcc.s, brevadd.s,
byteop16m.s, byteop16p.s, byteop1p.s, byteop2p.s, byteop3p.s,
byteunpack.s, c_alu2op_arith_r_sft.s, c_alu2op_conv_b.s,
c_alu2op_conv_h.s, c_alu2op_conv_mix.s, c_alu2op_conv_neg.s,
c_alu2op_conv_toggle.s, c_alu2op_conv_xb.s, c_alu2op_conv_xh.s,
c_alu2op_divq.s, c_alu2op_divs.s, c_alu2op_log_l_sft.s,
c_alu2op_log_r_sft.s, c_alu2op_shadd_1.s, c_alu2op_shadd_2.s,
c_brcc_bp1.s, c_brcc_bp2.s, c_brcc_bp3.s, c_brcc_bp4.s,
c_brcc_brf_bp.s, c_brcc_brf_brt_bp.s, c_brcc_brf_brt_nbp.s,
c_brcc_brf_fbkwd.s, c_brcc_brf_nbp.s, c_brcc_brt_bp.s,
c_brcc_brt_nbp.s, c_brcc_kills_dhits.s, c_brcc_kills_dmiss.s,
c_br_preg_killed_ac.s, c_br_preg_killed_ex1.s, c_br_preg_stall_ac.s,
c_br_preg_stall_ex1.s, cc0.s, cc1.s, cc5.S, c_cactrl_iflush_pr_pp.s,
c_cactrl_iflush_pr.s, c_calla_ljump.s, c_calla_subr.s, cc-alu.S,
cc-astat-bits.s, c_cc2dreg.s, c_cc2stat_cc_ac.S, c_cc2stat_cc_an.s,
c_cc2stat_cc_aq.s, c_cc2stat_cc_av0.S, c_cc2stat_cc_av1.S,
c_cc2stat_cc_az.s, c_ccflag_a0a1.S, c_cc_flag_ccmv_depend.S,
c_ccflag_dr_dr.s, c_ccflag_dr_dr_uu.s, c_cc_flagdreg_mvbrsft.s,
c_cc_flagdreg_mvbrsft_s1.s, c_cc_flagdreg_mvbrsft_sn.s,
c_ccflag_dr_imm3.s, c_ccflag_dr_imm3_uu.s, c_ccflag_pr_imm3.s,
c_ccflag_pr_imm3_uu.s, c_ccflag_pr_pr.s, c_ccflag_pr_pr_uu.s,
c_ccmv_cc_dr_dr.s, c_ccmv_cc_dr_pr.s, c_ccmv_cc_pr_pr.s,
c_ccmv_ncc_dr_dr.s, c_ccmv_ncc_dr_pr.s, c_ccmv_ncc_pr_pr.s,
c_cc_regmvlogi_mvbrsft.s, c_cc_regmvlogi_mvbrsft_s1.s,
c_cc_regmvlogi_mvbrsft_sn.S, c_comp3op_dr_and_dr.s,
c_comp3op_dr_minus_dr.s, c_comp3op_dr_mix.s, c_comp3op_dr_or_dr.s,
c_comp3op_dr_plus_dr.s, c_comp3op_dr_xor_dr.s,
c_comp3op_pr_plus_pr_sh1.s, c_comp3op_pr_plus_pr_sh2.s,
c_compi2opd_dr_add_i7_n.s, c_compi2opd_dr_add_i7_p.s,
c_compi2opd_dr_eq_i7_n.s, c_compi2opd_dr_eq_i7_p.s,
c_compi2opd_flags_2.S, c_compi2opd_flags.S, c_compi2opp_pr_add_i7_n.s,
c_compi2opp_pr_add_i7_p.s, c_compi2opp_pr_eq_i7_n.s,
c_compi2opp_pr_eq_i7_p.s, c_dagmodik_lnz_imgebl.s,
c_dagmodik_lnz_imltbl.s, c_dagmodik_lz_inc_dec.s,
c_dagmodim_lnz_imgebl.s, c_dagmodim_lnz_imltbl.s,
c_dagmodim_lz_inc_dec.s, c_dsp32alu_a0a1s.s, c_dsp32alu_a0_pm_a1.s,
c_dsp32alu_aa_absabs.s, c_dsp32alu_a_abs_a.s, c_dsp32alu_aa_negneg.s,
c_dsp32alu_absabs.s, c_dsp32alu_abs.s, c_dsp32alu_alhwx.s,
c_dsp32alu_a_neg_a.s, c_dsp32alu_awx.s, c_dsp32alu_byteop1ew.s,
c_dsp32alu_byteop2.s, c_dsp32alu_byteop3.s, c_dsp32alu_bytepack.s,
c_dsp32alu_byteunpack.s, c_dsp32alu_disalnexcpt.s, c_dsp32alu_maxmax.s,
c_dsp32alu_max.s, c_dsp32alu_minmin.s, c_dsp32alu_min.s,
c_dsp32alu_mix.s, c_dsp32alu_rh_m.s, c_dsp32alu_rh_p.s,
c_dsp32alu_rh_rnd12_m.s, c_dsp32alu_rh_rnd12_p.s,
c_dsp32alu_rh_rnd20_m.s, c_dsp32alu_rh_rnd20_p.s,
c_dsp32alu_r_lh_a0pa1.s, c_dsp32alu_rlh_rnd.s, c_dsp32alu_rl_m.s,
c_dsp32alu_rl_p.s, c_dsp32alu_rl_rnd12_m.s, c_dsp32alu_rl_rnd12_p.s,
c_dsp32alu_rl_rnd20_m.s, c_dsp32alu_rl_rnd20_p.s, c_dsp32alu_rmm.s,
c_dsp32alu_rmp.s, c_dsp32alu_rm.s, c_dsp32alu_r_negneg.s,
c_dsp32alu_rpm.s, c_dsp32alu_rpp.s, c_dsp32alu_rp.s,
c_dsp32alu_rr_lph_a1a0.s, c_dsp32alu_rrpm_aa.s, c_dsp32alu_rrpmmp.s,
c_dsp32alu_rrpmmp_sft.s, c_dsp32alu_rrpmmp_sft_x.s, c_dsp32alu_rrpm.s,
c_dsp32alu_rrppmm.s, c_dsp32alu_rrppmm_sft.s,
c_dsp32alu_rrppmm_sft_x.s, c_dsp32alu_saa.s, c_dsp32alu_sat_aa.S,
c_dsp32alu_search.s, c_dsp32alu_sgn.s, c_dsp32mac_a1a0_iuw32.s,
c_dsp32mac_a1a0_m.s, c_dsp32mac_a1a0.s, c_dsp32mac_dr_a0_ih.s,
c_dsp32mac_dr_a0_i.s, c_dsp32mac_dr_a0_is.s, c_dsp32mac_dr_a0_iu.s,
c_dsp32mac_dr_a0_m.s, c_dsp32mac_dr_a0.s, c_dsp32mac_dr_a0_s.s,
c_dsp32mac_dr_a0_t.s, c_dsp32mac_dr_a0_tu.s, c_dsp32mac_dr_a0_u.s,
c_dsp32mac_dr_a1a0_iutsh.s, c_dsp32mac_dr_a1a0_m.s,
c_dsp32mac_dr_a1a0.s, c_dsp32mac_dr_a1_ih.s, c_dsp32mac_dr_a1_i.s,
c_dsp32mac_dr_a1_is.s, c_dsp32mac_dr_a1_iu.s, c_dsp32mac_dr_a1_m.s,
c_dsp32mac_dr_a1.s, c_dsp32mac_dr_a1_s.s, c_dsp32mac_dr_a1_t.s,
c_dsp32mac_dr_a1_tu.s, c_dsp32mac_dr_a1_u.s, c_dsp32mac_mix.s,
c_dsp32mac_pair_a0_i.s, c_dsp32mac_pair_a0_is.s,
c_dsp32mac_pair_a0_m.s, c_dsp32mac_pair_a0.s, c_dsp32mac_pair_a0_s.s,
c_dsp32mac_pair_a0_u.s, c_dsp32mac_pair_a1a0_i.s,
c_dsp32mac_pair_a1a0_is.s, c_dsp32mac_pair_a1a0_m.s,
c_dsp32mac_pair_a1a0.s, c_dsp32mac_pair_a1a0_s.s,
c_dsp32mac_pair_a1a0_u.s, c_dsp32mac_pair_a1_i.s,
c_dsp32mac_pair_a1_is.s, c_dsp32mac_pair_a1_m.s, c_dsp32mac_pair_a1.s,
c_dsp32mac_pair_a1_s.s, c_dsp32mac_pair_a1_u.s, c_dsp32mac_pair_mix.s,
c_dsp32mult_dr_ih.s, c_dsp32mult_dr_i.s, c_dsp32mult_dr_is.s,
c_dsp32mult_dr_iu.s, c_dsp32mult_dr_m_i.s, c_dsp32mult_dr_m_iutsh.s,
c_dsp32mult_dr_mix.s, c_dsp32mult_dr_m.s, c_dsp32mult_dr_m_s.s,
c_dsp32mult_dr_m_t.s, c_dsp32mult_dr_m_u.s, c_dsp32mult_dr.s,
c_dsp32mult_dr_s.s, c_dsp32mult_dr_t.s, c_dsp32mult_dr_tu.s,
c_dsp32mult_dr_u.s, c_dsp32mult_pair_i.s, c_dsp32mult_pair_is.s,
c_dsp32mult_pair_m_i.s, c_dsp32mult_pair_m_is.s, c_dsp32mult_pair_m.s,
c_dsp32mult_pair_m_s.s, c_dsp32mult_pair_m_u.s, c_dsp32mult_pair.s,
c_dsp32mult_pair_s.s, c_dsp32mult_pair_u.s, c_dsp32shift_a0alr.s,
c_dsp32shift_af.s, c_dsp32shift_af_s.s, c_dsp32shift_ahalf_ln.s,
c_dsp32shift_ahalf_ln_s.s, c_dsp32shift_ahalf_lp.s,
c_dsp32shift_ahalf_lp_s.s, c_dsp32shift_ahalf_rn.s,
c_dsp32shift_ahalf_rn_s.s, c_dsp32shift_ahalf_rp.s,
c_dsp32shift_ahalf_rp_s.s, c_dsp32shift_ahh.s, c_dsp32shift_ahh_s.s,
c_dsp32shift_align16.s, c_dsp32shift_align24.s, c_dsp32shift_align8.s,
c_dsp32shift_amix.s, c_dsp32shift_bitmux.s, c_dsp32shift_bxor.s,
c_dsp32shift_expadj_h.s, c_dsp32shift_expadj_l.s,
c_dsp32shift_expadj_r.s, c_dsp32shift_expexp_r.s, c_dsp32shift_fdepx.s,
c_dsp32shift_fextx.s, c_dsp32shiftim_a0alr.s, c_dsp32shiftim_af.s,
c_dsp32shiftim_af_s.s, c_dsp32shiftim_ahalf_ln.s,
c_dsp32shiftim_ahalf_ln_s.s, c_dsp32shiftim_ahalf_lp.s,
c_dsp32shiftim_ahalf_lp_s.s, c_dsp32shiftim_ahalf_rn.s,
c_dsp32shiftim_ahalf_rn_s.s, c_dsp32shiftim_ahalf_rp.s,
c_dsp32shiftim_ahalf_rp_s.s, c_dsp32shiftim_ahh.s,
c_dsp32shiftim_ahh_s.s, c_dsp32shiftim_amix.s, c_dsp32shiftim_lf.s,
c_dsp32shiftim_lhalf_ln.s, c_dsp32shiftim_lhalf_lp.s,
c_dsp32shiftim_lhalf_rn.s, c_dsp32shiftim_lhalf_rp.s,
c_dsp32shiftim_lhh.s, c_dsp32shiftim_lmix.s, c_dsp32shiftim_rot.s,
c_dsp32shift_lf.s, c_dsp32shift_lhalf_ln.s, c_dsp32shift_lhalf_lp.s,
c_dsp32shift_lhalf_rn.s, c_dsp32shift_lhalf_rp.s, c_dsp32shift_lhh.s,
c_dsp32shift_lmix.s, c_dsp32shift_ones.s, c_dsp32shift_pack.s,
c_dsp32shift_rot_mix.s, c_dsp32shift_rot.s, c_dsp32shift_signbits_rh.s,
c_dsp32shift_signbits_rl.s, c_dsp32shift_signbits_r.s,
c_dsp32shift_vmax.s, c_dsp32shift_vmaxvmax.s, c_dspldst_ld_drhi_ipp.s,
c_dspldst_ld_drhi_i.s, c_dspldst_ld_dr_ippm.s, c_dspldst_ld_dr_ipp.s,
c_dspldst_ld_dr_i.s, c_dspldst_ld_drlo_ipp.s, c_dspldst_ld_drlo_i.s,
c_dspldst_st_drhi_ipp.s, c_dspldst_st_drhi_i.s, c_dspldst_st_dr_ippm.s,
c_dspldst_st_dr_ipp.s, c_dspldst_st_dr_i.s, c_dspldst_st_drlo_ipp.s,
c_dspldst_st_drlo_i.s, cec-exact-exception.S, cec-ifetch.S,
cec-multi-pending.S, cec-non-operating-env.s, cec-no-snen-reti.S,
cec-raise-reti.S, cec-snen-reti.S, cec-syscfg-ssstep.S,
cec-system-call.S, c_except_illopcode.S, c_except_sys_sstep.S,
c_except_user_mode.S, c_interr_disable_enable.S, c_interr_disable.S,
c_interr_excpt.S, c_interr_loopsetup_stld.S, c_interr_nested.S,
c_interr_nmi.S, c_interr_pending_2.S, c_interr_pending.S,
c_interr_timer_reload.S, c_interr_timer.S, c_interr_timer_tcount.S,
c_interr_timer_tscale.S, cir1.s, cir.s, c_ldimmhalf_dreg.s,
c_ldimmhalf_drhi.s, c_ldimmhalf_drlo.s, c_ldimmhalf_h_dr.s,
c_ldimmhalf_h_ibml.s, c_ldimmhalf_h_pr.s, c_ldimmhalf_l_dr.s,
c_ldimmhalf_l_ibml.s, c_ldimmhalf_l_pr.s, c_ldimmhalf_lz_dr.s,
c_ldimmhalf_lzhi_dr.s, c_ldimmhalf_lzhi_ibml.s, c_ldimmhalf_lzhi_pr.s,
c_ldimmhalf_lz_ibml.s, c_ldimmhalf_lz_pr.s, c_ldimmhalf_pibml.s,
c_ldstidxl_ld_dr_b.s, c_ldstidxl_ld_dreg.s, c_ldstidxl_ld_dr_h.s,
c_ldstidxl_ld_dr_xb.s, c_ldstidxl_ld_dr_xh.s, c_ldstidxl_ld_preg.s,
c_ldstidxl_st_dr_b.s, c_ldstidxl_st_dreg.s, c_ldstidxl_st_dr_h.s,
c_ldstidxl_st_preg.s, c_ldstiifp_ld_dreg.s, c_ldstiifp_ld_preg.s,
c_ldstiifp_st_dreg.s, c_ldstiifp_st_preg.s, c_ldstii_ld_dreg.s,
c_ldstii_ld_dr_h.s, c_ldstii_ld_dr_xh.s, c_ldstii_ld_preg.s,
c_ldstii_st_dreg.s, c_ldstii_st_dr_h.s, c_ldstii_st_preg.s,
c_ldst_ld_d_p_b.s, c_ldst_ld_d_p_h.s, c_ldst_ld_d_p_mm_b.s,
c_ldst_ld_d_p_mm_h.s, c_ldst_ld_d_p_mm.s, c_ldst_ld_d_p_mm_xb.s,
c_ldst_ld_d_p_mm_xh.s, c_ldst_ld_d_p_pp_b.s, c_ldst_ld_d_p_pp_h.s,
c_ldst_ld_d_p_ppmm_hbx.s, c_ldst_ld_d_p_pp.s, c_ldst_ld_d_p_pp_xb.s,
c_ldst_ld_d_p_pp_xh.s, c_ldst_ld_d_p.s, c_ldst_ld_d_p_xb.s,
c_ldst_ld_d_p_xh.s, c_ldst_ld_p_p_mm.s, c_ldst_ld_p_p_pp.s,
c_ldst_ld_p_p.s, c_ldstpmod_ld_dreg.s, c_ldstpmod_ld_dr_hi.s,
c_ldstpmod_ld_dr_lo.s, c_ldstpmod_ld_h_xh.s, c_ldstpmod_ld_lohi.s,
c_ldstpmod_st_dreg.s, c_ldstpmod_st_dr_hi.s, c_ldstpmod_st_dr_lo.s,
c_ldstpmod_st_lohi.s, c_ldst_st_p_d_b.s, c_ldst_st_p_d_h.s,
c_ldst_st_p_d_mm_b.s, c_ldst_st_p_d_mm_h.s, c_ldst_st_p_d_mm.s,
c_ldst_st_p_d_pp_b.s, c_ldst_st_p_d_pp_h.s, c_ldst_st_p_d_pp.s,
c_ldst_st_p_d.s, c_ldst_st_p_p_mm.s, c_ldst_st_p_p_pp.s,
c_ldst_st_p_p.s, c_linkage.s, cli-sti.s, c_logi2op_alshft_mix.s,
c_logi2op_arith_shft.s, c_logi2op_bitclr.s, c_logi2op_bitset.s,
c_logi2op_bittgl.s, c_logi2op_bittst.s, c_logi2op_log_l_shft_astat.S,
c_logi2op_log_l_shft.s, c_logi2op_log_r_shft_astat.S,
c_logi2op_log_r_shft.s, c_logi2op_nbittst.s, c_loopsetup_nested_bot.s,
c_loopsetup_nested_prelc.s, c_loopsetup_nested.s,
c_loopsetup_nested_top.s, c_loopsetup_overlap.s,
c_loopsetup_preg_div2_lc0.s, c_loopsetup_preg_div2_lc1.s,
c_loopsetup_preg_lc0.s, c_loopsetup_preg_lc1.s,
c_loopsetup_preg_stld.s, c_loopsetup_prelc.s, c_loopsetup_topbotcntr.s,
c_mmr_interr_ctl.s, c_mmr_loop.S, c_mmr_loop_user_except.S,
c_mmr_ppop_illegal_adr.S, c_mmr_ppopm_illegal_adr.S, c_mmr_timer.S,
c_mode_supervisor.S, c_mode_user.S, c_mode_user_superivsor.S, cmpacc.s,
cmpdreg.S, c_multi_issue_dsp_ld_ld.s, c_multi_issue_dsp_ldst_1.s,
c_multi_issue_dsp_ldst_2.s, compare.s, conv_enc_gen.s,
c_progctrl_call_pcpr.s, c_progctrl_call_pr.s,
c_progctrl_clisti_interr.S, c_progctrl_csync_mmr.S,
c_progctrl_except_rtx.S, c_progctrl_excpt.S, c_progctrl_jump_pcpr.s,
c_progctrl_jump_pr.s, c_progctrl_nop.s, c_progctrl_raise_rt_i_n.S,
c_progctrl_rts.s, c_ptr2op_pr_neg_pr.s, c_ptr2op_pr_sft_2_1.s,
c_ptr2op_pr_shadd_1_2.s, c_pushpopmultiple_dp_pair.s,
c_pushpopmultiple_dp.s, c_pushpopmultiple_dreg.s,
c_pushpopmultiple_preg.s, c_regmv_acc_acc.s, c_regmv_dag_lz_dep.s,
c_regmv_dr_acc_acc.s, c_regmv_dr_dep_nostall.s, c_regmv_dr_dr.s,
c_regmv_dr_imlb.s, c_regmv_dr_pr.s, c_regmv_imlb_dep_nostall.s,
c_regmv_imlb_dep_stall.s, c_regmv_imlb_dr.s, c_regmv_imlb_imlb.s,
c_regmv_imlb_pr.s, c_regmv_pr_dep_nostall.s, c_regmv_pr_dep_stall.s,
c_regmv_pr_dr.s, c_regmv_pr_imlb.s, c_regmv_pr_pr.s,
c_seq_ac_raise_mv_ppop.S, c_seq_ac_raise_mv.S,
c_seq_ac_regmv_pushpop.S, c_seq_dec_raise_pushpop.S,
c_seq_ex1_brcc_mv_pop.S, c_seq_ex1_call_mv_pop.S, c_seq_ex1_j_mv_pop.S,
c_seq_ex1_raise_brcc_mv_pop.S, c_seq_ex1_raise_call_mv_pop.S,
c_seq_ex1_raise_j_mv_pop.S, c_seq_ex2_brcc_mp_mv_pop.S,
c_seq_ex2_mmrj_mvpop.S, c_seq_ex2_mmr_mvpop.S,
c_seq_ex2_raise_mmrj_mvpop.S, c_seq_ex2_raise_mmr_mvpop.S,
c_seq_ex3_ls_brcc_mvp.S, c_seq_ex3_ls_mmrj_mvp.S,
c_seq_ex3_ls_mmr_mvp.S, c_seq_ex3_raise_ls_mmrj_mvp.S,
c_seq_wb_cs_lsmmrj_mvp.S, c_seq_wb_raisecs_lsmmrj_mvp.S,
c_seq_wb_rti_lsmmrj_mvp.S, c_seq_wb_rtn_lsmmrj_mvp.S,
c_seq_wb_rtx_lsmmrj_mvp.S, c_ujump.s, cycles.s, d0.s, d1.s, d2.s,
dbg_brprd_ntkn_src_kill.S, dbg_brtkn_nprd_src_kill.S,
dbg_jmp_src_kill.S, dbg_tr_basic.S, dbg_tr_simplejp.S, dbg_tr_tbuf0.S,
dbg_tr_umode.S, disalnexcpt_implicit.S, div0.s, divq.s, dotproduct2.s,
dotproduct.s, double_prec_mult.s, dsp_a4.s, dsp_a7.s, dsp_a8.s,
dsp_d0.s, dsp_d1.s, dsp_neg.S, dsp_s1.s, e0.s, edn_snafu.s,
eu_dsp32mac_s.s, events.s, f221.s, fact.s, fir.s, fsm.s, greg2.s,
hwloop-bits.S, hwloop-branch-in.s, hwloop-branch-out.s,
hwloop-lt-bits.s, hwloop-nested.s, i0.s, iir.s, issue103.s, issue109.s,
issue112.s, issue113.s, issue117.s, issue118.s, issue119.s, issue121.s,
issue123.s, issue124.s, issue125.s, issue126.s, issue127.s, issue129.s,
issue139.S, issue140.S, issue142.s, issue144.s, issue146.S, issue175.s,
issue205.s, issue257.s, issue272.S, issue83.s, issue89.s, l0.s,
l0shift.s, l2_loop.s, link-2.s, link.s, lmu_cplb_multiple0.S,
lmu_cplb_multiple1.S, lmu_excpt_align.S, lmu_excpt_default.S,
lmu_excpt_illaddr.S, lmu_excpt_prot0.S, lmu_excpt_prot1.S, load.s,
logic.s, loop_snafu.s, loop_strncpy.s, lp0.s, lp1.s, lsetup.s,
m0boundary.s, m10.s, m11.s, m12.s, m13.s, m14.s, m15.s, m16.s, m17.s,
m1.S, m2.s, m3.s, m4.s, m5.s, m6.s, m7.s, m8.s, m9.s, mac2halfreg.S,
Makefile, math.s, max_min_flags.s, mc_s2.s, mdma-32bit-1d.c,
mdma-32bit-1d-neg-count.c, mdma-8bit-1d.c, mdma-8bit-1d-neg-count.c,
mdma-skel.h, mem3.s, mmr-exception.s, move.s, msa_acp_5_10.s,
msa_acp_5.10.S, msa_acp_5.12_1.S, msa_acp_5.12_2.S, mult.s, neg-2.S,
neg-3.S, neg.S, nshift.s, PN_generator.s, pr.s, push-pop-multiple.s,
pushpopreg_1.s, push-pop.s, quadaddsub.s, random_0001.s, random_0002.S,
random_0003.S, random_0004.S, random_0005.S, random_0006.S,
random_0007.S, random_0008.S, random_0009.S, random_0010.S,
random_0011.S, random_0012.S, random_0013.S, random_0031.S,
random_0033.S, random_0034.S, run-tests.sh, s0.s, s10.s, s11.s, s12.s,
s13.s, s14.s, s15.s, s16.s, s17.s, s18.s, s19.s, s1.s, s20.s, s21.s,
s2.s, s30.s, s3.s, s4.s, s5.s, s6.s, s7.s, s8.s, s9.s, saatest.s,
se_all16bitopcodes.S, se_all32bitopcodes.lds, se_all32bitopcodes.S,
se_brtarget_stall.S, se_bug_ui2.S, se_bug_ui3.S, se_bug_ui.S,
se_cc2stat_haz.S, se_cc_kill.S, se_cof.S, se_event_quad.S,
se_excpt_dagprotviol.S, se_excpt_ifprotviol.S, se_excpt_ssstep.S,
se_illegalcombination.S, se_kills2.S, se_kill_wbbr.S,
se_loop_disable.S, se_loop_kill_01.S, se_loop_kill_dcr_01.S,
se_loop_kill_dcr.S, se_loop_kill.S, se_loop_lr.S,
se_loop_mv2lb_stall.S, se_loop_mv2lc.S, se_loop_mv2lc_stall.S,
se_loop_mv2lt_stall.S, se_loop_nest_ppm_1.S, se_loop_nest_ppm_2.S,
se_loop_nest_ppm.S, se_loop_ppm_1.S, se_loop_ppm_int.S, se_loop_ppm.S,
se_lsetup_kill.S, se_misaligned_fetch.S, se_more_ret_haz.S, se_mv2lp.S,
se_oneins_zoff.S, se_popkill.S, seqstat.s, se_regmv_usp_sysreg.S,
se_rets_hazard.s, se_rts_rti.S, se_ssstep_dagprotviol.S, se_ssync.S,
se_stall_if2.S, se_undefinedinstruction1.S, se_undefinedinstruction2.S,
se_undefinedinstruction3.S, se_undefinedinstruction4.S,
se_usermode_protviol.S, sign.s, simple0.s, sri.s, stk2.s, stk3.s,
stk4.s, stk5.s, stk6.s, stk.s, syscfg.s, tar10622.s, test-dma.h,
test.h, testset2.s, testset.s, testutils.inc, unlink.S, up0.s, usp.S,
vec-abs-2.S, vec-abs-3.S, vec-abs.S, vecadd.s, vec-neg-2.S,
vec-neg-3.S, vec-neg.S, viterbi2.s, vit_max.s, wtf.s, x1.s, zcall.s,
zeroflagrnd.s: New files.

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# mach: bfin
// GENERIC PN SEQUENCE GENERATOR
// Linear Feedback Shift Register
// -------------------------------
// This solution implements an LFSR by applying an XOR reduction
// function to the 40 bit accumulator, XORing the contents of the
// CC bit, shifting by one the accumulator, and inserting the
// resulting bit on the open bit slot.
// CC --> ----- XOR--------------------------
// | | | | | |
// | | | | | |
// +------------------------------+ v
// | b0 b1 b2 b3 b38 b39 | in <-- by one
// +------------------------------+
// after:
// +------------------------------+
// | b1 b2 b3 b38 b39 in |
// +------------------------------+
// The program shown here is a PN sequence generator, and hence
// does not take any input other than the initial state. However,
// in order to accept an input, one simply needs to rotate the
// input sequence via CC prior to applying the XOR reduction.
.include "testutils.inc"
start
loadsym P1, output;
init_r_regs 0;
ASTAT = R0;
// load Polynomial into A1
A1 = A0 = 0;
R0.L = 0x1cd4;
R0.H = 0xab18;
A1.w = R0;
R0.L = 0x008d;
A1.x = R0.L;
// load InitState into A0
R0.L = 0x0001;
R0.H = 0x0000;
A0.w = R0;
R0.L = 0x0000;
A0.x = R0.L;
P4 = 4;
LSETUP ( l$0 , l$0end ) LC0 = P4;
l$0: // **** START l-LOOP *****
P4 = 32;
LSETUP ( m$1 , m$1 ) LC1 = P4; // **** START m-LOOP *****
m$1:
A0 = BXORSHIFT( A0 , A1, CC );
// store 16 bits of outdata RL1
R1 = A0.w;
l$0end:
[ P1 ++ ] = R1;
// Check results
loadsym I2, output;
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5adf );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x2fc9 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0xbd91 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x5520 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x80d5 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x7fef );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x34d1 );
R0.L = W [ I2 ++ ]; DBGA ( R0.L , 0x915c );
pass
.data;
output:
.dw 0x0000
.dw 0x0000
.dw 0x0000
.dw 0x0000

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# mach: bfin
.include "testutils.inc"
start
R0 = 1;
R0 <<= 1;
DBGA ( R0.L , 2 );
R0 <<= 1;
DBGA ( R0.L , 4 );
R0 <<= 3;
DBGA ( R0.L , 32 );
R0 += 5;
DBGA ( R0.L , 37 );
R0 += -7;
DBGA ( R0.L , 30 );
pass

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# mach: bfin
#include "test.h"
.include "testutils.inc"
start
// 0xfffffe371c
r0 = 0;
r1 = 0;
r2 = 0;
r3 = 0;
r4 = 0;
r5 = 0;
r6 = 0;
r7 = 0;
a1 = a0 =0;
astat = R0;
R6.L = 0x8000;
R5.H = 0x8000;
// load acc with values;
R0.L = 0xc062;
R0.H = 0xffee;
A0.w = R0;
R0.L = 0xc52c;
A0.x = R0;
R0.L = 0x8d10;
R0.H = 0x34c;
A1.w = R0;
R0.L = 0xe10c;
A1.x = R0;
// load regs with values;
R0.L = 0xe844;
R0.H = 0x4aba;
R1.L = 0xa294;
R1.H = 0x52ea;
R2.L = 0xafda;
R2.H = 0x5c32;
// end load regs and acc;
R0.H = (A1 = R5.L * R6.H), R0.L = (A0 += R5.L * R6.H) (FU);
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY);
CHECKREG R0, 0xffff;
R0 = A1.w
CHECKREG R0, 0;
R0 = A1.x
CHECKREG R0, 0;
R0 = A0.w
CHECKREG R0, 0xffeec062;
R0 = A0.x
CHECKREG R0, 0x2c;
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY);
R4 = R6 +|- R5 , R3 = R6 -|+ R5;
CHECKREG R3, 0x80008000;
CHECKREG R4, 0x80008000;
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN);
A1 = R7.L * R2.L (M), A0 -= R7.L * R2.H (IS);
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN);
R7.H = R1.H * R3.L (TFU);
CHECKREG R7, 0x29750000;
P0 = ASTAT;
CHECKREG P0, (_VS|_AN);
R7.H = ( A1 -= R2.L * R5.H ), A0 = R2.L * R5.H;
CHECKREG R7, 0xafda0000;
R0 = A1.w
CHECKREG R0, 0xafda0000;
R0 = A1.x
CHECKREG R0, 0xffffffff;
R0 = A0.w
CHECKREG R0, 0x50260000;
R0 = A0.x
CHECKREG R0, 0x0;
P0 = ASTAT;
CHECKREG P0, (_VS|_AN);
R3 = R7.L * R6.H, R2 = R7.L * R6.H (IS);
CHECKREG R3, 0;
CHECKREG R2, 0;
P0 = ASTAT;
CHECKREG P0, (_VS|_AN);
R1.H = (A1 += R7.L * R4.H) (M), R1.L = (A0 = R7.H * R4.H) (FU);
CHECKREG R1, 0xafda57ed;
P0 = ASTAT;
R0 = A1.w
CHECKREG R0, 0xafda0000;
R0 = A1.x
CHECKREG R0, 0xffffffff;
R0 = A0.w
CHECKREG R0, 0x57ed0000;
R0 = A0.x
CHECKREG R0, 0x0;
CHECKREG P0, (_VS|_AN);
R3 = R6.H * R5.L (FU);
CHECKREG R3, 0;
P0 = ASTAT;
CHECKREG P0, (_VS|_AN);
R5.H = ( A1 += R3.L * R1.L ) (M), A0 -= R3.H * R1.H (ISS2);
CHECKREG R5, 0x80000000;
R0 = A1.w
CHECKREG R0, 0xafda0000;
R0 = A1.x
CHECKREG R0, 0xffffffff;
R0 = A0.w
CHECKREG R0, 0x57ed0000;
R0 = A0.x
CHECKREG R0, 0x0;
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN);
R3 = R3 +|- R5 , R6 = R3 -|+ R5 (CO);
CHECKREG R3, 0x80000000;
CHECKREG R6, 0x00008000;
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
R7 = ( A1 += R4.L * R1.L ) (M), R6 = ( A0 += R4.L * R1.H );
R0 = A1.w
CHECKREG R0, 0x83e38000;
R0 = A1.x
CHECKREG R0, 0xffffffff;
R0 = A0.w
CHECKREG R0, 0xa8130000;
R0 = A0.x
CHECKREG R0, 0x0;
CHECKREG R6, 0x7fffffff
CHECKREG R7, 0x83e38000
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
IF CC P2 = R1;
R2.H = (A1 = R7.L * R5.H) (M), R2.L = (A0 = R7.L * R5.H) (ISS2);
CHECKREG R2, 0x80007fff
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
R3.H = R4.H * R2.H, R3.L = R4.L * R2.L (T);
CHECKREG R3, 0x7fff8001
P0 = ASTAT;
CHECKREG P0, (_VS|_V|_V_COPY|_AN|_AZ);
R7 = ( A1 = R7.H * R1.H ) (M), A0 -= R7.H * R1.H (FU);
CHECKREG R7, 0xaabe7c4e
P0 = ASTAT;
CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ);
R0.H = R7.L * R4.H (M), R0.L = R7.L * R4.H (TFU);
CHECKREG R0, 0x3e273e27
P0 = ASTAT;
CHECKREG P0, (_VS|_AV0S|_AV0|_AN|_AZ);
R5 = ( A1 = R7.L * R7.L ), R4 = ( A0 -= R7.H * R7.H ) (ISS2);
CHECKREG R5, 0x78b74f88
CHECKREG R4, 0xc73635f8
R0 = A1.w
CHECKREG R0, 0x3c5ba7c4;
R0 = A1.x
CHECKREG R0, 0x0;
R0 = A0.w
CHECKREG R0, 0xe39b1afc;
R0 = A0.x
CHECKREG R0, 0xffffffff;
R0 = ASTAT;
CHECKREG r0, (_VS|_AV0S|_AZ|_AN);
A0 = A0 >> 2;
R0 = ASTAT;
checkreg r0, (_VS|_AV0S);
R0 = A0.x;
DBGA (R0.L, 0x3f);
R0 = A0.w;
checkreg r0, 0xF8E6C6BF;
pass

29
sim/testsuite/sim/bfin/a1.s Normal file
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// check the imm7 bit constants bounds
# mach: bfin
.include "testutils.inc"
start
R0 = 63;
DBGA ( R0.L , 63 );
R0 = -64;
DBGA ( R0.L , 0xffc0 );
P0 = 63;
R0 = P0; DBGA ( R0.L , 63 );
P0 = -64;
R0 = P0; DBGA ( R0.L , 0xffc0 );
// check loading imm16 into h/l halves
R0.L = 0x1111;
DBGA ( R0.L , 0x1111 );
R0.H = 0x1111;
DBGA ( R0.H , 0x1111 );
P0.L = 0x2222;
R0 = P0; DBGA ( R0.L , 0x2222 );
P0.H = 0x2222;
R0 = P0; DBGA ( R0.H , 0x2222 );
pass

176
sim/testsuite/sim/bfin/a10.s Normal file
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// ALU test program.
// Test dual 16 bit MAX, MIN, ABS instructions
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
// MAX
// first operand is larger, so AN=0
R0.L = 0x0001;
R0.H = 0x0002;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0002 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// second operand is larger
R0.L = 0x0000;
R0.H = 0x0000;
R1.L = 0x0001;
R1.H = 0x0022;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0022 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// one operand larger, one smaller.
R0.L = 0x000a;
R0.H = 0x0000;
R1.L = 0x0001;
R1.H = 0x0022;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x000a );
DBGA ( R7.H , 0x0022 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x8001;
R0.H = 0xffff;
R1.L = 0x8000;
R1.H = 0x0022;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x8001 );
DBGA ( R7.H , 0x0022 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x8000;
R0.H = 0xffff;
R1.L = 0x8000;
R1.H = 0x0022;
R7 = MAX ( R0 , R1 ) (V);
DBGA ( R7.L , 0x8000 );
DBGA ( R7.H , 0x0022 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// MIN
// second operand is smaller
R0.L = 0x0001;
R0.H = 0x0004;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MIN ( R0 , R1 ) (V);
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// first operand is smaller
R0.L = 0xffff;
R0.H = 0x8001;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MIN ( R0 , R1 ) (V);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x8001 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// one of each
R0.L = 0xffff;
R0.H = 0x0034;
R1.L = 0x0999;
R1.H = 0x0010;
R7 = MIN ( R0 , R1 ) (V);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x0010 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xffff;
R0.H = 0x0010;
R1.L = 0x0999;
R1.H = 0x0010;
R7 = MIN ( R0 , R1 ) (V);
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x0010 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// ABS
R0.L = 0x0001;
R0.H = 0x8001;
R7 = ABS R0 (V);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x7fff );
_DBG ASTAT;
R6 = ASTAT;
_DBG R6;
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = VS; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0001;
R0.H = 0x8000;
R7 = ABS R0 (V);
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = VS; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0000;
R0.H = 0xffff;
R7 = ABS R0 (V);
_DBG R7;
_DBG ASTAT;
R6 = ASTAT;
_DBG R6;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0001 );
CC = VS; R6 = CC; DBGA ( R6.L, 0x1 );
CC = AZ; R6 = CC; DBGA ( R6.L, 0x1 );
pass

386
sim/testsuite/sim/bfin/a11.S Normal file
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// Test ALU RND RND12 RND20
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
R7 = 0;
ASTAT = R7;
// 7ffffff0
// + 00008000
// -> 7fff0000
R0 = 0xfff0 (Z);
R0.H = 0x7fff;
R7.L = R0 (RND);
R0 = ASTAT;
CHECKREG R7, 0x7fff;
CHECKREG R0, (_VS|_V|_V_COPY);
// 7ffffff0
// + 00008000
// -> 7fff0000
R0.L = 0xfff0;
R0.H = 0x7fff;
R7.H = R0 (RND);
R0 = ASTAT;
CHECKREG R7, 0x7fff7fff;
CHECKREG R0, (_VS|_V|_V_COPY);
// 7ff0fff0
// + 00008000
// -> 7ff10000
R0.L = 0xfff0;
R0.H = 0x7ff0;
R7.L = R0 (RND);
R0 = ASTAT;
CHECKREG R7, 0x7fff7ff1
CHECKREG R0, (_VS);
// 7ff0fff0
// + 00008000
// -> 7ff10000
// 7ff0fff0
// + 8000
// -> 7ff1
R0.L = 0xfff0;
R0.H = 0x7ff0;
R7.H = R0 (RND);
R0 = ASTAT;
CHECKREG R7, 0x7ff17ff1
CHECKREG R0, (_VS);
// fffffff0
// + 00008000
// -> 00000000
R0.L = 0xfff0;
R0.H = 0xffff;
R7.L = R0 (RND);
R0 = ASTAT;
CHECKREG R7, 0x7ff10000;
CHECKREG R0, (_VS|_AZ);
// fffffff0
// + 00008000
// -> 00000000
R0.L = 0xfff0;
R0.H = 0xffff;
R7.H = R0 (RND);
R0 = ASTAT;
DBGA ( R7.H , 0 );
CHECKREG R0, (_VS|_AZ);
// 00fffff0
// + 00008000
// -> 0100
R0.L = 0xfff0;
R0.H = 0x00ff;
R7.L = R0 (RND);
R0 = ASTAT;
DBGA ( R7.L , 0x0100 );
CHECKREG R0, (_VS);
// RND12
// 07ffe000
// + 00000000
// = 07ffe000
// + 00000800
// -> 7ffe
R0.L = 0xe000;
R0.H = 0x07ff;
R1 = 0x0000 (Z);
R1.H = 0x0000;
R7.L = R0 + R1 (RND12);
R0 = ASTAT;
DBGA ( R7.L , 0x7ffe );
CHECKREG R0, (_VS);
// 07ffff00
// + 00000000
// = 07ffff00
// + 00000800
// -> 7fff
R0.L = 0xff00;
R0.H = 0x07ff;
R1.L = 0x0000;
R1.H = 0x0000;
R7.L = R0 + R1 (RND12);
R0 = ASTAT;
DBGA ( R7.L , 0x7fff );
CHECKREG R0, (_VS|_V|_V_COPY);
// 07fffc00
// + 00000f00
// = 08000b00
// + 00000800
// -> 7fff
R0.L = 0xfc00;
R0.H = 0x07ff;
R1.L = 0x0f00;
R1.H = 0x0000;
R7.L = R0 + R1 (RND12);
R0 = ASTAT;
DBGA ( R7.L , 0x7fff );
CHECKREG R0, (_VS|_V|_V_COPY);
// 07ff c000
// + 0000 1000
// = 07ff d000
// + 0000 0800
// -> 7ff d
R0.L = 0xc000;
R0.H = 0x07ff;
R1.L = 0x1000;
R1.H = 0x0000;
_DBG ASTAT;
R7.L = R0 + R1 (RND12);
_DBG ASTAT;
R0 = ASTAT;
_DBG R0;
DBGA ( R7.L , 0x7ffd );
CHECKREG R0, (_VS);
// ffff ffea
// + 07ff fe00
// = 107ff fdea
// + 0000 0800
// -> 7ff f
R0.L = 0xffea;
R0.H = 0xffff;
R1.L = 0xfe00;
R1.H = 0x07ff;
_DBG ASTAT;
R7.L = R0 + R1 (RND12);
_DBG ASTAT;
R0 = ASTAT;
_DBG R0;
DBGA ( R7.L , 0x7fff );
CHECKREG R0, (_VS|_V|_V_COPY);
// Small negative plus small negative should give zero
// ffff ffff
// + ffff ffff
// + 0000 0800
// -> 000 0
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0xffff;
R1.H = 0xffff;
_DBG ASTAT;
R7.L = R0 + R1 (RND12);
R0 = ASTAT;
_DBG R0;
DBGA ( R7.L , 0x0000 );
CHECKREG R0, (_VS|_AZ);
// Small negative minus small positive should give zero
// ffff ffff
// + 0000 0001
// - 0000 0800
// -> 000 0
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0x0001;
R1.H = 0x0000;
R7.L = R0 - R1 (RND12);
R0 = ASTAT;
DBGA ( R7.L , 0x0000 );
CHECKREG R0, (_VS|_AZ);
// Large positive plus large positive should give maxpos
// 07ff ffff
// + 07ff ffff
// + 0000 0800
// -> 7ff f
R0.L = 0xffff;
R0.H = 0x07ff;
R1.L = 0xffff;
R1.H = 0x07ff;
R7.L = R0 + R1 (RND12);
R0 = ASTAT;
DBGA ( R7.L , 0x7fff );
CHECKREG R0, (_VS|_V|_V_COPY);
// Large negative plus large negative should give maxneg
// 0800 0000
// + 0800 0000
// + 0000 0800
// -> 800 0
R0.L = 0x0000;
R0.H = 0x0800;
R1.L = 0x0000;
R1.H = 0x0800;
R7.L = R0 + R1 (RND12);
R0 = ASTAT;
DBGA ( R7.L , 0x7fff );
CHECKREG R0, (_VS|_V|_V_COPY);
// Large positive minus large negative should give maxpos
// 07ff ffff
// - 0800 0000
// + 0000 0800
// -> 800 0
R0.L = 0xffff;
R0.H = 0x07ff;
R1.L = 0x0000;
R1.H = 0x0800;
R7.L = R0 - R1 (RND12);
R0 = ASTAT;
_DBG ASTAT;
DBGA ( R7.L , 0x0 );
CHECKREG R0, (_VS|_AZ);
// Large negative minus large positive should give maxneg
// 0800 0000
// - 07ff ffff
// + 0000 0800
// -> 800 0
R0.L = 0x0000;
R0.H = 0x0800;
R1.L = 0xffff;
R1.H = 0x07ff;
R7.L = R0 - R1 (RND12);
R0 = ASTAT;
_DBG ASTAT;
DBGA ( R7.L , 0x0000 );
CHECKREG R0, (_VS|_AZ);
// cef4 3ed6
// - 56f4 417a
// + 0000 0800
// -> 800 0
R0.L = 0x3ed6;
R0.H = 0xcef4;
R1.L = 0x417a;
R1.H = 0x56f4;
R7.L = R0 - R1 (RND12);
R0 = ASTAT;
DBGA ( R7.L , 0x8000 );
CHECKREG R0, (_VS|_V|_V_COPY|_AN);
// RND20
// 00ff 0000
// + 0000 0000
// + 0008 0000
// ->0010
R0.L = 0x0000;
R0.H = 0x00ff;
R1.L = 0x0000;
R1.H = 0x0000;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0x0010 );
CHECKREG R0, (_VS);
// 00f0 0000
// + 000f 0000
// + 0008 0000
// ->0010
R0.L = 0x0000;
R0.H = 0x00f0;
R1.L = 0x0000;
R1.H = 0x000f;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0x0010 );
CHECKREG R0, (_VS);
// 7ff0 0000
// + 0000 0000
// + 0008 0000
// ->07ff
R0.L = 0x0000;
R0.H = 0x7ff0;
R1.L = 0x0000;
R1.H = 0x0000;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0x07ff );
CHECKREG R0, (_VS);
// 7fff 0000
// + 0000 0000
// + 0008 0000
// ->0800
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0x0000;
R1.H = 0x0000;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0x0800 );
CHECKREG R0, (_VS);
// ffff 0000
// + 0000 0000
// + 0008 0000
// ->0000
R0.L = 0x0000;
R0.H = 0xffff;
R1.L = 0x0000;
R1.H = 0x0000;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0x0000 );
DBGA ( R0.H , 0x0200 );
DBGA ( R0.L , 0x0001 );
// ff00 0000
// + 0010 0000
// + 0008 0000
// ->fff1
R0.L = 0x0000;
R0.H = 0xff00;
R1.L = 0x0000;
R1.H = 0x0010;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0xfff1 );
CHECKREG R0, (_VS|_AN);
// ff00 0000
// + 0018 0000
// + 0008 0000
// ->fff2
R0.L = 0x0000;
R0.H = 0xff00;
R1.L = 0x0000;
R1.H = 0x0018;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0xfff2 );
CHECKREG R0, (_VS|_AN);
// Small negative plus small negative should give zero
// ffff ffff
// + ffff ffff
// + 0008 0000
// ->0000
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0xffff;
R1.H = 0xffff;
R7.L = R0 + R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0x0000 );
CHECKREG R0, (_VS|_AZ);
// Small negative minus small positive should give zero
// ffff ffff
// + 0000 0010
// + 0008 0000
// ->0000
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0x0010;
R1.H = 0x0000;
R7.L = R0 - R1 (RND20);
R0 = ASTAT;
DBGA ( R7.L , 0x0000 );
CHECKREG R0, (_VS|_AZ);
pass

40
sim/testsuite/sim/bfin/a12.s Normal file
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@ -0,0 +1,40 @@
// Test SAA
# mach: bfin
.include "testutils.inc"
start
I0 = 0;
I1 = 0;
imm32 R0, 0x04030201;
imm32 R2, 0x04030201;
A1 = A0 = 0;
saa(r1:0,r3:2);
R0 = A0.w;
R1 = A1.w;
CHECKREG R0, 0;
CHECKREG R1, 0;
imm32 R0, 0x00000201;
imm32 R2, 0x00020102;
A1 = A0 = 0;
saa(r1:0,r3:2);
saa(r1:0,r3:2);
saa(r1:0,r3:2);
R0 = A0.w;
R1 = A1.w;
CHECKREG R0, 0x00030003;
CHECKREG R1, 0x00000006;
imm32 R0, 0x000300ff;
imm32 R2, 0x0001ff00;
A1 = A0 = 0;
saa(r1:0,r3:2);
saa(r1:0,r3:2);
R0 = A0.w;
R1 = A1.w;
CHECKREG R0, 0x1fe01fe;
CHECKREG R1, 0x0000004;
pass

179
sim/testsuite/sim/bfin/a2.s Normal file
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@ -0,0 +1,179 @@
# mach: bfin
.include "testutils.inc"
start
loadsym P0, middle;
R0 = [ P0 + 0 ]; DBGA ( R0.L , 50 );
R0 = [ P0 + 4 ]; DBGA ( R0.L , 51 );
R0 = [ P0 + 8 ]; DBGA ( R0.L , 52 );
R0 = [ P0 + 12 ]; DBGA ( R0.L , 53 );
R0 = [ P0 + 16 ]; DBGA ( R0.L , 54 );
R0 = [ P0 + 20 ]; DBGA ( R0.L , 55 );
R0 = [ P0 + 24 ]; DBGA ( R0.L , 56 );
R0 = [ P0 + 28 ]; DBGA ( R0.L , 57 );
R0 = [ P0 + -4 ]; DBGA ( R0.L , 49 );
R0 = [ P0 + -8 ]; DBGA ( R0.L , 48 );
R0 = [ P0 + -12 ]; DBGA ( R0.L , 47 );
R0 = [ P0 + -16 ]; DBGA ( R0.L , 46 );
R0 = [ P0 + -20 ]; DBGA ( R0.L , 45 );
R0 = [ P0 + -24 ]; DBGA ( R0.L , 44 );
R0 = [ P0 + -28 ]; DBGA ( R0.L , 43 );
R0 = [ P0 + -32 ]; DBGA ( R0.L , 42 );
FP = P0;
R0 = [ FP + 0 ]; DBGA ( R0.L , 50 );
R0 = [ FP + 4 ]; DBGA ( R0.L , 51 );
R0 = [ FP + 8 ]; DBGA ( R0.L , 52 );
R0 = [ FP + 12 ]; DBGA ( R0.L , 53 );
R0 = [ FP + 16 ]; DBGA ( R0.L , 54 );
R0 = [ FP + 20 ]; DBGA ( R0.L , 55 );
R0 = [ FP + 24 ]; DBGA ( R0.L , 56 );
R0 = [ FP + 28 ]; DBGA ( R0.L , 57 );
R0 = [ FP + 32 ]; DBGA ( R0.L , 58 );
R0 = [ FP + 36 ]; DBGA ( R0.L , 59 );
R0 = [ FP + 40 ]; DBGA ( R0.L , 60 );
R0 = [ FP + 44 ]; DBGA ( R0.L , 61 );
R0 = [ FP + 48 ]; DBGA ( R0.L , 62 );
R0 = [ FP + 52 ]; DBGA ( R0.L , 63 );
R0 = [ FP + 56 ]; DBGA ( R0.L , 64 );
R0 = [ FP + 60 ]; DBGA ( R0.L , 65 );
R0 = [ FP + -4 ]; DBGA ( R0.L , 49 );
R0 = [ FP + -8 ]; DBGA ( R0.L , 48 );
R0 = [ FP + -12 ]; DBGA ( R0.L , 47 );
R0 = [ FP + -16 ]; DBGA ( R0.L , 46 );
R0 = [ FP + -20 ]; DBGA ( R0.L , 45 );
R0 = [ FP + -24 ]; DBGA ( R0.L , 44 );
R0 = [ FP + -28 ]; DBGA ( R0.L , 43 );
R0 = [ FP + -32 ]; DBGA ( R0.L , 42 );
R0 = [ FP + -36 ]; DBGA ( R0.L , 41 );
R0 = [ FP + -40 ]; DBGA ( R0.L , 40 );
R0 = [ FP + -44 ]; DBGA ( R0.L , 39 );
R0 = [ FP + -48 ]; DBGA ( R0.L , 38 );
R0 = [ FP + -52 ]; DBGA ( R0.L , 37 );
R0 = [ FP + -56 ]; DBGA ( R0.L , 36 );
R0 = [ FP + -60 ]; DBGA ( R0.L , 35 );
R0 = [ FP + -64 ]; DBGA ( R0.L , 34 );
R0 = [ FP + -68 ]; DBGA ( R0.L , 33 );
R0 = [ FP + -72 ]; DBGA ( R0.L , 32 );
R0 = [ FP + -76 ]; DBGA ( R0.L , 31 );
R0 = [ FP + -80 ]; DBGA ( R0.L , 30 );
R0 = [ FP + -84 ]; DBGA ( R0.L , 29 );
R0 = [ FP + -88 ]; DBGA ( R0.L , 28 );
R0 = [ FP + -92 ]; DBGA ( R0.L , 27 );
R0 = [ FP + -96 ]; DBGA ( R0.L , 26 );
R0 = [ FP + -100 ]; DBGA ( R0.L , 25 );
R0 = [ FP + -104 ]; DBGA ( R0.L , 24 );
R0 = [ FP + -108 ]; DBGA ( R0.L , 23 );
R0 = [ FP + -112 ]; DBGA ( R0.L , 22 );
R0 = [ FP + -116 ]; DBGA ( R0.L , 21 );
pass
.data
base:
.dd 0
.dd 1
.dd 2
.dd 3
.dd 4
.dd 5
.dd 6
.dd 7
.dd 8
.dd 9
.dd 10
.dd 11
.dd 12
.dd 13
.dd 14
.dd 15
.dd 16
.dd 17
.dd 18
.dd 19
.dd 20
.dd 21
.dd 22
.dd 23
.dd 24
.dd 25
.dd 26
.dd 27
.dd 28
.dd 29
.dd 30
.dd 31
.dd 32
.dd 33
.dd 34
.dd 35
.dd 36
.dd 37
.dd 38
.dd 39
.dd 40
.dd 41
.dd 42
.dd 43
.dd 44
.dd 45
.dd 46
.dd 47
.dd 48
.dd 49
middle:
.dd 50
.dd 51
.dd 52
.dd 53
.dd 54
.dd 55
.dd 56
.dd 57
.dd 58
.dd 59
.dd 60
.dd 61
.dd 62
.dd 63
.dd 64
.dd 65
.dd 66
.dd 67
.dd 68
.dd 69
.dd 70
.dd 71
.dd 72
.dd 73
.dd 74
.dd 75
.dd 76
.dd 77
.dd 78
.dd 79
.dd 80
.dd 81
.dd 82
.dd 83
.dd 84
.dd 85
.dd 86
.dd 87
.dd 88
.dd 89
.dd 90
.dd 91
.dd 92
.dd 93
.dd 94
.dd 95
.dd 96
.dd 97
.dd 98
.dd 99

68
sim/testsuite/sim/bfin/a20.S Normal file
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# mach: bfin
#include "test.h"
.include "testutils.inc"
start
R1 = 0;
ASTAT = R1;
R1.H = -32768;
R2 = 0;
R2.H = -32768;
R3 = R1 +|+ R2;
_DBG ASTAT;
R7 = ASTAT;
CHECKREG R7, (_VS|_V|_V_COPY|_AC1|_AZ);
R0.L = 32767;
R0.H = 32767;
R0 = R0 +|- R0;
_DBG ASTAT;
R7 = ASTAT;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN|_AZ)
R0 = 0;
ASTAT = R0;
_DBG ASTAT;
R7 = ASTAT;
CHECKREG R7, (_UNSET)
R1.L = -1;
R1.H = 0x7fff;
R0 = ABS R1;
_DBG R0;
_DBG ASTAT;
R7 = ASTAT;
CHECKREG R7, (_UNSET)
R1=0;
R1.H = 0x8000;
_DBG R1;
R0 = ABS R1;
_DBG R0;
_DBG ASTAT;
R7 = ASTAT;
CHECKREG R7, (_VS|_V|_V_COPY)
R0 = 0;
ASTAT = R0;
R1.L = 32767;
R1.H = 32767;
R0 = R1 +|+ R1 (CO);
_DBG R0;
_DBG ASTAT;
R7 = ASTAT;
CHECKREG R7, (_VS|_V|_V_COPY|_AN)
R0.L = -1;
R0.H = 32766;
R1.L = -1;
R1.H = -32768;
R0 = PACK( R0.H , R1.L );
_DBG R0;
R7 = ASTAT;
CHECKREG R7, (_VS|_V|_V_COPY|_AN)
pass

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sim/testsuite/sim/bfin/a21.s Normal file
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// Test ALU RND RND12 RND20
# mach: bfin
.include "testutils.inc"
start
// positive saturation
R0 = 0xffffffff;
A0.w = R0;
A1.w = R0;
R0 = 0x7f (X);
A0.x = R0;
A1.x = R0;
R3 = A1 + A0, R4 = A1 - A0 (S);
DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff );
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 );
// neg saturation
R0 = 0;
A0.w = R0;
A1.w = R0;
R0 = 0x80 (X);
A0.x = R0;
A1.x = R0;
R3 = A1 + A0, R4 = A1 - A0 (S);
DBGA ( R3.H , 0x8000 ); DBGA ( R3.L , 0x0000 );
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 );
// positive saturation
R0 = 0xfffffff0;
A0.w = R0;
A1.w = R0;
R0 = 0x01;
A0.x = R0;
A1.x = R0;
R3 = A1 + A0, R4 = A1 - A0 (S);
DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff );
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 );
// no sat
R0 = 0xfffffff0;
A0.w = R0;
A1.w = R0;
R0 = 0x01;
A0.x = R0;
A1.x = R0;
R3 = A1 + A0, R4 = A1 - A0 (NS);
DBGA ( R3.H , 0xffff ); DBGA ( R3.L , 0xffe0 );
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0000 );
// add and sub +1 -1
R0 = 0x00000001;
A0.w = R0;
R0 = 0xffffffff;
A1.w = R0;
R0 = 0;
A0.x = R0;
R0 = 0xff (X);
A1.x = R0;
R3 = A1 + A0, R4 = A1 - A0 (NS);
DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 ); // 0
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe ); // -2
// should get the same with saturation
R3 = A1 + A0, R4 = A1 - A0 (S);
DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 ); // 0
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe ); // -2
// add and sub -1 +1 but with reverse order of A0 A1
R0 = 0x00000001;
A0.w = R0;
R0 = 0xffffffff;
A1.w = R0;
R0 = 0;
A0.x = R0;
R0 = 0xff (X);
A1.x = R0;
R3 = A0 + A1, R4 = A0 - A1 (NS);
DBGA ( R3.H , 0x0000 ); DBGA ( R3.L , 0x0000 );
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0002 );
pass

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sim/testsuite/sim/bfin/a22.s Normal file
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// Test ALU NEG accumulators
# mach: bfin
.include "testutils.inc"
start
R0 = 0xffffffff;
A0.w = R0;
R0 = 0x7f (X);
A0.x = R0;
A0 = - A0;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff80 );
R0 = 0x1;
A0.w = R0;
R0 = 0x0;
A0.x = R0;
A0 = - A0;
R4 = A0.w;
R5 = A0.x;
_DBG A0;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xffff );
R0 = 0xffffffff;
A0.w = R0;
R0 = 0xff (X);
A0.x = R0;
A0 = - A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 );
R0 = 0x00000000;
A0.w = R0;
R0 = 0x80 (X);
A0.x = R0;
A0 = - A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
// NEG NEG
R0 = 0x00000000;
A0.w = R0;
R0 = 0x80 (X);
A0.x = R0;
R0 = 0xffffffff;
A1.w = R0;
R0 = 0x7f (X);
A1.x = R0;
A1 = - A1, A0 = - A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
R4 = A1.w;
R5 = A1.x;
_DBG A1;
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 );
DBGA ( R5.H , 0xffff ); DBGA ( R5.L , 0xff80 );
// NEG NEG register
R0.L = 0x0001;
R0.H = 0x8000;
R3 = - R0 (V);
DBGA ( R3.H , 0x7fff ); DBGA ( R3.L , 0xffff );
_DBG ASTAT;
pass

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sim/testsuite/sim/bfin/a23.s Normal file
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// Test ALU ABS accumulators
# mach: bfin
.include "testutils.inc"
start
R0 = 0x00000000;
A0.w = R0;
R0 = 0x80 (X);
A0.x = R0;
A0 = ABS A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
R0 = 0x00000001;
A0.w = R0;
R0 = 0x80 (X);
A0.x = R0;
A0 = ABS A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
R0 = 0xffffffff;
A0.w = R0;
R0 = 0xff (X);
A0.x = R0;
A0 = ABS A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x0001 );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0000 );
R0 = 0xfffffff0;
A0.w = R0;
R0 = 0x7f (X);
A0.x = R0;
A0 = ABS A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfff0 );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
R0 = 0x00000000;
A0.w = R0;
R0 = 0x80 (X);
A0.x = R0;
A1 = ABS A0;
R4 = A1.w;
R5 = A1.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
R0 = 0x00000000;
A0.w = R0;
R0 = 0x80 (X);
A0.x = R0;
R0 = 0x00000002;
A1.w = R0;
R0 = 0x80 (X);
A1.x = R0;
A1 = ABS A1, A0 = ABS A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xffff );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
R4 = A1.w;
R5 = A1.x;
DBGA ( R4.H , 0xffff ); DBGA ( R4.L , 0xfffe );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x007f );
pass

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sim/testsuite/sim/bfin/a24.s Normal file
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# mach: bfin
.include "testutils.inc"
start
R0 = 0x1111 (X);
R0.H = 0x1111;
A0.x = R0;
R1 = A0.x;
DBGA ( R1.L , 0x11 );
DBGA ( R1.H , 0x0 );
pass

28
sim/testsuite/sim/bfin/a25.s Normal file
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# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0.L = 0x01;
A0.x = R0;
//A0 = 0x0100000000
//A1 = 0x0000000000
R4.L = 0x2d1a;
R4.H = 0x32e0;
A1.x = R4;
//A1 = 0x1a00000000
A0.w = A1.x;
_DBG A0;
R4 = A0.w;
R5 = A0.x;
DBGA ( R4.H , 0x0000 ); DBGA ( R4.L , 0x001a );
DBGA ( R5.H , 0x0000 ); DBGA ( R5.L , 0x0001 );
pass

72
sim/testsuite/sim/bfin/a26.s Normal file
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// Test ALU SEARCH instruction
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
R0 = 4;
R1 = 5;
A1 = A0 = 0;
R2.L = 0x0001;
R2.H = 0xffff;
loadsym P0, foo;
( R1 , R0 ) = SEARCH R2 (GT);
// R0 should be the pointer
R7 = P0;
CC = R0 == R7;
if !CC JUMP _fail;
_DBG R1; // does not change
DBGA ( R1.H , 0 ); DBGA ( R1.L , 0x5 );
_DBG A0; // changes
R0 = A0.w;
DBGA ( R0.H , 0 ); DBGA ( R0.L , 0x1 );
_DBG A1; // does not change
R0 = A1.w;
DBGA ( R0.H , 0 ); DBGA ( R0.L , 0 );
R0 = 4;
R1 = 5;
A1 = A0 = 0;
R2.L = 0x0000;
R2.H = 0xffff;
loadsym p0, foo;
( R1 , R0 ) = SEARCH R2 (LT);
_DBG R0; // no change
DBGA ( R0.H , 0 ); DBGA ( R0.L , 4 );
_DBG R1; // change
R7 = P0;
CC = R1 == R7;
if !CC JUMP _fail;
_DBG A0;
R0 = A0.w;
DBGA ( R0.H , 0 ); DBGA ( R0.L , 0 );
_DBG A1;
R0 = A1.w;
DBGA ( R0.H , 0xffff ); DBGA ( R0.L , 0xffff );
pass
_fail:
fail;
.data
foo:
.space (0x100)

313
sim/testsuite/sim/bfin/a3.s Normal file
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# mach: bfin
.include "testutils.inc"
start
loadsym P1, middle;
R0 = W [ P1 + -2 ] (Z); DBGA ( R0.L , 49 );
R0 = W [ P1 + -4 ] (Z); DBGA ( R0.L , 48 );
R0 = W [ P1 + -6 ] (Z); DBGA ( R0.L , 47 );
R0 = W [ P1 + -8 ] (Z); DBGA ( R0.L , 46 );
R0 = W [ P1 + -10 ] (Z); DBGA ( R0.L , 45 );
R0 = W [ P1 + -12 ] (Z); DBGA ( R0.L , 44 );
R0 = W [ P1 + -14 ] (Z); DBGA ( R0.L , 43 );
R0 = W [ P1 + -16 ] (Z); DBGA ( R0.L , 42 );
R0 = W [ P1 + -18 ] (Z); DBGA ( R0.L , 41 );
R0 = W [ P1 + -20 ] (Z); DBGA ( R0.L , 40 );
R0 = W [ P1 + -22 ] (Z); DBGA ( R0.L , 39 );
R0 = W [ P1 + -24 ] (Z); DBGA ( R0.L , 38 );
R0 = W [ P1 + -26 ] (Z); DBGA ( R0.L , 37 );
R0 = W [ P1 + -28 ] (Z); DBGA ( R0.L , 36 );
R0 = W [ P1 + -30 ] (Z); DBGA ( R0.L , 35 );
R0 = W [ P1 + -32 ] (Z); DBGA ( R0.L , 34 );
R0 = W [ P1 + -34 ] (Z); DBGA ( R0.L , 33 );
R0 = W [ P1 + -36 ] (Z); DBGA ( R0.L , 32 );
R0 = W [ P1 + -38 ] (Z); DBGA ( R0.L , 31 );
R0 = W [ P1 + -40 ] (Z); DBGA ( R0.L , 30 );
R0 = W [ P1 + -42 ] (Z); DBGA ( R0.L , 29 );
R0 = W [ P1 + -44 ] (Z); DBGA ( R0.L , 28 );
R0 = W [ P1 + -46 ] (Z); DBGA ( R0.L , 27 );
R0 = W [ P1 + -48 ] (Z); DBGA ( R0.L , 26 );
R0 = W [ P1 + -50 ] (Z); DBGA ( R0.L , 25 );
R0 = W [ P1 + -52 ] (Z); DBGA ( R0.L , 24 );
R0 = W [ P1 + -54 ] (Z); DBGA ( R0.L , 23 );
R0 = W [ P1 + -56 ] (Z); DBGA ( R0.L , 22 );
R0 = W [ P1 + -58 ] (Z); DBGA ( R0.L , 21 );
R0 = W [ P1 + -60 ] (Z); DBGA ( R0.L , 20 );
R0 = W [ P1 + -62 ] (Z); DBGA ( R0.L , 19 );
R0 = W [ P1 + -64 ] (Z); DBGA ( R0.L , 18 );
R0 = W [ P1 + -66 ] (Z); DBGA ( R0.L , 17 );
R0 = W [ P1 + -68 ] (Z); DBGA ( R0.L , 16 );
R0 = W [ P1 + -70 ] (Z); DBGA ( R0.L , 15 );
R0 = W [ P1 + -72 ] (Z); DBGA ( R0.L , 14 );
R0 = W [ P1 + -74 ] (Z); DBGA ( R0.L , 13 );
R0 = W [ P1 + -76 ] (Z); DBGA ( R0.L , 12 );
R0 = W [ P1 + -78 ] (Z); DBGA ( R0.L , 11 );
R0 = W [ P1 + -80 ] (Z); DBGA ( R0.L , 10 );
R0 = W [ P1 + -82 ] (Z); DBGA ( R0.L , 9 );
R0 = W [ P1 + -84 ] (Z); DBGA ( R0.L , 8 );
R0 = W [ P1 + -86 ] (Z); DBGA ( R0.L , 7 );
R0 = W [ P1 + -88 ] (Z); DBGA ( R0.L , 6 );
R0 = W [ P1 + -90 ] (Z); DBGA ( R0.L , 5 );
R0 = W [ P1 + -92 ] (Z); DBGA ( R0.L , 4 );
R0 = W [ P1 + -94 ] (Z); DBGA ( R0.L , 3 );
R0 = W [ P1 + -96 ] (Z); DBGA ( R0.L , 2 );
R0 = W [ P1 + -98 ] (Z); DBGA ( R0.L , 1 );
R0 = W [ P1 + 0 ] (Z); DBGA ( R0.L , 50 );
R0 = W [ P1 + 2 ] (Z); DBGA ( R0.L , 51 );
R0 = W [ P1 + 4 ] (Z); DBGA ( R0.L , 52 );
R0 = W [ P1 + 6 ] (Z); DBGA ( R0.L , 53 );
R0 = W [ P1 + 8 ] (Z); DBGA ( R0.L , 54 );
R0 = W [ P1 + 10 ] (Z); DBGA ( R0.L , 55 );
R0 = W [ P1 + 12 ] (Z); DBGA ( R0.L , 56 );
R0 = W [ P1 + 14 ] (Z); DBGA ( R0.L , 57 );
R0 = W [ P1 + 16 ] (Z); DBGA ( R0.L , 58 );
R0 = W [ P1 + 18 ] (Z); DBGA ( R0.L , 59 );
R0 = W [ P1 + 20 ] (Z); DBGA ( R0.L , 60 );
R0 = W [ P1 + 22 ] (Z); DBGA ( R0.L , 61 );
R0 = W [ P1 + 24 ] (Z); DBGA ( R0.L , 62 );
R0 = W [ P1 + 26 ] (Z); DBGA ( R0.L , 63 );
R0 = W [ P1 + 28 ] (Z); DBGA ( R0.L , 64 );
R0 = W [ P1 + 30 ] (Z); DBGA ( R0.L , 65 );
R0 = W [ P1 + 32 ] (Z); DBGA ( R0.L , 66 );
R0 = W [ P1 + 34 ] (Z); DBGA ( R0.L , 67 );
R0 = W [ P1 + 36 ] (Z); DBGA ( R0.L , 68 );
R0 = W [ P1 + 38 ] (Z); DBGA ( R0.L , 69 );
R0 = W [ P1 + 40 ] (Z); DBGA ( R0.L , 70 );
R0 = W [ P1 + 42 ] (Z); DBGA ( R0.L , 71 );
R0 = W [ P1 + 44 ] (Z); DBGA ( R0.L , 72 );
R0 = W [ P1 + 46 ] (Z); DBGA ( R0.L , 73 );
R0 = W [ P1 + 48 ] (Z); DBGA ( R0.L , 74 );
R0 = W [ P1 + 50 ] (Z); DBGA ( R0.L , 75 );
R0 = W [ P1 + 52 ] (Z); DBGA ( R0.L , 76 );
R0 = W [ P1 + 54 ] (Z); DBGA ( R0.L , 77 );
R0 = W [ P1 + 56 ] (Z); DBGA ( R0.L , 78 );
R0 = W [ P1 + 58 ] (Z); DBGA ( R0.L , 79 );
R0 = W [ P1 + 60 ] (Z); DBGA ( R0.L , 80 );
R0 = W [ P1 + 62 ] (Z); DBGA ( R0.L , 81 );
R0 = W [ P1 + 64 ] (Z); DBGA ( R0.L , 82 );
R0 = W [ P1 + 66 ] (Z); DBGA ( R0.L , 83 );
R0 = W [ P1 + 68 ] (Z); DBGA ( R0.L , 84 );
R0 = W [ P1 + 70 ] (Z); DBGA ( R0.L , 85 );
R0 = W [ P1 + 72 ] (Z); DBGA ( R0.L , 86 );
R0 = W [ P1 + 74 ] (Z); DBGA ( R0.L , 87 );
R0 = W [ P1 + 76 ] (Z); DBGA ( R0.L , 88 );
R0 = W [ P1 + 78 ] (Z); DBGA ( R0.L , 89 );
R0 = W [ P1 + 80 ] (Z); DBGA ( R0.L , 90 );
R0 = W [ P1 + 82 ] (Z); DBGA ( R0.L , 91 );
R0 = W [ P1 + 84 ] (Z); DBGA ( R0.L , 92 );
R0 = W [ P1 + 86 ] (Z); DBGA ( R0.L , 93 );
R0 = W [ P1 + 88 ] (Z); DBGA ( R0.L , 94 );
R0 = W [ P1 + 90 ] (Z); DBGA ( R0.L , 95 );
R0 = W [ P1 + 92 ] (Z); DBGA ( R0.L , 96 );
R0 = W [ P1 + 94 ] (Z); DBGA ( R0.L , 97 );
R0 = W [ P1 + 96 ] (Z); DBGA ( R0.L , 98 );
R0 = W [ P1 + 98 ] (Z); DBGA ( R0.L , 99 );
FP = P1;
R0 = W [ FP + -2 ] (Z); DBGA ( R0.L , 49 );
R0 = W [ FP + -4 ] (Z); DBGA ( R0.L , 48 );
R0 = W [ FP + -6 ] (Z); DBGA ( R0.L , 47 );
R0 = W [ FP + -8 ] (Z); DBGA ( R0.L , 46 );
R0 = W [ FP + -10 ] (Z); DBGA ( R0.L , 45 );
R0 = W [ FP + -12 ] (Z); DBGA ( R0.L , 44 );
R0 = W [ FP + -14 ] (Z); DBGA ( R0.L , 43 );
R0 = W [ FP + -16 ] (Z); DBGA ( R0.L , 42 );
R0 = W [ FP + -18 ] (Z); DBGA ( R0.L , 41 );
R0 = W [ FP + -20 ] (Z); DBGA ( R0.L , 40 );
R0 = W [ FP + -22 ] (Z); DBGA ( R0.L , 39 );
R0 = W [ FP + -24 ] (Z); DBGA ( R0.L , 38 );
R0 = W [ FP + -26 ] (Z); DBGA ( R0.L , 37 );
R0 = W [ FP + -28 ] (Z); DBGA ( R0.L , 36 );
R0 = W [ FP + -30 ] (Z); DBGA ( R0.L , 35 );
R0 = W [ FP + -32 ] (Z); DBGA ( R0.L , 34 );
R0 = W [ FP + -34 ] (Z); DBGA ( R0.L , 33 );
R0 = W [ FP + -36 ] (Z); DBGA ( R0.L , 32 );
R0 = W [ FP + -38 ] (Z); DBGA ( R0.L , 31 );
R0 = W [ FP + -40 ] (Z); DBGA ( R0.L , 30 );
R0 = W [ FP + -42 ] (Z); DBGA ( R0.L , 29 );
R0 = W [ FP + -44 ] (Z); DBGA ( R0.L , 28 );
R0 = W [ FP + -46 ] (Z); DBGA ( R0.L , 27 );
R0 = W [ FP + -48 ] (Z); DBGA ( R0.L , 26 );
R0 = W [ FP + -50 ] (Z); DBGA ( R0.L , 25 );
R0 = W [ FP + -52 ] (Z); DBGA ( R0.L , 24 );
R0 = W [ FP + -54 ] (Z); DBGA ( R0.L , 23 );
R0 = W [ FP + -56 ] (Z); DBGA ( R0.L , 22 );
R0 = W [ FP + -58 ] (Z); DBGA ( R0.L , 21 );
R0 = W [ FP + -60 ] (Z); DBGA ( R0.L , 20 );
R0 = W [ FP + -62 ] (Z); DBGA ( R0.L , 19 );
R0 = W [ FP + -64 ] (Z); DBGA ( R0.L , 18 );
R0 = W [ FP + -66 ] (Z); DBGA ( R0.L , 17 );
R0 = W [ FP + -68 ] (Z); DBGA ( R0.L , 16 );
R0 = W [ FP + -70 ] (Z); DBGA ( R0.L , 15 );
R0 = W [ FP + -72 ] (Z); DBGA ( R0.L , 14 );
R0 = W [ FP + -74 ] (Z); DBGA ( R0.L , 13 );
R0 = W [ FP + -76 ] (Z); DBGA ( R0.L , 12 );
R0 = W [ FP + -78 ] (Z); DBGA ( R0.L , 11 );
R0 = W [ FP + -80 ] (Z); DBGA ( R0.L , 10 );
R0 = W [ FP + -82 ] (Z); DBGA ( R0.L , 9 );
R0 = W [ FP + -84 ] (Z); DBGA ( R0.L , 8 );
R0 = W [ FP + -86 ] (Z); DBGA ( R0.L , 7 );
R0 = W [ FP + -88 ] (Z); DBGA ( R0.L , 6 );
R0 = W [ FP + -90 ] (Z); DBGA ( R0.L , 5 );
R0 = W [ FP + -92 ] (Z); DBGA ( R0.L , 4 );
R0 = W [ FP + -94 ] (Z); DBGA ( R0.L , 3 );
R0 = W [ FP + -96 ] (Z); DBGA ( R0.L , 2 );
R0 = W [ FP + -98 ] (Z); DBGA ( R0.L , 1 );
R0 = W [ FP + 0 ] (Z); DBGA ( R0.L , 50 );
R0 = W [ FP + 2 ] (Z); DBGA ( R0.L , 51 );
R0 = W [ FP + 4 ] (Z); DBGA ( R0.L , 52 );
R0 = W [ FP + 6 ] (Z); DBGA ( R0.L , 53 );
R0 = W [ FP + 8 ] (Z); DBGA ( R0.L , 54 );
R0 = W [ FP + 10 ] (Z); DBGA ( R0.L , 55 );
R0 = W [ FP + 12 ] (Z); DBGA ( R0.L , 56 );
R0 = W [ FP + 14 ] (Z); DBGA ( R0.L , 57 );
R0 = W [ FP + 16 ] (Z); DBGA ( R0.L , 58 );
R0 = W [ FP + 18 ] (Z); DBGA ( R0.L , 59 );
R0 = W [ FP + 20 ] (Z); DBGA ( R0.L , 60 );
R0 = W [ FP + 22 ] (Z); DBGA ( R0.L , 61 );
R0 = W [ FP + 24 ] (Z); DBGA ( R0.L , 62 );
R0 = W [ FP + 26 ] (Z); DBGA ( R0.L , 63 );
R0 = W [ FP + 28 ] (Z); DBGA ( R0.L , 64 );
R0 = W [ FP + 30 ] (Z); DBGA ( R0.L , 65 );
R0 = W [ FP + 32 ] (Z); DBGA ( R0.L , 66 );
R0 = W [ FP + 34 ] (Z); DBGA ( R0.L , 67 );
R0 = W [ FP + 36 ] (Z); DBGA ( R0.L , 68 );
R0 = W [ FP + 38 ] (Z); DBGA ( R0.L , 69 );
R0 = W [ FP + 40 ] (Z); DBGA ( R0.L , 70 );
R0 = W [ FP + 42 ] (Z); DBGA ( R0.L , 71 );
R0 = W [ FP + 44 ] (Z); DBGA ( R0.L , 72 );
R0 = W [ FP + 46 ] (Z); DBGA ( R0.L , 73 );
R0 = W [ FP + 48 ] (Z); DBGA ( R0.L , 74 );
R0 = W [ FP + 50 ] (Z); DBGA ( R0.L , 75 );
R0 = W [ FP + 52 ] (Z); DBGA ( R0.L , 76 );
R0 = W [ FP + 54 ] (Z); DBGA ( R0.L , 77 );
R0 = W [ FP + 56 ] (Z); DBGA ( R0.L , 78 );
R0 = W [ FP + 58 ] (Z); DBGA ( R0.L , 79 );
R0 = W [ FP + 60 ] (Z); DBGA ( R0.L , 80 );
R0 = W [ FP + 62 ] (Z); DBGA ( R0.L , 81 );
R0 = W [ FP + 64 ] (Z); DBGA ( R0.L , 82 );
R0 = W [ FP + 66 ] (Z); DBGA ( R0.L , 83 );
R0 = W [ FP + 68 ] (Z); DBGA ( R0.L , 84 );
R0 = W [ FP + 70 ] (Z); DBGA ( R0.L , 85 );
R0 = W [ FP + 72 ] (Z); DBGA ( R0.L , 86 );
R0 = W [ FP + 74 ] (Z); DBGA ( R0.L , 87 );
R0 = W [ FP + 76 ] (Z); DBGA ( R0.L , 88 );
R0 = W [ FP + 78 ] (Z); DBGA ( R0.L , 89 );
R0 = W [ FP + 80 ] (Z); DBGA ( R0.L , 90 );
R0 = W [ FP + 82 ] (Z); DBGA ( R0.L , 91 );
R0 = W [ FP + 84 ] (Z); DBGA ( R0.L , 92 );
R0 = W [ FP + 86 ] (Z); DBGA ( R0.L , 93 );
R0 = W [ FP + 88 ] (Z); DBGA ( R0.L , 94 );
R0 = W [ FP + 90 ] (Z); DBGA ( R0.L , 95 );
R0 = W [ FP + 92 ] (Z); DBGA ( R0.L , 96 );
R0 = W [ FP + 94 ] (Z); DBGA ( R0.L , 97 );
R0 = W [ FP + 96 ] (Z); DBGA ( R0.L , 98 );
R0 = W [ FP + 98 ] (Z); DBGA ( R0.L , 99 );
pass
.data
.dw 0
.dw 1
.dw 2
.dw 3
.dw 4
.dw 5
.dw 6
.dw 7
.dw 8
.dw 9
.dw 10
.dw 11
.dw 12
.dw 13
.dw 14
.dw 15
.dw 16
.dw 17
.dw 18
.dw 19
.dw 20
.dw 21
.dw 22
.dw 23
.dw 24
.dw 25
.dw 26
.dw 27
.dw 28
.dw 29
.dw 30
.dw 31
.dw 32
.dw 33
.dw 34
.dw 35
.dw 36
.dw 37
.dw 38
.dw 39
.dw 40
.dw 41
.dw 42
.dw 43
.dw 44
.dw 45
.dw 46
.dw 47
.dw 48
.dw 49
middle:
.dw 50
.dw 51
.dw 52
.dw 53
.dw 54
.dw 55
.dw 56
.dw 57
.dw 58
.dw 59
.dw 60
.dw 61
.dw 62
.dw 63
.dw 64
.dw 65
.dw 66
.dw 67
.dw 68
.dw 69
.dw 70
.dw 71
.dw 72
.dw 73
.dw 74
.dw 75
.dw 76
.dw 77
.dw 78
.dw 79
.dw 80
.dw 81
.dw 82
.dw 83
.dw 84
.dw 85
.dw 86
.dw 87
.dw 88
.dw 89
.dw 90
.dw 91
.dw 92
.dw 93
.dw 94
.dw 95
.dw 96
.dw 97
.dw 98
.dw 99

55
sim/testsuite/sim/bfin/a30.s Normal file
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# mach: bfin
.include "testutils.inc"
start
R0.L = 0.5;
R0.H = 0.5;
R1.L = 0.5;
R1.H = 0.5;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
_DBGCMPLX R2;
_DBGCMPLX R3;
DBGA ( R2.L , 0.5 );
DBGA ( R2.H , 0.5 );
DBGA ( R3.L , 0 );
DBGA ( R3.H , 0 );
R1.L = 0.125;
R1.H = 0.125;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
_DBGCMPLX R2;
_DBGCMPLX R3;
DBGA ( R2.L , 0.3125 );
DBGA ( R2.H , 0.3125 );
DBGA ( R3.L , 0.1875 );
DBGA ( R3.H , 0.1875 );
R0 = R2 +|+ R3, R1 = R2 -|- R3 (S , ASR);
_DBGCMPLX R0;
_DBGCMPLX R1;
DBGA ( R0.L , 0.25 );
DBGA ( R0.H , 0.25 );
DBGA ( R1.L , 0.0625 );
DBGA ( R1.H , 0.0625 );
R0 = 1;
R0 <<= 15;
R1 = R0 << 16;
r0=r0 | r1;
R1 = R0;
R2 = R0 +|+ R1, R3 = R0 -|- R1 (S , ASR);
_DBGCMPLX R2;
_DBGCMPLX R3;
DBGA ( R0.L , 0x8000 );
DBGA ( R0.H , 0x8000 );
DBGA ( R1.L , 0x8000 );
DBGA ( R1.H , 0x8000 );
pass

36
sim/testsuite/sim/bfin/a4.s Normal file
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# Blackfin testcase for signbits
# mach: bfin
.include "testutils.inc"
start
xx:
R0 = 1;
CALL red;
JUMP.L aa;
.align 16
aa:
R0 = 2;
CALL red;
JUMP.S bb;
.align 16
bb:
R0 = 3;
CALL red;
JUMP.S ccd;
.align 16
red:
RTS;
.align 16
ccd:
R1 = 3 (Z);
CC = R0 == R1
if CC jump 1f;
fail
1:
pass

140
sim/testsuite/sim/bfin/a5.s Normal file
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// ALU test program.
// Test instructions
// rL4= L+L (r2,r3);
// rH4= L+H (r2,r3) S;
// rL4= L-L (r2,r3);
// rH4= L-H (r2,r3) S;
# mach: bfin
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
// overflow positive
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0x7fff;
R1.H = 0x0000;
R7 = 0;
ASTAT = R7;
R3.L = R0.H + R1.L (NS);
DBGA ( R3.L , 0xfffe );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// overflow negative
R0.L = 0xffff;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x8000;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.H = R0.L + R1.H (NS);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate positive
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0x7fff;
R1.H = 0x0000;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.L = R0.H + R1.L (S);
DBGA ( R3.L , 0x7fff );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// saturate negative
R0.L = 0xffff;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x8000;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.L = R0.L + R1.H (S);
DBGA ( R3.L , 0x8000 );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// overflow positive with subtraction
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0xffff;
R1.H = 0x0000;
R7 = 0;
ASTAT = R7;
R3.L = R0.H - R1.L (NS);
DBGA ( R3.L , 0x8000 );
DBGA ( R3.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// overflow negative with subtraction
R0.L = 0x8000;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x0001;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.H = R0.L - R1.H (NS);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// saturate positive with subtraction
R0.L = 0x0000;
R0.H = 0x7fff;
R1.L = 0xffff;
R1.H = 0x0000;
R7 = 0;
ASTAT = R7;
R3.H = R0.H - R1.L (S);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// saturate negative with subtraction
R0.L = 0x8000;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x0001;
R3 = 0;
R7 = 0;
ASTAT = R7;
R3.H = R0.L - R1.H (S);
DBGA ( R3.L , 0x0000 );
DBGA ( R3.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
pass

132
sim/testsuite/sim/bfin/a6.s Normal file
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// ALU test program.
// Test instructions
// r7 = +/+ (r0,r1);
// r7 = +/+ (r0,r1) s;
// r7 = +/+ (r0,r1) sx;
# mach: bfin
.include "testutils.inc"
start
// one result overflows positive
R0.L = 0x0001;
R0.H = 0x0010;
R1.L = 0x7fff;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1;
DBGA ( R7.L , 0x8000 );
DBGA ( R7.H , 0x0020 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// one result overflows negative
R0.L = 0xffff;
R0.H = 0x0010;
R1.L = 0x8000;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1;
DBGA ( R7.L , 0x7fff );
DBGA ( R7.H , 0x0020 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// one result zero
R0.L = 0x0001;
R0.H = 0xffff;
R1.L = 0x0001;
R1.H = 0x0001;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1;
DBGA ( R7.L , 0x0002 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R5 = CC; DBGA ( R5.L , 0x1 );
CC = AN; R5 = CC; DBGA ( R5.L , 0x0 );
CC = V; R5 = CC; DBGA ( R5.L , 0x0 );
CC = AC0; R5 = CC; DBGA ( R5.L , 0x0 );
// one result saturates positive
R0.L = 0x0001;
R0.H = 0x0010;
R1.L = 0x7fff;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1 (S);
DBGA ( R7.L , 0x7fff );
DBGA ( R7.H , 0x0020 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// one result saturates negative
R0.L = 0xffff;
R0.H = 0x0010;
R1.L = 0x8000;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1 (S);
DBGA ( R7.L , 0x8000 );
DBGA ( R7.H , 0x0020 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// two results saturates negative
R0.L = 0xffff;
R0.H = 0xfff0;
R1.L = 0x8000;
R1.H = 0x8000;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1 (S);
DBGA ( R7.L , 0x8000 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
// one result overflows positive and cross
R0.L = 0x0001;
R0.H = 0x0010;
R1.L = 0x7fff;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1 (CO);
DBGA ( R7.L , 0x0020 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
// one result saturates negative and cross
R0.L = 0xffff;
R0.H = 0x0010;
R1.L = 0x8000;
R1.H = 0x0010;
R7 = 0;
ASTAT = R7;
R7 = R0 +|+ R1 (SCO);
DBGA ( R7.L , 0x0020 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x1 );
pass

179
sim/testsuite/sim/bfin/a7.s Normal file
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# mach: bfin
.include "testutils.inc"
start
R1 = 0;
R0 = 0;
R0 = R1 ^ R0;
//_DBG ASTAT;
//R7 = ASTAT;
//DBGA ( R7.L , 1 );
cc = az;
r7 = cc;
dbga( r7.l, 1);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
R0 = R1 | R0;
//_DBG ASTAT;
//R7 = ASTAT;
//DBGA ( R7.L , 1 );
cc = az;
r7 = cc;
dbga( r7.l, 1);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
R0 = 0;
R1 = 1;
CC = R0 == R1;
//_DBG ASTAT;
//R7 = ASTAT;
//DBGA ( R7.L , 2 );
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
CC = BITTST ( R1 , 1 );
//_DBG ASTAT;
//R7 = ASTAT;
//DBGA ( R7.L , 2 );
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
CC = ! BITTST( R1 , 1 );
//_DBG ASTAT;
//R7 = ASTAT;
//DBGA ( R7.L , 0x22 );
r7 = cc;
dbga( r7.l, 1);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
R0.L = 0;
R0.H = 0x8000;
R0 >>>= 1;
_DBG ASTAT;
//R7 = ASTAT;
//DBGA ( R7.L , 0x22 );
cc = az;
r6 = cc;
dbga( r6.l, 0);
cc = an;
r6 = cc;
dbga( r6.l, 1);
cc = av0;
r6 = cc;
dbga( r6.l, 0);
cc = av0s;
r6 = cc;
dbga( r6.l, 0);
cc = av1;
r6 = cc;
dbga( r6.l, 0);
cc = av1s;
r6 = cc;
dbga( r6.l, 0);
R0.L = 17767; R0.H = 291;
R1.L = 52719; R1.H = -30293;
R2.L = 39612; R2.H = 22136;
R3.L = 4660; R3.H = -8464;
R4.L = 26777; R4.H = 9029;
R5.L = 9029; R5.H = 30865;
R6.L = 21554; R6.H = -26506;
R7.L = 22136; R7.H = 4660;
R0 = R0 + R0;
R1 = R0 - R1;
R2 = R0 & R2;
R3 = R0 | R3;
R4 = R0 & R4;
R5 = R0 & R5;
R6 = R0 | R6;
R7 = R0 & R7;
DBGA ( R0.l , 35534 ); DBGA( R0.h , 582 );
DBGA( R1.l , 48351 ); DBGA ( R1.h , 30874 );
DBGA ( R2.l , 35468 ); DBGA ( R2.h , 576 );
DBGA ( R3.l , 39678 ); DBGA ( R3.h , 0xdef6);
DBGA ( R4.l , 2184 ); DBGA ( R4.h , 580 );
DBGA ( R5.l , 580 ); DBGA( R5.h , 0 );
DBGA ( R6.l, 57086 ); DBGA ( R6.h , 0x9a76 );
DBGA ( R7.l , 584 ); DBGA ( R7.h , 516 );
pass

41
sim/testsuite/sim/bfin/a8.s Normal file
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# mach: bfin
.include "testutils.inc"
start
// xh, h, xb, b
R0.L = 32898; R0.H = 1;
R1.L = 49346; R1.H = 3;
R2.L = 6; R2.H = -1;
R3.L = 129; R3.H = 7;
R4.L = 4; R4.H = 0;
R5.L = 5; R5.H = 0;
R6.L = 6; R6.H = 0;
R7.L = 7; R7.H = 0;
R4 = R0.L (X);
// _DBG ASTAT; R7 = ASTAT;DBGA ( R7.L , 2 );
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 1);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
R5 = R0.L;
R6 = R1.B (X);
R7 = R1.B;
DBGA ( R4.l , 32898 ); DBGA ( R4.h , 0xffff);
pass

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// ALU test program.
// Test 32 bit MAX, MIN, ABS instructions
# mach: bfin
.include "testutils.inc"
start
// MAX
// first operand is larger, so AN=0
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// second operand is larger, so AN=1
R0.L = 0x0000;
R0.H = 0x0000;
R1.L = 0x0001;
R1.H = 0x0000;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// first operand is larger, check correct output with overflow
R0.L = 0xffff;
R0.H = 0x7fff;
R1.L = 0xffff;
R1.H = 0xffff;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// second operand is larger, no overflow here
R0.L = 0xffff;
R0.H = 0xffff;
R1.L = 0xffff;
R1.H = 0x7fff;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// second operand is larger, overflow
R0.L = 0xffff;
R0.H = 0x800f;
R1.L = 0xffff;
R1.H = 0x7fff;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV0S; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1S; R7 = CC; DBGA ( R7.L , 0x0 );
// both operands equal
R0.L = 0x0080;
R0.H = 0x8000;
R1.L = 0x0080;
R1.H = 0x8000;
R7 = MAX ( R0 , R1 );
DBGA ( R7.L , 0x0080 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// MIN
// second operand is smaller
R0.L = 0x0001;
R0.H = 0x0000;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MIN ( R0 , R1 );
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// first operand is smaller
R0.L = 0x0001;
R0.H = 0x8000;
R1.L = 0x0000;
R1.H = 0x0000;
R7 = MIN ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// first operand is smaller, overflow
R0.L = 0x0001;
R0.H = 0x8000;
R1.L = 0x0000;
R1.H = 0x0ff0;
R7 = MIN ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// equal operands
R0.L = 0x0001;
R0.H = 0x8000;
R1.L = 0x0001;
R1.H = 0x8000;
R7 = MIN ( R0 , R1 );
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x8000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
// ABS
R0.L = 0x0001;
R0.H = 0x8000;
R7 = ABS R0;
_DBG R7;
_DBG ASTAT;
R6 = ASTAT;
_DBG R6;
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
//CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
//CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
//CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
//CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
//CC = VS; R7 = CC; DBGA ( R7.L , 0x1 );
//CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0001;
R0.H = 0x0000;
R7 = ABS R0;
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0000;
R0.H = 0x8000;
R7 = ABS R0;
DBGA ( R7.L , 0xffff );
DBGA ( R7.H , 0x7fff );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x1 );
CC = VS; R7 = CC; DBGA ( R7.L , 0x1 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0xffff;
R0.H = 0xffff;
R7 = ABS R0;
DBGA ( R7.L , 0x0001 );
DBGA ( R7.H , 0x0000 );
CC = AZ; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AN; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AC0; R7 = CC; DBGA ( R7.L , 0x0 );
CC = V; R7 = CC; DBGA ( R7.L , 0x0 );
CC = AV1; R7 = CC; DBGA ( R7.L , 0x0 );
R0.L = 0x0000;
R0.H = 0x0000;
R7 = ABS R0;
_DBG R7;
_DBG ASTAT;
R6 = ASTAT;
_DBG R6;
DBGA ( R7.L , 0x0000 );
DBGA ( R7.H , 0x0000 );
CC = VS; R6 = CC; DBGA (R6.L, 0x1);
CC = AZ; R6 = CC; DBGA (R6.L, 0x1);
pass

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sim/testsuite/sim/bfin/abs-2.S Normal file
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# Blackfin testcase for ABS instruction
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
.global _test
_test:
R6 = ASTAT;
R0.H = 0x8765;
R0.L = 0x4321;
R1 = ABS R0;
R7 = ASTAT;
R2.H = 0x789a;
R2.L = 0xbcdf;
CC = R1 == R2;
IF !CC JUMP 1f;
/* CLEARED: AZ AN V V_COPY */
R3.H = HI(_AZ|_AN|_V|_V_COPY);
R3.L = LO(_AZ|_AN|_V|_V_COPY);
R4 = R7 & R3;
CC = R4 == 0;
IF !CC JUMP 1f;
/* SET: */
R3.H = HI(0);
R3.L = LO(0);
R4 = R7 & R3;
CC = R3 == R4;
IF !CC JUMP 1f;
/* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */
R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1);
R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1);
R4 = R6 & R3;
R5 = R7 & R3;
CC = R4 == R5;
IF !CC JUMP 1f;
pass
1:
fail

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# Blackfin testcase for ABS instruction
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
.global _test
_test:
R6 = ASTAT;
R0.H = 0x0;
R0.L = 0x0;
R1 = ABS R0;
R7 = ASTAT;
R2.H = 0x0;
R2.L = 0x0;
CC = R1 == R2;
IF !CC JUMP 1f;
/* CLEARED: AN V V_COPY */
R3.H = HI(_AN|_V|_V_COPY);
R3.L = LO(_AN|_V|_V_COPY);
R4 = R7 & R3;
CC = R4 == 0;
IF !CC JUMP 1f;
/* SET: AZ */
R3.H = HI(_AZ);
R3.L = LO(_AZ);
R4 = R7 & R3;
CC = R3 == R4;
IF !CC JUMP 1f;
/* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */
R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1);
R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1);
R4 = R6 & R3;
R5 = R7 & R3;
CC = R4 == R5;
IF !CC JUMP 1f;
pass
1:
fail

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# Blackfin testcase for ABS instruction
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
.global _test
_test:
R6 = ASTAT;
R0.H = 0x8000;
R0.L = 0x0;
R1 = ABS R0;
R7 = ASTAT;
R2.H = 0x7fff;
R2.L = 0xffff;
CC = R1 == R2;
IF !CC JUMP 1f;
/* CLEARED: AZ AN V V_COPY */
R3.H = HI(_AZ|_AN);
R3.L = LO(_AZ|_AN);
R4 = R7 & R3;
CC = R4 == 0;
IF !CC JUMP 1f;
/* SET: V V_COPY VS */
R3.H = HI(_V|_V_COPY|_VS);
R3.L = LO(_V|_V_COPY|_VS);
R4 = R7 & R3;
CC = R3 == R4;
IF !CC JUMP 1f;
/* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S AC0 AC0_COPY AC1 */
R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1);
R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_AC0|_AC0_COPY|_AC1);
R4 = R6 & R3;
R5 = R7 & R3;
CC = R4 == R5;
IF !CC JUMP 1f;
pass
1:
fail

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sim/testsuite/sim/bfin/abs.S Normal file
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# Blackfin testcase for ABS instruction
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
.global _test
_test:
R6 = ASTAT;
R0.H = 0x1234;
R0.L = 0x5678;
R1 = ABS R0;
R7 = ASTAT;
R2.H = 0x1234;
R2.L = 0x5678;
CC = R1 == R2;
IF !CC JUMP 1f;
/* CLEARED: AZ AN V V_COPY */
R3.H = HI(_AZ|_AN|_V|_V_COPY);
R3.L = LO(_AZ|_AN|_V|_V_COPY);
R4 = R7 & R3;
CC = R4 == 0;
IF !CC JUMP 1f;
/* SET: */
R3.H = HI(0);
R3.L = LO(0);
R4 = R7 & R3;
CC = R3 == R4;
IF !CC JUMP 1f;
/* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS AC0 AC0_COPY AC1 */
R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1);
R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS|_AC0|_AC0_COPY|_AC1);
R4 = R6 & R3;
R5 = R7 & R3;
CC = R4 == R5;
IF !CC JUMP 1f;
pass
1:
fail

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sim/testsuite/sim/bfin/abs_acc.s Normal file
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// ACP 5.7 ABS(A1) sets AV0
# mach: bfin
.include "testutils.inc"
start
r1=0x80 (z);
A0=0;
A0.x=r1;
A0=abs A0;
_DBG astat;
//r7=astat;
//dbga (r7.h, 0x3);
//dbga (r7.l, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 1);
cc = av0s;
r7 = cc;
dbga( r7.l, 1);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
r6=A0.x;
dbga (r6.l, 0x7f);
r1=0x80 (z);
A1=0;
A1.x=r1;
A1=abs A1;
_DBG astat;
//r7=astat;
//dbga (r7.h, 0xf);
//dbga (r7.l, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 1);
cc = av0s;
r7 = cc;
dbga( r7.l, 1);
cc = av1;
r7 = cc;
dbga( r7.l, 1);
cc = av1s;
r7 = cc;
dbga( r7.l, 1);
r6=A1.x;
dbga (r6.l, 0x7f);
r7=0;
astat=r7;
r1=0x80 (z);
A1=0;
A1.x=r1;
A0 = abs A1;
_DBG astat;
//r7=astat;
//dbga (r7.h, 0x3);
//dbga (r7.l, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 1);
cc = av0s;
r7 = cc;
dbga( r7.l, 1);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
r6=A0.x;
dbga (r6.l, 0x7f);
r7=0;
astat=r7;
r1=0x80 (z);
A0=0;
A0.x=r1;
A1 = abs A0;
_DBG astat;
//r7=astat;
//dbga (r7.h, 0xc);
//dbga (r7.l, 0x0);
cc = az;
r3 = cc;
dbga( r3.l, 0);
cc = an;
r3 = cc;
dbga( r3.l, 0);
cc = av0;
r3 = cc;
dbga( r3.l, 0);
cc = av0s;
r3 = cc;
dbga( r3.l, 0);
cc = av1;
r3 = cc;
dbga( r3.l, 1);
cc = av1s;
r3 = cc;
dbga( r3.l, 1);
r6=A1.x;
dbga (r6.l, 0x7f);
r7=0;
astat=r7;
r1=0x80 (z);
A1=0;
A1.x=r1;
A0.x=r6;
_DBG A1;
_DBG A0;
A1=abs A1, A0=abs A0;
_DBG ASTAT;
//r7=astat;
//dbga (r7.h, 0xc);
//dbga (r7.l, 0x0);
cc = az;
r4 = cc;
dbga( r4.l, 0);
cc = an;
r4 = cc;
dbga( r4.l, 0);
cc = av0;
r4 = cc;
dbga( r4.l, 0);
cc = av0s;
r4 = cc;
dbga( r4.l, 0);
cc = av1;
r4 = cc;
dbga( r4.l, 1);
cc = av1s;
r4 = cc;
dbga( r4.l, 1);
r7=0;
astat=r7;
r1=0x80 (z);
A1=0;
A1.x=r1;
A0 = A1;
A1=abs A1, A0=abs A0;
_DBG ASTAT;
//r7=astat;
//dbga (r7.h, 0xf);
//dbga (r7.l, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 1);
cc = av0s;
r7 = cc;
dbga( r7.l, 1);
cc = av1;
r7 = cc;
dbga( r7.l, 1);
cc = av1s;
r7 = cc;
dbga( r7.l, 1);
// ACP 5.8 ABS sometimes sets AN
r7=0;
astat=r7;
r0=1;
r1=abs r0;
_DBG r0;
_DBG r1;
_DBG astat;
//r7=astat;
//dbga (r7.h, 0x0);
//dbga (r7.l, 0x0);
cc = az;
r7 = cc;
dbga( r7.l, 0);
cc = an;
r7 = cc;
dbga( r7.l, 0);
cc = av0;
r7 = cc;
dbga( r7.l, 0);
cc = av0s;
r7 = cc;
dbga( r7.l, 0);
cc = av1;
r7 = cc;
dbga( r7.l, 0);
cc = av1s;
r7 = cc;
dbga( r7.l, 0);
pass;

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sim/testsuite/sim/bfin/acc-rot.s Normal file
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# Blackfin testcase for Accumulator Rotates (ROT)
# mach: bfin
.include "testutils.inc"
.macro atest_setup acc:req, val_x:req, val_w:req, cc:req, shift:req
imm32 R0, \val_w
imm32 R1, \val_x
R2 = \cc;
R3 = \shift
\acc\().W = R0;
\acc\().X = R1;
CC = R2;
.endm
.macro atest_check acc:req, exp_x:req, exp_w:req, expcc:req
R7 = CC;
CHECKREG R7, \expcc;
R2 = \acc\().W;
CHECKREG R2, \exp_w;
R6 = \acc\().X;
R6 = R6.B (z);
CHECKREG R6, \exp_x;
.endm
.macro _atest acc:req, val_x:req, val_w:req, cc:req, shift:req, exp_x:req, exp_w:req, expcc:req
atest_setup \acc, \val_x, \val_w, \cc, \shift
_DBG \acc;
\acc = ROT \acc BY \shift;
atest_check \acc, \exp_x, \exp_w, \expcc
atest_setup \acc, \val_x, \val_w, \cc, \shift
\acc = ROT \acc BY R3.L;
atest_check \acc, \exp_x, \exp_w, \expcc
.endm
.macro atest val_x:req, val_w:req, cc:req, shift:req, exp_x:req, exp_w:req, expcc:req
_atest A0, \val_x, \val_w, \cc, \shift, \exp_x, \exp_w, \expcc
_atest A1, \val_x, \val_w, \cc, \shift, \exp_x, \exp_w, \expcc
.endm
start
atest 0x00, 0x00000000, 0, 0, 0x00, 0x00000000, 0
atest 0xa5, 0xa5a5a5a5, 0, 0, 0xa5, 0xa5a5a5a5, 0
atest 0x00, 0x00000000, 1, 0, 0x00, 0x00000000, 1
atest 0xa5, 0xa5a5a5a5, 1, 0, 0xa5, 0xa5a5a5a5, 1
atest 0x00, 0x00000000, 0, 10, 0x00, 0x00000000, 0
atest 0x00, 0x0000000f, 0, 4, 0x00, 0x000000f0, 0
atest 0x00, 0x0000000f, 1, 4, 0x00, 0x000000f8, 0
atest 0x00, 0x0000000f, 0, 20, 0x00, 0x00f00000, 0
atest 0x00, 0x0000000f, 1, 20, 0x00, 0x00f80000, 0
atest 0x00, 0x0000000f, 0, -5, 0xf0, 0x00000000, 0
atest 0x00, 0x0000000f, 1, -5, 0xf8, 0x00000000, 0
atest 0x00, 0x0000000f, 0, -1, 0x00, 0x00000007, 1
atest 0x00, 0x0000000f, 1, -1, 0x80, 0x00000007, 1
atest 0xff, 0xffffffff, 1, 10, 0xff, 0xffffffff, 1
atest 0x11, 0x11111110, 0, -5, 0x00, 0x88888888, 1
atest 0x1f, 0x2e3d4c5b, 1, 0, 0x1f, 0x2e3d4c5b, 1
atest 0x1f, 0x2e3d4c5b, 1, 1, 0x3e, 0x5c7a98b7, 0
atest 0x1f, 0x2e3d4c5b, 1, 2, 0x7c, 0xb8f5316e, 0
atest 0x1f, 0x2e3d4c5b, 1, 3, 0xf9, 0x71ea62dc, 0
atest 0x1f, 0x2e3d4c5b, 1, 4, 0xf2, 0xe3d4c5b8, 1
atest 0x1f, 0x2e3d4c5b, 1, 5, 0xe5, 0xc7a98b71, 1
atest 0x1f, 0x2e3d4c5b, 1, 6, 0xcb, 0x8f5316e3, 1
atest 0x1f, 0x2e3d4c5b, 1, 7, 0x97, 0x1ea62dc7, 1
atest 0x1f, 0x2e3d4c5b, 1, 8, 0x2e, 0x3d4c5b8f, 1
atest 0x1f, 0x2e3d4c5b, 1, 9, 0x5c, 0x7a98b71f, 0
atest 0x1f, 0x2e3d4c5b, 1, 10, 0xb8, 0xf5316e3e, 0
atest 0x1f, 0x2e3d4c5b, 1, 11, 0x71, 0xea62dc7c, 1
atest 0x1f, 0x2e3d4c5b, 1, 12, 0xe3, 0xd4c5b8f9, 0
atest 0x1f, 0x2e3d4c5b, 1, 13, 0xc7, 0xa98b71f2, 1
atest 0x1f, 0x2e3d4c5b, 1, 14, 0x8f, 0x5316e3e5, 1
atest 0x1f, 0x2e3d4c5b, 1, 15, 0x1e, 0xa62dc7cb, 1
atest 0x1f, 0x2e3d4c5b, 1, 16, 0x3d, 0x4c5b8f97, 0
atest 0x1f, 0x2e3d4c5b, 1, 17, 0x7a, 0x98b71f2e, 0
atest 0x1f, 0x2e3d4c5b, 1, 18, 0xf5, 0x316e3e5c, 0
atest 0x1f, 0x2e3d4c5b, 1, 19, 0xea, 0x62dc7cb8, 1
atest 0x1f, 0x2e3d4c5b, 1, 20, 0xd4, 0xc5b8f971, 1
atest 0x1f, 0x2e3d4c5b, 1, 21, 0xa9, 0x8b71f2e3, 1
atest 0x1f, 0x2e3d4c5b, 1, 22, 0x53, 0x16e3e5c7, 1
atest 0x1f, 0x2e3d4c5b, 1, 23, 0xa6, 0x2dc7cb8f, 0
atest 0x1f, 0x2e3d4c5b, 1, 24, 0x4c, 0x5b8f971e, 1
atest 0x1f, 0x2e3d4c5b, 1, 25, 0x98, 0xb71f2e3d, 0
atest 0x1f, 0x2e3d4c5b, 1, 26, 0x31, 0x6e3e5c7a, 1
atest 0x1f, 0x2e3d4c5b, 1, 27, 0x62, 0xdc7cb8f5, 0
atest 0x1f, 0x2e3d4c5b, 1, 28, 0xc5, 0xb8f971ea, 0
atest 0x1f, 0x2e3d4c5b, 1, 29, 0x8b, 0x71f2e3d4, 1
atest 0x1f, 0x2e3d4c5b, 1, 30, 0x16, 0xe3e5c7a9, 1
atest 0x1f, 0x2e3d4c5b, 1, 31, 0x2d, 0xc7cb8f53, 0
atest 0x1f, 0x2e3d4c5b, 1, -1, 0x8f, 0x971ea62d, 1
atest 0x1f, 0x2e3d4c5b, 1, -2, 0xc7, 0xcb8f5316, 1
atest 0x1f, 0x2e3d4c5b, 1, -3, 0xe3, 0xe5c7a98b, 0
atest 0x1f, 0x2e3d4c5b, 1, -4, 0x71, 0xf2e3d4c5, 1
atest 0x1f, 0x2e3d4c5b, 1, -5, 0xb8, 0xf971ea62, 1
atest 0x1f, 0x2e3d4c5b, 1, -6, 0xdc, 0x7cb8f531, 0
atest 0x1f, 0x2e3d4c5b, 1, -7, 0x6e, 0x3e5c7a98, 1
atest 0x1f, 0x2e3d4c5b, 1, -8, 0xb7, 0x1f2e3d4c, 0
atest 0x1f, 0x2e3d4c5b, 1, -9, 0x5b, 0x8f971ea6, 0
atest 0x1f, 0x2e3d4c5b, 1, -10, 0x2d, 0xc7cb8f53, 0
atest 0x1f, 0x2e3d4c5b, 1, -11, 0x16, 0xe3e5c7a9, 1
atest 0x1f, 0x2e3d4c5b, 1, -12, 0x8b, 0x71f2e3d4, 1
atest 0x1f, 0x2e3d4c5b, 1, -13, 0xc5, 0xb8f971ea, 0
atest 0x1f, 0x2e3d4c5b, 1, -14, 0x62, 0xdc7cb8f5, 0
atest 0x1f, 0x2e3d4c5b, 1, -15, 0x31, 0x6e3e5c7a, 1
atest 0x1f, 0x2e3d4c5b, 1, -16, 0x98, 0xb71f2e3d, 0
atest 0x1f, 0x2e3d4c5b, 1, -17, 0x4c, 0x5b8f971e, 1
atest 0x1f, 0x2e3d4c5b, 1, -18, 0xa6, 0x2dc7cb8f, 0
atest 0x1f, 0x2e3d4c5b, 1, -19, 0x53, 0x16e3e5c7, 1
atest 0x1f, 0x2e3d4c5b, 1, -20, 0xa9, 0x8b71f2e3, 1
atest 0x1f, 0x2e3d4c5b, 1, -21, 0xd4, 0xc5b8f971, 1
atest 0x1f, 0x2e3d4c5b, 1, -22, 0xea, 0x62dc7cb8, 1
atest 0x1f, 0x2e3d4c5b, 1, -23, 0xf5, 0x316e3e5c, 0
atest 0x1f, 0x2e3d4c5b, 1, -24, 0x7a, 0x98b71f2e, 0
atest 0x1f, 0x2e3d4c5b, 1, -25, 0x3d, 0x4c5b8f97, 0
atest 0x1f, 0x2e3d4c5b, 1, -26, 0x1e, 0xa62dc7cb, 1
atest 0x1f, 0x2e3d4c5b, 1, -27, 0x8f, 0x5316e3e5, 1
atest 0x1f, 0x2e3d4c5b, 1, -28, 0xc7, 0xa98b71f2, 1
atest 0x1f, 0x2e3d4c5b, 1, -29, 0xe3, 0xd4c5b8f9, 0
atest 0x1f, 0x2e3d4c5b, 1, -30, 0x71, 0xea62dc7c, 1
atest 0x1f, 0x2e3d4c5b, 1, -31, 0xb8, 0xf5316e3e, 0
atest 0x1f, 0x2e3d4c5b, 1, -32, 0x5c, 0x7a98b71f, 0
pass

12
sim/testsuite/sim/bfin/acp5_19.s Normal file
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# mach: bfin
.include "testutils.inc"
start
r0.h=0xa5a5;
r0.l=0xffff;
a0 = 0;
r0=a0.x;
dbga(r0.h, 0x0000);
dbga(r0.l, 0x0000);
pass;

39
sim/testsuite/sim/bfin/acp5_4.s Normal file
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// test RND setting AZ
# mach: bfin
.include "testutils.inc"
start
// result is zero with overflow ==> AZ, therefore, is not set
R0.L = 0x8000;
R0 = R0.L (X);
R1.L = R0 (RND);
CC = AZ; R7 = CC;
DBGA(R1.L, 0);
DBGA ( R7.L , 0x1 );
// No Overflow, result is zero, AZ is set
R0 = 1 (X);
R1.L = r0 (RND);
CC = AZ; R7 = CC;
DBGA(R1.L, 0);
DBGA ( R7.L , 0x1 );
// result should be 1
R0.L = 0x8000;
R0.H = 0;
R1.L = R0 (RND);
CC = AZ; R7 = CC;
DBGA(R1.L, 1);
DBGA ( R7.L , 0x0 );
// Result should be non-zero
R0.H = 0x7ff0;
R0.L = 0x8000;
R1.L = R0 (RND);
CC = AZ; R7 = CC;
DBGA(R1.L, 0x7ff1);
DBGA ( R7.L , 0x0 );
pass

38
sim/testsuite/sim/bfin/add_imm7.s Normal file
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# mach: bfin
.include "testutils.inc"
start
r0 = 0
ASTAT = r0;
r2=-7;
r2+=-63;
_dbg r2;
_dbg astat;
r7=astat;
dbga ( r7.h, 0x0);
dbga ( r7.l, 0x1006);
r7=0;
astat=r7;
r2=64;
r2+=-64;
_dbg r2;
_dbg astat;
r7=astat;
dbga ( r7.h, 0x0);
dbga ( r7.l, 0x1005);
r7=0;
astat=r7;
r2=0;
r2.h=0x8000;
r2+=-63;
_dbg astat;
_dbg r2;
r7=astat;
dbga ( r7.h, 0x0300);
dbga ( r7.l, 0x100c);
pass

53
sim/testsuite/sim/bfin/add_shift.S Normal file
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// ACP 5.6 Flags for dreg=(dreg+dreg)<<1,2
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
r1=0;
ASTAT = R1;
r2=0;
r2.h=0x4000;
r2=(r2+r1)<<2;
dbga (r2.l,0x0);
dbga (r2.h,0x0);
_dbg ASTAT;
r7=ASTAT;
CHECKREG R7, (_VS|_V|_V_COPY|_AZ)
r2=0;
r2.h=0x4000;
r2=(r2+r1)<<1;
dbga (r2.l,0x0);
dbga (r2.h,0x8000);
_dbg ASTAT;
r7=ASTAT;
CHECKREG R7, (_VS|_V|_V_COPY|_AN)
r1=0;
r1.h=0xd300;
r2=0;
r2.h=0xb700;
r2=(r2+r1)<<1;
dbga (r2.l,0x0);
dbga (r2.h,0x1400);
_dbg ASTAT;
r7=ASTAT;
CHECKREG R7, (_VS|_V|_V_COPY)
r0 = 1;
r0 <<= 31; // r0 should be 0x80000000
r7 = 0;
ASTAT = r7;
_dbg r0;
r1 = r0;
_dbg r1;
r1 = (r1 + r0) << 1; // add overflows to zero, no shift overflow
_dbg r1;
_dbg ASTAT;
r7 = ASTAT;
CHECKREG R7, (_VS|_V|_V_COPY|_AZ);
pass

123
sim/testsuite/sim/bfin/add_sub_acc.s Normal file
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// ACP 5.9 A0 -= A1 doesn't set flags
# mach: bfin
.include "testutils.inc"
start
A1 = A0 = 0;
R0 = 0x0;
astat=r0;
A0.w = R0;
R0.L = 0x0080;
A0.x = R0;
R1 = 1;
_DBG A0;
_DBG A1;
A0 -= A1;
_dbg A0;
_dbg ASTAT;
r7=astat;
dbga (r7.h, 0x0);
dbga (r7.l, 0x1006);
A1 = A0 = 0;
R0 = 0x1 (z);
astat=r0;
A0.w = R0;
R0.L = 0x0080;
A0.x = R0;
R1 = 1;
_DBG A0;
_DBG A1;
A0 -= A1;
_dbg A0;
_dbg ASTAT;
r7=astat;
dbga (r7.h, 0x0);
dbga (r7.l, 0x1006);
A1 = A0 = 0;
R0 = 0x0;
astat=r0;
A0.w = R0;
R0.L = 0x0080;
A0.x = R0;
R1 = 1;
A1 = R1;
_DBG A0;
_DBG A1;
A0 -= A1;
_dbg A0;
_dbg ASTAT;
r7=astat;
dbga (r7.h, 0x3);
dbga (r7.l, 0x1006);
A1 = A0 = 0;
R0 = 0x1 (z);
astat=r0;
A0.w = R0;
R0.L = 0x0080;
A0.x = R0;
R1 = 2 (z);
A1 = R1;
_DBG A0;
_DBG A1;
A0 -= A1;
_dbg A0;
_dbg ASTAT;
r7=astat;
dbga (r7.h, 0x3);
dbga (r7.l, 0x1006);
#
A1 = A0 = 0;
R0 = 0x0;
astat=r0;
R0.L=0xffff;
R0.H=0xffff;
A0.w = R0;
R1=0x7f;
A0.x = R1;
A1.x = R1;
A1.w = R0;
_DBG A0;
_DBG A1;
A0 += A1;
_dbg A0;
_dbg ASTAT;
r7=astat;
dbga (r7.h, 0x3);
dbga (r7.l, 0x0);
A1 = A0 = 0;
R0 = 0x0;
astat=r0;
A0.w = R0;
R1=0x80;
A0.x = R1;
A1.x = R1;
A1.w = R0;
_DBG A0;
_DBG A1;
A0 += A1;
_dbg A0;
_dbg ASTAT;
r7=astat;
dbga (r7.h, 0x3);
dbga (r7.l, 0x1006);
pass;

107
sim/testsuite/sim/bfin/addsub_flags.S Normal file
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// ACP 5.17 Dual ALU ops
// AZ, AN, AC0, AC1, V and VS are affected
// AV0, AV0S, AV1, AV1S are unaffected
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
init_r_regs 0;
ASTAT = R0;
A0 = A1 = 0;
r0=0;
r0.h=0x7fff;
r2=0;
r2.h=0x7000;
r1=r0+r2,r3=r0-r2;
r7=astat;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN);
a1=r2;
a0=r0;
r1=a0+a1, r3=a0-a1;
r7=astat;
_dbg a0;
_dbg a1;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN);
a0=r2;
a1=r0;
r1=a1+a0, r3=a1-a0;
r7=astat;
_dbg a0;
_dbg a1;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AN);
r0.h=0xafff;
r2.h=0xa000;
a1=r2;
a0=r0;
r1=a0+a1, r3=a0-a1;
r7=astat;
_dbg a0;
_dbg a1;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1);
r1=a0+a1, r3=a0-a1 (s);
r7=astat;
_dbg a0;
_dbg a1;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1|_AN);
r0.h=0xafff;
r2.h=0xa000;
a0=r2;
a1=r0;
r1=a1+a0, r3=a1-a0;
r7=astat;
_dbg a0;
_dbg a1;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1);
r1=a1+a0, r3=a1-a0 (s);
r7=astat;
_dbg a0;
_dbg a1;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1|_AN);
r2.h=0x8001;
r1=r0+r2,r3=r0-r2;
_dbg r1;
_dbg r3;
_dbg astat;
r7=astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1);
r2.h=0x8000;
r1=r0+r2,r3=r0-r2;
r7=astat;
_dbg r1;
_dbg r3;
_dbg astat;
CHECKREG R7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY|_AC1);
pass;

38
sim/testsuite/sim/bfin/algnbug1.s Normal file
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# mach: bfin
.include "testutils.inc"
start
loadsym P0, blocka;
I0 = P0;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
I0 = P0;
M0 = 1 (X);
I0 += M0;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
pass
.data
.align 8
blocka:
.dw 0xfeff
.dw 0xfcfd
.dw 0xfafb
.dw 0xf8f9

69
sim/testsuite/sim/bfin/algnbug2.s Normal file
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# mach: bfin
.include "testutils.inc"
start
M0 = 1 (X);
loadsym I0, blocka;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
loadsym I0, blocka;
I0 += M0;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
loadsym I0, blocka;
I0 += M0;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
loadsym I0, blocka;
I0 += M0;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.L , 0xfeff );
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
loadsym I0, blocka;
I0 += M0;
DISALGNEXCPT || NOP || R0 = [ I0 ++ ];
DISALGNEXCPT || NOP || R1 = [ I0 ++ ];
DBGA ( R0.H , 0xfcfd );
DBGA ( R1.L , 0xfafb );
DBGA ( R1.H , 0xf8f9 );
pass
.data;
.align 8
blocka:
.dw 0xfeff
.dw 0xfcfd
.dw 0xfafb
.dw 0xf8f9

15
sim/testsuite/sim/bfin/allinsn.exp Normal file
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# Analog Devices Blackfin simulator testsuite
if [istarget bfin-*-elf] {
# all machines
set all_machs "bfin"
foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.\[csS\]]] {
# If we're only testing specific files and this isn't one of them,
# skip it.
if ![runtest_file_p $runtests $src] {
continue
}
run_sim_test $src $all_machs
}
}

31
sim/testsuite/sim/bfin/argc.c Normal file
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/* Basic argc/argv tests.
# mach: bfin
# cc: -msim
# progopts: a bb ccc dddd
*/
int streq(const char *s1, const char *s2)
{
int i = 0;
while (s1[i] && s2[i] && s1[i] == s2[i])
++i;
return s1[i] == '\0' && s2[i] == '\0';
}
int main(int argc, char *argv[])
{
if (argc != 5)
return 1;
if (!streq(argv[1], "a"))
return 2;
if (!streq(argv[2], "bb"))
return 2;
if (!streq(argv[3], "ccc"))
return 2;
if (!streq(argv[4], "dddd"))
return 2;
puts("pass");
return 0;
}

323
sim/testsuite/sim/bfin/ashift.s Normal file
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# Blackfin testcase for ashift
# mach: bfin
.include "testutils.inc"
.macro ashift_test in:req, shift:req, out:req, opt
r0 = \in (Z);
r2.L = \shift;
r2.h = ASHIFT R0.L BY R2.L \opt;
DBGA (r2.h, \out);
.endm
start
/*
* 16-bit ashift and lshift uses a 6-bit signed magnitude, which
* gives a range from -32 to 31. In the case where the magnitude
* is -32, make sure the answer is correct.
*/
ashift_test 0x8001, 33, 0xffff;
ashift_test 0x8001, 32, 0xffff;
ashift_test 0x8001, 31, 0x0000;
ashift_test 0x8001, 30, 0x0000;
ashift_test 0x8001, 29, 0x0000;
ashift_test 0x8001, 28, 0x0000;
ashift_test 0x8001, 27, 0x0000;
ashift_test 0x8001, 26, 0x0000;
ashift_test 0x8001, 25, 0x0000;
ashift_test 0x8001, 24, 0x0000;
ashift_test 0x8001, 23, 0x0000;
ashift_test 0x8001, 22, 0x0000;
ashift_test 0x8001, 21, 0x0000;
ashift_test 0x8001, 20, 0x0000;
ashift_test 0x8001, 19, 0x0000;
ashift_test 0x8001, 18, 0x0000;
ashift_test 0x8001, 17, 0x0000;
ashift_test 0x8001, 16, 0x0000;
ashift_test 0x8001, 15, 0x8000;
ashift_test 0x8001, 14, 0x4000;
ashift_test 0x8001, 13, 0x2000;
ashift_test 0x8001, 12, 0x1000;
ashift_test 0x8001, 11, 0x0800;
ashift_test 0x8001, 10, 0x0400;
ashift_test 0x8001, 9, 0x0200;
ashift_test 0x8001, 8, 0x0100;
ashift_test 0x8001, 7, 0x0080;
ashift_test 0x8001, 6, 0x0040;
ashift_test 0x8001, 5, 0x0020;
ashift_test 0x8001, 4, 0x0010;
ashift_test 0x8001, 3, 0x0008;
ashift_test 0x8001, 2, 0x0004;
ashift_test 0x8001, 1, 0x0002;
ashift_test 0x8001, 0, 0x8001;
ashift_test 0x8001, -1, 0xc000;
ashift_test 0x8001, -2, 0xe000;
ashift_test 0x8001, -3, 0xf000;
ashift_test 0x8001, -4, 0xf800;
ashift_test 0x8001, -5, 0xfc00;
ashift_test 0x8001, -6, 0xfe00;
ashift_test 0x8001, -7, 0xff00;
ashift_test 0x8001, -8, 0xff80;
ashift_test 0x8001, -9, 0xffc0;
ashift_test 0x8001, -10, 0xffe0;
ashift_test 0x8001, -11, 0xfff0;
ashift_test 0x8001, -12, 0xfff8;
ashift_test 0x8001, -13, 0xfffc;
ashift_test 0x8001, -14, 0xfffe;
ashift_test 0x8001, -15, 0xffff;
ashift_test 0x8001, -16, 0xffff;
ashift_test 0x8001, -17, 0xffff;
ashift_test 0x8001, -18, 0xffff;
ashift_test 0x8001, -19, 0xffff;
ashift_test 0x8001, -20, 0xffff;
ashift_test 0x8001, -21, 0xffff;
ashift_test 0x8001, -22, 0xffff;
ashift_test 0x8001, -23, 0xffff;
ashift_test 0x8001, -24, 0xffff;
ashift_test 0x8001, -25, 0xffff;
ashift_test 0x8001, -26, 0xffff;
ashift_test 0x8001, -27, 0xffff;
ashift_test 0x8001, -28, 0xffff;
ashift_test 0x8001, -29, 0xffff;
ashift_test 0x8001, -30, 0xffff;
ashift_test 0x8001, -31, 0xffff;
ashift_test 0x8001, -32, 0xffff;
ashift_test 0x8001, -33, 0x0;
ashift_test 0x8001, -34, 0x0;
ashift_test 0x8001, 33, 0xffff, (S);
ashift_test 0x8001, 32, 0xffff, (S);
ashift_test 0x8001, 31, 0x8000, (S);
ashift_test 0x8001, 30, 0x8000, (S);
ashift_test 0x8001, 29, 0x8000, (S);
ashift_test 0x8001, 28, 0x8000, (S);
ashift_test 0x8001, 27, 0x8000, (S);
ashift_test 0x8001, 26, 0x8000, (S);
ashift_test 0x8001, 25, 0x8000, (S);
ashift_test 0x8001, 24, 0x8000, (S);
ashift_test 0x8001, 23, 0x8000, (S);
ashift_test 0x8001, 22, 0x8000, (S);
ashift_test 0x8001, 21, 0x8000, (S);
ashift_test 0x8001, 20, 0x8000, (S);
ashift_test 0x8001, 19, 0x8000, (S);
ashift_test 0x8001, 18, 0x8000, (S);
ashift_test 0x8001, 17, 0x8000, (S);
ashift_test 0x8001, 16, 0x8000, (S);
ashift_test 0x8001, 15, 0x8000, (S);
ashift_test 0x8001, 14, 0x8000, (S);
ashift_test 0x8001, 13, 0x8000, (S);
ashift_test 0x8001, 12, 0x8000, (S);
ashift_test 0x8001, 11, 0x8000, (S);
ashift_test 0x8001, 10, 0x8000, (S);
ashift_test 0x8001, 9, 0x8000, (S);
ashift_test 0x8001, 8, 0x8000, (S);
ashift_test 0x8001, 7, 0x8000, (S);
ashift_test 0x8001, 6, 0x8000, (S);
ashift_test 0x8001, 5, 0x8000, (S);
ashift_test 0x8001, 4, 0x8000, (S);
ashift_test 0x8001, 3, 0x8000, (S);
ashift_test 0x8001, 2, 0x8000, (S);
ashift_test 0x8001, 1, 0x8000, (S);
ashift_test 0x8001, 0, 0x8001, (S);
ashift_test 0x8001, -1, 0xc000, (S);
ashift_test 0x8001, -2, 0xe000, (S);
ashift_test 0x8001, -3, 0xf000, (S);
ashift_test 0x8001, -4, 0xf800, (S);
ashift_test 0x8001, -5, 0xfc00, (S);
ashift_test 0x8001, -6, 0xfe00, (S);
ashift_test 0x8001, -7, 0xff00, (S);
ashift_test 0x8001, -8, 0xff80, (S);
ashift_test 0x8001, -9, 0xffc0, (S);
ashift_test 0x8001, -10, 0xffe0, (S);
ashift_test 0x8001, -11, 0xfff0, (S);
ashift_test 0x8001, -12, 0xfff8, (S);
ashift_test 0x8001, -13, 0xfffc, (S);
ashift_test 0x8001, -14, 0xfffe, (S);
ashift_test 0x8001, -15, 0xffff, (S);
ashift_test 0x8001, -16, 0xffff, (S);
ashift_test 0x8001, -17, 0xffff, (S);
ashift_test 0x8001, -18, 0xffff, (S);
ashift_test 0x8001, -19, 0xffff, (S);
ashift_test 0x8001, -20, 0xffff, (S);
ashift_test 0x8001, -21, 0xffff, (S);
ashift_test 0x8001, -22, 0xffff, (S);
ashift_test 0x8001, -23, 0xffff, (S);
ashift_test 0x8001, -24, 0xffff, (S);
ashift_test 0x8001, -25, 0xffff, (S);
ashift_test 0x8001, -26, 0xffff, (S);
ashift_test 0x8001, -27, 0xffff, (S);
ashift_test 0x8001, -28, 0xffff, (S);
ashift_test 0x8001, -29, 0xffff, (S);
ashift_test 0x8001, -30, 0xffff, (S);
ashift_test 0x8001, -31, 0xffff, (S);
ashift_test 0x8001, -32, 0xffff, (S);
ashift_test 0x8001, -33, 0x8000, (S);
ashift_test 0x8001, -34, 0x8000, (S);
ashift_test 0x4002, 33, 0x0;
ashift_test 0x4002, 32, 0x0;
ashift_test 0x4002, 31, 0x0;
ashift_test 0x4002, 30, 0x0;
ashift_test 0x4002, 20, 0x0;
ashift_test 0x4002, 19, 0x0;
ashift_test 0x4002, 18, 0x0;
ashift_test 0x4002, 17, 0x0;
ashift_test 0x4002, 16, 0x0;
ashift_test 0x4002, 15, 0x0;
ashift_test 0x4002, 14, 0x8000;
ashift_test 0x4002, 13, 0x4000;
ashift_test 0x4002, 12, 0x2000;
ashift_test 0x4002, 11, 0x1000;
ashift_test 0x4002, 10, 0x0800;
ashift_test 0x4002, 9, 0x0400;
ashift_test 0x4002, 8, 0x0200;
ashift_test 0x4002, 7, 0x0100;
ashift_test 0x4002, 6, 0x0080;
ashift_test 0x4002, 5, 0x0040;
ashift_test 0x4002, 4, 0x0020;
ashift_test 0x4002, 3, 0x0010;
ashift_test 0x4002, 2, 0x0008;
ashift_test 0x4002, 1, 0x8004;
ashift_test 0x4002, 0, 0x4002;
ashift_test 0x4002, -1, 0x2001;
ashift_test 0x4002, -2, 0x1000;
ashift_test 0x4002, -3, 0x0800;
ashift_test 0x4002, -4, 0x0400;
ashift_test 0x4002, -5, 0x0200;
ashift_test 0x4002, -6, 0x0100;
ashift_test 0x4002, -7, 0x0080;
ashift_test 0x4002, -8, 0x0040;
ashift_test 0x4002, -9, 0x0020;
ashift_test 0x4002, -10, 0x0010;
ashift_test 0x4002, -11, 0x0008;
ashift_test 0x4002, -12, 0x0004;
ashift_test 0x4002, -13, 0x0002;
ashift_test 0x4002, -14, 0x0001;
ashift_test 0x4002, -15, 0x0;
ashift_test 0x4002, -16, 0x0;
ashift_test 0x4002, -17, 0x0;
ashift_test 0x4002, -31, 0x0;
ashift_test 0x4002, -32, 0x0;
ashift_test 0x4002, -33, 0x0;
ashift_test 0x4002, -34, 0x0;
ashift_test 0x4002, 33, 0x0, (S);
ashift_test 0x4002, 32, 0x0, (S);
ashift_test 0x4002, 31, 0x7fff, (S);
ashift_test 0x4002, 30, 0x7fff, (S);
ashift_test 0x4002, 20, 0x7fff, (S);
ashift_test 0x4002, 19, 0x7fff, (S);
ashift_test 0x4002, 18, 0x7fff, (S);
ashift_test 0x4002, 17, 0x7fff, (S);
ashift_test 0x4002, 16, 0x7fff, (S);
ashift_test 0x4002, 15, 0x7fff, (S);
ashift_test 0x4002, 14, 0x7fff, (S);
ashift_test 0x4002, 13, 0x7fff, (S);
ashift_test 0x4002, 12, 0x7fff, (S);
ashift_test 0x4002, 11, 0x7fff, (S);
ashift_test 0x4002, 10, 0x7fff, (S);
ashift_test 0x4002, 9, 0x7fff, (S);
ashift_test 0x4002, 8, 0x7fff, (S);
ashift_test 0x4002, 7, 0x7fff, (S);
ashift_test 0x4002, 6, 0x7fff, (S);
ashift_test 0x4002, 5, 0x7fff, (S);
ashift_test 0x4002, 4, 0x7fff, (S);
ashift_test 0x4002, 3, 0x7fff, (S);
ashift_test 0x4002, 2, 0x7fff, (S);
ashift_test 0x4002, 1, 0x7fff, (S);
ashift_test 0x4002, 0, 0x4002, (S);
ashift_test 0x4002, -1, 0x2001, (S);
ashift_test 0x4002, -2, 0x1000, (S);
ashift_test 0x4002, -3, 0x0800, (S);
ashift_test 0x4002, -4, 0x0400, (S);
ashift_test 0x4002, -5, 0x0200, (S);
ashift_test 0x4002, -6, 0x0100, (S);
ashift_test 0x4002, -7, 0x0080, (S);
ashift_test 0x4002, -8, 0x0040, (S);
ashift_test 0x4002, -9, 0x0020, (S);
ashift_test 0x4002, -10, 0x0010, (S);
ashift_test 0x4002, -11, 0x0008, (S);
ashift_test 0x4002, -12, 0x0004, (S);
ashift_test 0x4002, -13, 0x0002, (S);
ashift_test 0x4002, -14, 0x0001, (S);
ashift_test 0x4002, -15, 0x0000, (S);
ashift_test 0x4002, -16, 0x0000, (S);
ashift_test 0x4002, -17, 0x0000, (S);
ashift_test 0x4002, -31, 0x0000, (S);
ashift_test 0x4002, -32, 0x0000, (S);
ashift_test 0x4002, -33, 0x7fff, (S);
ashift_test 0x4002, -34, 0x7fff, (S);
ashift_test 0x0001, 33, 0x0000, (S);
ashift_test 0x0001, 32, 0x0000, (S);
ashift_test 0x0001, 31, 0x7fff, (S);
ashift_test 0x0001, 30, 0x7fff, (S);
ashift_test 0x0001, 29, 0x7fff, (S);
ashift_test 0x0001, 28, 0x7fff, (S);
ashift_test 0x0001, 27, 0x7fff, (S);
ashift_test 0x0001, 26, 0x7fff, (S);
ashift_test 0x0001, 25, 0x7fff, (S);
ashift_test 0x0001, 24, 0x7fff, (S);
ashift_test 0x0001, 23, 0x7fff, (S);
ashift_test 0x0001, 22, 0x7fff, (S);
ashift_test 0x0001, 21, 0x7fff, (S);
ashift_test 0x0001, 20, 0x7fff, (S);
ashift_test 0x0001, 19, 0x7fff, (S);
ashift_test 0x0001, 18, 0x7fff, (S);
ashift_test 0x0001, 17, 0x7fff, (S);
ashift_test 0x0001, 16, 0x7fff, (S);
ashift_test 0x0001, 15, 0x7fff, (S);
ashift_test 0x0001, 14, 0x4000, (S);
ashift_test 0x0001, 13, 0x2000, (S);
ashift_test 0x0001, 12, 0x1000, (S);
ashift_test 0x0001, 11, 0x0800, (S);
ashift_test 0x0001, 10, 0x0400, (S);
ashift_test 0x0001, 9, 0x0200, (S);
ashift_test 0x0001, 8, 0x0100, (S);
ashift_test 0x0001, 7, 0x0080, (S);
ashift_test 0x0001, 6, 0x0040, (S);
ashift_test 0x0001, 5, 0x0020, (S);
ashift_test 0x0001, 4, 0x0010, (S);
ashift_test 0x0001, 3, 0x0008, (S);
ashift_test 0x0001, 2, 0x0004, (S);
ashift_test 0x0001, 1, 0x0002, (S);
ashift_test 0x0001, 0, 0x0001, (S);
ashift_test 0x0001, -1, 0x0000, (S);
ashift_test 0x0001, -2, 0x0000, (S);
ashift_test 0x0001, -3, 0x0000, (S);
ashift_test 0x0001, -4, 0x0000, (S);
ashift_test 0x0001, -5, 0x0000, (S);
ashift_test 0x0001, -6, 0x0000, (S);
ashift_test 0x0001, -7, 0x0000, (S);
ashift_test 0x0001, -8, 0x0000, (S);
ashift_test 0x0001, -9, 0x0000, (S);
ashift_test 0x0001, -10, 0x0000, (S);
ashift_test 0x0001, -11, 0x0000, (S);
ashift_test 0x0001, -12, 0x0000, (S);
ashift_test 0x0001, -13, 0x0000, (S);
ashift_test 0x0001, -14, 0x0, (S);
ashift_test 0x0001, -15, 0x0, (S);
ashift_test 0x0001, -16, 0x0, (S);
ashift_test 0x0001, -17, 0x0, (S);
ashift_test 0x0001, -18, 0x0, (S);
ashift_test 0x0001, -19, 0x0, (S);
ashift_test 0x0001, -20, 0x0, (S);
ashift_test 0x0001, -21, 0x0, (S);
ashift_test 0x0001, -22, 0x0, (S);
ashift_test 0x0001, -23, 0x0, (S);
ashift_test 0x0001, -24, 0x0, (S);
ashift_test 0x0001, -25, 0x0, (S);
ashift_test 0x0001, -26, 0x0, (S);
ashift_test 0x0001, -27, 0x0, (S);
ashift_test 0x0001, -28, 0x0, (S);
ashift_test 0x0001, -29, 0x0, (S);
ashift_test 0x0001, -30, 0x0, (S);
ashift_test 0x0001, -31, 0x0, (S);
ashift_test 0x0001, -32, 0x0, (S);
ashift_test 0x0001, -33, 0x7fff, (S);
ashift_test 0x0001, -34, 0x7fff, (S);
pass

84
sim/testsuite/sim/bfin/ashift_flags.s Normal file
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# mach: bfin
.include "testutils.inc"
start
// load r1=0x7fffffff
// load r2=0x80000000
// load r3=0x000000ff
// load r4=0x00000000
loadsym p0, data0;
R0 = [ P0 ++ ];
R1 = [ P0 ++ ];
R2 = [ P0 ++ ];
R3 = [ P0 ++ ];
R4 = [ P0 ++ ];
_dbg r0;
_dbg r1;
_dbg r2;
_dbg r3;
_dbg r4;
R7 = 0;
ASTAT = R7;
r5 = r1 << 0x4 (s);
_DBG ASTAT;
r7=astat;
dbga (r5.h, 0x7fff);
dbga (r5.l, 0xffff);
dbga (r7.h, 0x0300); // V=1, VS=1
dbga (r7.l, 0x8);
R7 = 0;
ASTAT = R7;
r5.h = r1.h << 0x4 (s);
_DBG ASTAT;
r7=astat;
dbga (r5.h, 0x7fff);
dbga (r7.h, 0x0300); // V=1, VS=1
dbga (r7.l, 0x8);
A0 = 0;
A0.w = r1;
A0.x = r0.l;
r6 = 0x3;
_dbg r6;
_dbg A0;
R7 = 0;
ASTAT = R7;
A0 = ASHIFT A0 BY R6.L;
_DBG ASTAT;
_DBG A0;
r7 = astat;
dbga (r7.h, 0x0); // AV0=0, AV0S=0
dbga (r7.l, 0x2); // AN = 1
A1 = 0;
A1 = r1;
A1.x = r0.l;
r6 = 0x3;
_dbg A1;
R7 = 0;
ASTAT = R7;
A1 = ASHIFT A1 BY R6.L;
_DBG ASTAT;
_DBG A1;
r7 = astat;
dbga (r7.h, 0x0); // AV1=0, AV1S=0
dbga (r7.l, 0x2); // AN = 1
pass
.data 0x1000;
data0:
.dw 0x1111
.dw 0x1111
.dw 0xffff
.dw 0x7fff
.dw 0x0000
.dw 0x8000
.dw 0x00ff
.dw 0x0000
.dw 0x0000
.dw 0x0000

51
sim/testsuite/sim/bfin/b0.S Normal file
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# mach: bfin
#include "test.h"
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
CC = R0 == R0;
AZ = CC;
_DBG ASTAT;
R0 = ASTAT; CHECKREG R0, (_AC0|_AC0_COPY|_CC|_AZ);
R0 = R0 + R0;
R0 = ASTAT; CHECKREG R0, (_CC);
AN = CC;
R0 = ASTAT; CHECKREG R0, (_CC|_AN);
R0 = - R0;
R0 = ASTAT; CHECKREG R0, (_CC|_AN);
AC0 = CC;
_DBG ASTAT;
R0 = ASTAT; CHECKREG R0, (_AC0|_CC|_AN);
AV0 = CC;
_DBG ASTAT;
R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_CC|_AN);
AV1 = CC;
_DBG ASTAT;
R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_CC|_AN);
AQ = CC;
_DBG ASTAT;
R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_AQ|_CC|_AN);
CC = R0 < R0;
_DBG ASTAT;
// When AV0 is set, AV1 is unchanged
AQ = CC;
_DBG ASTAT;
R0 = ASTAT; CHECKREG R0, (_AV1|_AV0|_AC0|_AC0_COPY|_AZ);
AV1 = CC;
_DBG ASTAT;
R0 = ASTAT; CHECKREG R0, (_AV0|_AC0|_AC0_COPY|_AZ);
pass

12
sim/testsuite/sim/bfin/b1.s Normal file
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# mach: bfin
.include "testutils.inc"
start
R0 = 0;
CC = R0 == R0;
IF CC JUMP 4;
JUMP.S LL1;
pass
LL1:
fail

26
sim/testsuite/sim/bfin/b2.S Normal file
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# mach: bfin
#include "test.h"
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
CC = BITTST ( R0 , 0x0 );
BITSET( R0 , 0x0 );
CC = BITTST ( R0 , 0x0 );
CC = ! BITTST( R0 , 0x0 );
R1.L = 1;
R1.H = 0;
CC = R0 == R1;
CC = BITTST ( R0 , 0x1 );
R5 = ASTAT;
CHECKREG R5, (_AC0|_AC0_COPY|_AZ)
BITSET( R0 , 0x1 );
R5 = ASTAT;
CHECKREG R5, 0
CC = BITTST ( R0 , 0x1 );
CC = ! BITTST( R0 , 0x1 );
pass

164
sim/testsuite/sim/bfin/brcc.s Normal file
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# mach: bfin
.include "testutils.inc"
start
/* Stall tests */
r0 = 0;
r1 = 1;
loadsym p0, foo;
p1 = p0;
pass_1:
cc = r0;
nop;
nop;
if cc jump _fail_1;
[p0++] = p0;
[p0++] = p0;
r7 = p0;
r5 = CC;
P1 += 8;
r6 = p1;
CC = R6 == R7;
if !CC jump _failure;
cc = R5;
if !cc jump over;
_fail_1:
[p0++] = p0;
[p0++] = p0;
back:
if !cc jump skip(bp);
_fail_2:
[p0++] = p0;
[p0++] = p0;
over:
if cc jump _fail_3(bp);
[p0++] = p0;
[p0++] = p0;
r7=p0;
R5=cc;
P1 += 8;
R6 = P1;
CC = R6 == R7;
if !CC jump _failure;
CC = R5;
if !cc jump back(bp);
_fail_3:
[p0++] = p0;
[p0++] = p0;
skip:
[p0++] = p0;
[p0++] = p0;
[p0++] = p0;
r7=p0;
P1 += 0xc;
R6 = P1;
CC = R6 == R7;
if !CC jump _failure;
next:
[p0++] = p0;
r7=p0;
P1 += 4;
R6 = P1;
CC = R6 == R7;
if !CC jump _failure;
pass_2:
cc = r1;
nop;
nop;
if !cc jump _fail_4;
[p0++] = p0;
[p0++] = p0;
r7=p0;
R5 = cc;
P1 += 8;
R6 = P1;
CC = R6 == R7;
if !CC jump _failure;
cc = R5;
if cc jump over_2;
_fail_4:
[p0++] = p0;
[p0++] = p0;
P1 += 8;
back_2:
if cc jump skip_2 (bp);
_fail_5:
[p0++] = p0;
[p0++] = p0;
P1 += 8;
over_2:
if !cc jump _fail_6 (bp);
[p0++] = p0;
[p0++] = p0;
r7=p0;
R5 = cc;
P1 += 8;
R6 = P1;
CC = R6 == R7;
if !CC jump _failure;
cc = R5;
if cc jump back_2 (bp);
_fail_6:
[p0++] = p0;
[p0++] = p0;
skip_2:
[p0++] = p0;
[p0++] = p0;
[p0++] = p0;
r7=p0;
R5 = cc;
P1 += 0xc;
R6 = P1;
CC = R6 == R7;
if !CC jump _failure;
cc = r5;
if cc jump next_2 (bp);
next_2:
[p0++] = p0;
[p0++] = p0;
P1 += 8;
r7=p0;
r6 = P1;
CC = R6 == R7;
if !CC jump _failure;
cc = r0;
_halt:
pass;
_fail_7:
[p0++] = p0;
_failure:
fail;
.data
foo:
.space (0x100)

20
sim/testsuite/sim/bfin/brevadd.s Normal file
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# Blackfin testcase for signbits
# mach: bfin
.include "testutils.inc"
start
L2 = 0;
M2 = -4 (X);
I2.H = 0x9000;
I2.L = 0;
I2 += M2 (BREV);
R2 = I2;
imm32 r0, 0x10000002
CC = R2 == R0
if CC jump 1f;
fail
1:
pass

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# Blackfin testcase for BYTEOP16M
# mach: bfin
.include "testutils.inc"
start
.macro check_it resL:req, resH:req
imm32 R6, \resL
CC = R4 == R6;
IF !CC JUMP 1f;
#DBG R4
imm32 R7, \resH
CC = R5 == R7;
IF !CC JUMP 1f;
#DBG R5
.endm
.macro test_byteop16m i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req
dmm32 I0, \i0
dmm32 I1, \i1
(R4, R5) = BYTEOP16M (R1:0, R3:2);
check_it \resL, \resH
(R4, R5) = BYTEOP16M (R1:0, R3:2) (R);
check_it \resLR, \resHR
jump 2f;
1: fail
2:
.endm
imm32 R0, 0x01020304
imm32 R1, 0x10203040
imm32 R2, 0x0a0b0c0d
imm32 R3, 0xa0b0c0d0
test_byteop16m 0, 0, 0xfff7fff7, 0xfff7fff7, 0xff70ff70, 0xff70ff70
test_byteop16m 0, 1, 0xff31fff8, 0xfff8fff8, 0x0003ff80, 0xff80ff80
test_byteop16m 0, 2, 0xff41ff32, 0xfff9fff9, 0x00040013, 0xff90ff90
test_byteop16m 0, 3, 0xff51ff42, 0xff33fffa, 0x00050014, 0x0023ffa0
test_byteop16m 1, 0, 0x0036fff6, 0xfff6fff6, 0xff64ff60, 0xff60ff60
test_byteop16m 1, 1, 0xff70fff7, 0xfff7fff7, 0xfff7ff70, 0xff70ff70
test_byteop16m 1, 2, 0xff80ff31, 0xfff8fff8, 0xfff80003, 0xff80ff80
test_byteop16m 1, 3, 0xff90ff41, 0xff32fff9, 0xfff90004, 0x0013ff90
test_byteop16m 2, 0, 0x00260035, 0xfff5fff5, 0xff63ff54, 0xff50ff50
test_byteop16m 2, 1, 0xff600036, 0xfff6fff6, 0xfff6ff64, 0xff60ff60
test_byteop16m 2, 2, 0xff70ff70, 0xfff7fff7, 0xfff7fff7, 0xff70ff70
test_byteop16m 2, 3, 0xff80ff80, 0xff31fff8, 0xfff8fff8, 0x0003ff80
test_byteop16m 3, 0, 0x00160025, 0x0034fff4, 0xff62ff53, 0xff44ff40
test_byteop16m 3, 1, 0xff500026, 0x0035fff5, 0xfff5ff63, 0xff54ff50
test_byteop16m 3, 2, 0xff60ff60, 0x0036fff6, 0xfff6fff6, 0xff64ff60
test_byteop16m 3, 3, 0xff70ff70, 0xff70fff7, 0xfff7fff7, 0xfff7ff70
imm32 R0, ~0x01020304
imm32 R1, ~0x10203040
imm32 R2, ~0x0a0b0c0d
imm32 R3, ~0xa0b0c0d0
test_byteop16m 0, 0, 0x00090009, 0x00090009, 0x00900090, 0x00900090
test_byteop16m 0, 1, 0x00cf0008, 0x00080008, 0xfffd0080, 0x00800080
test_byteop16m 0, 2, 0x00bf00ce, 0x00070007, 0xfffcffed, 0x00700070
test_byteop16m 0, 3, 0x00af00be, 0x00cd0006, 0xfffbffec, 0xffdd0060
test_byteop16m 1, 0, 0xffca000a, 0x000a000a, 0x009c00a0, 0x00a000a0
test_byteop16m 1, 1, 0x00900009, 0x00090009, 0x00090090, 0x00900090
test_byteop16m 1, 2, 0x008000cf, 0x00080008, 0x0008fffd, 0x00800080
test_byteop16m 1, 3, 0x007000bf, 0x00ce0007, 0x0007fffc, 0xffed0070
test_byteop16m 2, 0, 0xffdaffcb, 0x000b000b, 0x009d00ac, 0x00b000b0
test_byteop16m 2, 1, 0x00a0ffca, 0x000a000a, 0x000a009c, 0x00a000a0
test_byteop16m 2, 2, 0x00900090, 0x00090009, 0x00090009, 0x00900090
test_byteop16m 2, 3, 0x00800080, 0x00cf0008, 0x00080008, 0xfffd0080
test_byteop16m 3, 0, 0xffeaffdb, 0xffcc000c, 0x009e00ad, 0x00bc00c0
test_byteop16m 3, 1, 0x00b0ffda, 0xffcb000b, 0x000b009d, 0x00ac00b0
test_byteop16m 3, 2, 0x00a000a0, 0xffca000a, 0x000a000a, 0x009c00a0
test_byteop16m 3, 3, 0x00900090, 0x00900009, 0x00090009, 0x00090090
pass

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# Blackfin testcase for BYTEOP16P
# mach: bfin
.include "testutils.inc"
start
.macro check_it resL:req, resH:req
imm32 R6, \resL
CC = R4 == R6;
IF !CC JUMP 1f;
imm32 R7, \resH
CC = R5 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop16p i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req
dmm32 I0, \i0
dmm32 I1, \i1
(R4, R5) = BYTEOP16P (R1:0, R3:2);
check_it \resL, \resH
(R4, R5) = BYTEOP16P (R1:0, R3:2) (R);
check_it \resLR, \resHR
jump 2f;
1: fail
2:
.endm
imm32 R0, 0x01020304
imm32 R1, 0x10203040
imm32 R2, 0x0a0b0c0d
imm32 R3, 0xa0b0c0d0
test_byteop16p 0, 0, 0x000b000d, 0x000f0011, 0x00b000d0, 0x00f00110
test_byteop16p 0, 1, 0x00d1000c, 0x000e0010, 0x001d00c0, 0x00e00100
test_byteop16p 0, 2, 0x00c100d2, 0x000d000f, 0x001c002d, 0x00d000f0
test_byteop16p 0, 3, 0x00b100c2, 0x00d3000e, 0x001b002c, 0x003d00e0
test_byteop16p 1, 0, 0x004a000c, 0x000e0010, 0x00a400c0, 0x00e00100
test_byteop16p 1, 1, 0x0110000b, 0x000d000f, 0x001100b0, 0x00d000f0
test_byteop16p 1, 2, 0x010000d1, 0x000c000e, 0x0010001d, 0x00c000e0
test_byteop16p 1, 3, 0x00f000c1, 0x00d2000d, 0x000f001c, 0x002d00d0
test_byteop16p 2, 0, 0x003a004b, 0x000d000f, 0x00a300b4, 0x00d000f0
test_byteop16p 2, 1, 0x0100004a, 0x000c000e, 0x001000a4, 0x00c000e0
test_byteop16p 2, 2, 0x00f00110, 0x000b000d, 0x000f0011, 0x00b000d0
test_byteop16p 2, 3, 0x00e00100, 0x00d1000c, 0x000e0010, 0x001d00c0
test_byteop16p 3, 0, 0x002a003b, 0x004c000e, 0x00a200b3, 0x00c400e0
test_byteop16p 3, 1, 0x00f0003a, 0x004b000d, 0x000f00a3, 0x00b400d0
test_byteop16p 3, 2, 0x00e00100, 0x004a000c, 0x000e0010, 0x00a400c0
test_byteop16p 3, 3, 0x00d000f0, 0x0110000b, 0x000d000f, 0x001100b0
imm32 R0, ~0x01020304
imm32 R1, ~0x10203040
imm32 R2, ~0x0a0b0c0d
imm32 R3, ~0xa0b0c0d0
test_byteop16p 0, 0, 0x01f301f1, 0x01ef01ed, 0x014e012e, 0x010e00ee
test_byteop16p 0, 1, 0x012d01f2, 0x01f001ee, 0x01e1013e, 0x011e00fe
test_byteop16p 0, 2, 0x013d012c, 0x01f101ef, 0x01e201d1, 0x012e010e
test_byteop16p 0, 3, 0x014d013c, 0x012b01f0, 0x01e301d2, 0x01c1011e
test_byteop16p 1, 0, 0x01b401f2, 0x01f001ee, 0x015a013e, 0x011e00fe
test_byteop16p 1, 1, 0x00ee01f3, 0x01f101ef, 0x01ed014e, 0x012e010e
test_byteop16p 1, 2, 0x00fe012d, 0x01f201f0, 0x01ee01e1, 0x013e011e
test_byteop16p 1, 3, 0x010e013d, 0x012c01f1, 0x01ef01e2, 0x01d1012e
test_byteop16p 2, 0, 0x01c401b3, 0x01f101ef, 0x015b014a, 0x012e010e
test_byteop16p 2, 1, 0x00fe01b4, 0x01f201f0, 0x01ee015a, 0x013e011e
test_byteop16p 2, 2, 0x010e00ee, 0x01f301f1, 0x01ef01ed, 0x014e012e
test_byteop16p 2, 3, 0x011e00fe, 0x012d01f2, 0x01f001ee, 0x01e1013e
test_byteop16p 3, 0, 0x01d401c3, 0x01b201f0, 0x015c014b, 0x013a011e
test_byteop16p 3, 1, 0x010e01c4, 0x01b301f1, 0x01ef015b, 0x014a012e
test_byteop16p 3, 2, 0x011e00fe, 0x01b401f2, 0x01f001ee, 0x015a013e
test_byteop16p 3, 3, 0x012e010e, 0x00ee01f3, 0x01f101ef, 0x01ed014e
pass

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sim/testsuite/sim/bfin/byteop1p.s Normal file
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# Blackfin testcase for BYTEOP1P
# mach: bfin
.include "testutils.inc"
start
.macro check_it res:req
imm32 R7, \res
CC = R6 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop1p i0:req, i1:req, res:req, resT:req, resR:req, resTR:req
dmm32 I0, \i0
dmm32 I1, \i1
R6 = BYTEOP1P (R1:0, R3:2);
check_it \res
R6 = BYTEOP1P (R1:0, R3:2) (T);
check_it \resT
R6 = BYTEOP1P (R1:0, R3:2) (R);
check_it \resR
R6 = BYTEOP1P (R1:0, R3:2) (T, R);
check_it \resTR
jump 2f;
1: fail
2:
.endm
imm32 R0, 0x01020304
imm32 R1, 0x10203040
imm32 R2, 0x0a0b0c0d
imm32 R3, 0xa0b0c0d0
test_byteop1p 0, 0, 0x06070809, 0x05060708, 0x58687888, 0x58687888
test_byteop1p 0, 1, 0x69060708, 0x68060708, 0x0f607080, 0x0e607080
test_byteop1p 0, 2, 0x61690708, 0x60690607, 0x0e176878, 0x0e166878
test_byteop1p 0, 3, 0x59616a07, 0x58616907, 0x0e161f70, 0x0d161e70
test_byteop1p 1, 0, 0x25060708, 0x25060708, 0x52607080, 0x52607080
test_byteop1p 1, 1, 0x88060708, 0x88050607, 0x09586878, 0x08586878
test_byteop1p 1, 2, 0x80690607, 0x80680607, 0x080f6070, 0x080e6070
test_byteop1p 1, 3, 0x78616907, 0x78606906, 0x080e1768, 0x070e1668
test_byteop1p 2, 0, 0x1d260708, 0x1d250607, 0x525a6878, 0x515a6878
test_byteop1p 2, 1, 0x80250607, 0x80250607, 0x08526070, 0x08526070
test_byteop1p 2, 2, 0x78880607, 0x78880506, 0x08095868, 0x07085868
test_byteop1p 2, 3, 0x70806906, 0x70806806, 0x07080f60, 0x07080e60
test_byteop1p 3, 0, 0x151e2607, 0x151d2607, 0x515a6270, 0x51596270
test_byteop1p 3, 1, 0x781d2607, 0x781d2506, 0x08525a68, 0x07515a68
test_byteop1p 3, 2, 0x70802506, 0x70802506, 0x07085260, 0x07085260
test_byteop1p 3, 3, 0x68788806, 0x68788805, 0x07080958, 0x06070858
imm32 R0, ~0x01020304
imm32 R1, ~0x10203040
imm32 R2, ~0x0a0b0c0d
imm32 R3, ~0xa0b0c0d0
test_byteop1p 0, 0, 0xfaf9f8f7, 0xf9f8f7f6, 0xa7978777, 0xa7978777
test_byteop1p 0, 1, 0x97f9f8f7, 0x96f9f8f7, 0xf19f8f7f, 0xf09f8f7f
test_byteop1p 0, 2, 0x9f96f9f8, 0x9e96f8f7, 0xf1e99787, 0xf1e89787
test_byteop1p 0, 3, 0xa79e96f8, 0xa69e95f8, 0xf2e9e18f, 0xf1e9e08f
test_byteop1p 1, 0, 0xdaf9f8f7, 0xdaf9f8f7, 0xad9f8f7f, 0xad9f8f7f
test_byteop1p 1, 1, 0x77faf9f8, 0x77f9f8f7, 0xf7a79787, 0xf6a79787
test_byteop1p 1, 2, 0x7f97f9f8, 0x7f96f9f8, 0xf7f19f8f, 0xf7f09f8f
test_byteop1p 1, 3, 0x879f96f9, 0x879e96f8, 0xf8f1e997, 0xf7f1e897
test_byteop1p 2, 0, 0xe2daf9f8, 0xe2d9f8f7, 0xaea59787, 0xada59787
test_byteop1p 2, 1, 0x7fdaf9f8, 0x7fdaf9f8, 0xf7ad9f8f, 0xf7ad9f8f
test_byteop1p 2, 2, 0x8777faf9, 0x8777f9f8, 0xf8f7a797, 0xf7f6a797
test_byteop1p 2, 3, 0x8f7f97f9, 0x8f7f96f9, 0xf8f7f19f, 0xf8f7f09f
test_byteop1p 3, 0, 0xeae2d9f8, 0xeae1d9f8, 0xaea69d8f, 0xaea59d8f
test_byteop1p 3, 1, 0x87e2daf9, 0x87e2d9f8, 0xf8aea597, 0xf7ada597
test_byteop1p 3, 2, 0x8f7fdaf9, 0x8f7fdaf9, 0xf8f7ad9f, 0xf8f7ad9f
test_byteop1p 3, 3, 0x978777fa, 0x978777f9, 0xf9f8f7a7, 0xf8f7f6a7
pass

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sim/testsuite/sim/bfin/byteop2p.s Normal file
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# Blackfin testcase for BYTEOP2P
# mach: bfin
.include "testutils.inc"
start
.macro check_it res:req
imm32 R7, \res
CC = R6 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop2p i0:req, resRL:req, resRH:req, resTL:req, resTH:req, resRLr:req, resRHr:req, resTLr:req, resTHr:req
dmm32 I0, \i0
R6 = BYTEOP2P (R1:0, R3:2) (rndl);
check_it \resRL
R6 = BYTEOP2P (R1:0, R3:2) (rndh);
check_it \resRH
R6 = BYTEOP2P (R1:0, R3:2) (tl);
check_it \resTL
R6 = BYTEOP2P (R1:0, R3:2) (th);
check_it \resTH
R6 = BYTEOP2P (R1:0, R3:2) (rndl, r);
check_it \resRLr
R6 = BYTEOP2P (R1:0, R3:2) (rndh, r);
check_it \resRHr
R6 = BYTEOP2P (R1:0, R3:2) (tl, r);
check_it \resTLr
R6 = BYTEOP2P (R1:0, R3:2) (th, r);
check_it \resTHr
jump 2f;
1: fail
2:
.endm
imm32 R0, 0x01020304
imm32 R1, 0x10203040
imm32 R2, 0x0a0b0c0d
imm32 R3, 0xa0b0c0d0
test_byteop2p 0, 0x00060008, 0x06000800, 0x00060008, 0x06000800, 0x00600080, 0x60008000, 0x00600080, 0x60008000
test_byteop2p 1, 0x00470007, 0x47000700, 0x00460007, 0x46000700, 0x00300070, 0x30007000, 0x00300070, 0x30007000
test_byteop2p 2, 0x00800006, 0x80000600, 0x00800006, 0x80000600, 0x00080060, 0x08006000, 0x00080060, 0x08006000
test_byteop2p 3, 0x00700047, 0x70004700, 0x00700046, 0x70004600, 0x00070030, 0x07003000, 0x00070030, 0x07003000
imm32 R0, ~0x01020304
imm32 R1, ~0x10203040
imm32 R2, ~0x0a0b0c0d
imm32 R3, ~0xa0b0c0d0
test_byteop2p 0, 0x00f900f7, 0xf900f700, 0x00f900f7, 0xf900f700, 0x009f007f, 0x9f007f00, 0x009f007f, 0x9f007f00
test_byteop2p 1, 0x00b800f8, 0xb800f800, 0x00b800f8, 0xb800f800, 0x00cf008f, 0xcf008f00, 0x00ce008f, 0xce008f00
test_byteop2p 2, 0x007f00f9, 0x7f00f900, 0x007f00f9, 0x7f00f900, 0x00f7009f, 0xf7009f00, 0x00f7009f, 0xf7009f00
test_byteop2p 3, 0x008f00b8, 0x8f00b800, 0x008f00b8, 0x8f00b800, 0x00f800cf, 0xf800cf00, 0x00f800ce, 0xf800ce00
pass

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sim/testsuite/sim/bfin/byteop3p.s Normal file
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# Blackfin testcase for BYTEOP3P
# mach: bfin
.include "testutils.inc"
start
.macro check_it res:req
imm32 R7, \res
CC = R6 == R7;
IF !CC JUMP 1f;
.endm
.macro test_byteop3p i0:req, i1:req, resL:req, resH:req, resLR:req, resHR:req
dmm32 I0, \i0
dmm32 I1, \i1
R6 = BYTEOP3P (R1:0, R3:2) (LO);
check_it \resL
R6 = BYTEOP3P (R1:0, R3:2) (HI);
check_it \resH
R6 = BYTEOP3P (R1:0, R3:2) (LO, R);
check_it \resLR
R6 = BYTEOP3P (R1:0, R3:2) (HI, R);
check_it \resHR
jump 2f;
1: fail
2:
.endm
imm32 R0, 0x01020304
imm32 R1, 0x10203040
imm32 R2, 0x0a0b0c0d
imm32 R3, 0xa0b0c0d0
test_byteop3p 0, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 0, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 0, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 0, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
imm32 R0, ~0x01020304
imm32 R1, ~0x10203040
imm32 R2, ~0x0a0b0c0d
imm32 R3, ~0xa0b0c0d0
test_byteop3p 0, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 0, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 0, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 0, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 1, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 1, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 1, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 1, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 2, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 2, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 2, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 2, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 3, 0, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 3, 1, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 3, 2, 0x00000000, 0x00000000, 0x00000000, 0x00000000
test_byteop3p 3, 3, 0x00000000, 0x00000000, 0x00000000, 0x00000000
imm32 R0, 0x00010002
imm32 R1, 0x00030004
imm32 R2, 0x10203040
imm32 R3, 0x50607080
test_byteop3p 0, 0, 0x00110032, 0x21004200, 0x00530074, 0x63008400
test_byteop3p 0, 1, 0x00810022, 0x11003200, 0x00430064, 0x53007400
test_byteop3p 0, 2, 0x00710012, 0x81002200, 0x00330054, 0x43006400
test_byteop3p 0, 3, 0x00610082, 0x71001200, 0x00230044, 0x33005400
test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 0, 0x00140031, 0x24004100, 0x00520073, 0x62008300
test_byteop3p 2, 1, 0x00840021, 0x14003100, 0x00420063, 0x52007300
test_byteop3p 2, 2, 0x00740011, 0x84002100, 0x00320053, 0x42006300
test_byteop3p 2, 3, 0x00640081, 0x74001100, 0x00220043, 0x32005300
test_byteop3p 3, 0, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 1, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 2, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 3, 0x00ff00ff, 0xff00ff00, 0x00ff00ff, 0xff00ff00
imm32 R0, 0x00100200
imm32 R1, 0x30000040
imm32 R2, 0x1a2b3c4d
imm32 R3, 0x5e6f7a8b
test_byteop3p 0, 0, 0x002a00ff, 0x3b00ff00, 0x00ff00ba, 0xff00cb00
test_byteop3p 0, 1, 0x009b00ff, 0x2a00ff00, 0x00ff00af, 0xff00ba00
test_byteop3p 0, 2, 0x008a00ff, 0x9b00ff00, 0x00ff009e, 0xff00af00
test_byteop3p 0, 3, 0x007f00ff, 0x8a00ff00, 0x00ff008d, 0xff009e00
test_byteop3p 1, 0, 0x00ff00ff, 0xff00ff00, 0x008e007a, 0x9f008b00
test_byteop3p 1, 1, 0x00ff00ff, 0xff00ff00, 0x007d006f, 0x8e007a00
test_byteop3p 1, 2, 0x00ff00ff, 0xff00ff00, 0x006c005e, 0x7d006f00
test_byteop3p 1, 3, 0x00ff00ff, 0xff00ff00, 0x005b004d, 0x6c005e00
test_byteop3p 2, 0, 0x005a004c, 0x6b005d00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 1, 0x00cb003b, 0x5a004c00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 2, 0x00ba002a, 0xcb003b00, 0x00ff00ff, 0xff00ff00
test_byteop3p 2, 3, 0x00af009b, 0xba002a00, 0x00ff00ff, 0xff00ff00
test_byteop3p 3, 0, 0x001a00ff, 0x2b00ff00, 0x00ff00aa, 0xff00bb00
test_byteop3p 3, 1, 0x008b00ff, 0x1a00ff00, 0x00ff009f, 0xff00aa00
test_byteop3p 3, 2, 0x007a00ff, 0x8b00ff00, 0x00ff008e, 0xff009f00
test_byteop3p 3, 3, 0x006f00ff, 0x7a00ff00, 0x00ff007d, 0xff008e00
pass

45
sim/testsuite/sim/bfin/byteunpack.s Normal file
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# Blackfin testcase for playing with BYTEUNPACK
# mach: bfin
.include "testutils.inc"
start
.macro _bu_pre_test i0:req, src0:req, src1:req
dmm32 I0, \i0
imm32 R0, \src0
imm32 R1, \src1
.endm
.macro _bu_chk_test dst0:req, dst1:req
imm32 R2, \dst0
imm32 R3, \dst1
CC = R5 == R2;
IF !CC jump 1f;
CC = R6 == R3;
IF !CC jump 1f;
.endm
.macro bu_test i0:req, dst0:req, dst1:req, src0:req, src1:req
_bu_pre_test \i0, \src0, \src1
(R6, R5) = BYTEUNPACK R1:0;
_bu_chk_test \dst0, \dst1
.endm
.macro bu_r_test i0:req, dst0:req, dst1:req, src0:req, src1:req
_bu_pre_test \i0, \src0, \src1
(R6, R5) = BYTEUNPACK R1:0 (R);
_bu_chk_test \dst0, \dst1
.endm
# Taken from PRM
bu_test 0, 0x00BA00DD, 0x00BE00EF, 0xBEEFBADD, 0xFEEDFACE
bu_test 1, 0x00EF00BA, 0x00CE00BE, 0xBEEFBADD, 0xFEEDFACE
bu_test 2, 0x00BE00EF, 0x00FA00CE, 0xBEEFBADD, 0xFEEDFACE
bu_test 3, 0x00CE00BE, 0x00ED00FA, 0xBEEFBADD, 0xFEEDFACE
# Taken from PRM
bu_r_test 0, 0x00FA00CE, 0x00FE00ED, 0xBEEFBADD, 0xFEEDFACE
bu_r_test 1, 0x00ED00FA, 0x00DD00FE, 0xBEEFBADD, 0xFEEDFACE
bu_r_test 2, 0x00FE00ED, 0x00BA00DD, 0xBEEFBADD, 0xFEEDFACE
bu_r_test 3, 0x00DD00FE, 0x00EF00BA, 0xBEEFBADD, 0xFEEDFACE
pass
1: fail

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//Original:/testcases/core/c_alu2op_arith_r_sft/c_alu2op_arith_r_sft.dsp
// Spec Reference: alu2op arith right
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R1.L = 1;
R1 >>>= R0;
R2 >>>= R0;
R3 >>>= R0;
R4 >>>= R0;
R5 >>>= R0;
R6 >>>= R0;
R7 >>>= R0;
R4 >>>= R0;
R0 >>>= R0;
CHECKREG r1, 0x12340001;
CHECKREG r2, 0x23456789;
CHECKREG r3, 0x3456789A;
CHECKREG r4, 0x856789AB;
CHECKREG r5, 0x96789ABC;
CHECKREG r6, 0xA789ABCD;
CHECKREG r7, 0xB89ABCDE;
CHECKREG r0, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R1.L = -1;
R0 >>>= R1;
R2 >>>= R1;
R3 >>>= R1;
R4 >>>= R1;
R5 >>>= R1;
R6 >>>= R1;
R7 >>>= R1;
R1 >>>= R1;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0x00000000;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 31;
R0 >>>= R2;
R1 >>>= R2;
R3 >>>= R2;
R4 >>>= R2;
R5 >>>= R2;
R6 >>>= R2;
R7 >>>= R2;
R2 >>>= R2;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0x00000000;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R3.L = -31;
R0 >>>= R3;
R1 >>>= R3;
R2 >>>= R3;
R4 >>>= R3;
R5 >>>= R3;
R6 >>>= R3;
R7 >>>= R3;
R3 >>>= R3;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x00000001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x00000000;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R4.L = 15;
R1 >>>= R4;
R2 >>>= R4;
R3 >>>= R4;
R0 >>>= R4;
R5 >>>= R4;
R6 >>>= R4;
R7 >>>= R4;
R4 >>>= R4;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00002468;
CHECKREG r2, 0x0000468A;
CHECKREG r3, 0x000068AC;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0xFFFF2CF1;
CHECKREG r6, 0xFFFF4F13;
CHECKREG r7, 0xFFFF7135;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0x00000000;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R5.L = -15;
R0 >>>= R5;
R1 >>>= R5;
R2 >>>= R5;
R3 >>>= R5;
R4 >>>= R5;
R6 >>>= R5;
R7 >>>= R5;
R5 >>>= R5;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0xFFFFFFFF;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0xb1256790;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x00000000;
imm32 r7, 0x789abcde;
R6.L = 24;
R0 >>>= R6;
R1 >>>= R6;
R2 >>>= R6;
R3 >>>= R6;
R4 >>>= R6;
R5 >>>= R6;
R7 >>>= R6;
R6 >>>= R6;
CHECKREG r0, 0x00000051;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0xFFFFFFB1;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0xFFFFFF95;
CHECKREG r5, 0xFFFFFF86;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000078;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0x00000000;
R7.L = -24;
R0 >>>= R7;
R1 >>>= R7;
R2 >>>= R7;
R3 >>>= R7;
R4 >>>= R7;
R5 >>>= R7;
R6 >>>= R7;
R7 >>>= R7;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0xFFFFFFFF;
CHECKREG r2, 0xFFFFFFFF;
CHECKREG r3, 0xFFFFFFFF;
CHECKREG r4, 0xFFFFFFFF;
CHECKREG r5, 0xFFFFFFFF;
CHECKREG r6, 0xFFFFFFFF;
CHECKREG r7, 0x00000000;
// special case
R2.L = -1;
R2.H = 32767;
R0 = 0;
R2 >>>= R0;
CHECKREG r2, 0x7FFFFFFF;
pass

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//Original:/testcases/core/c_alu2op_conv_b/c_alu2op_conv_b.dsp
// Spec Reference: alu2op convert b
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0 = R0.B (Z);
R1 = R0.B (Z);
R2 = R0.B (Z);
R3 = R0.B (Z);
R4 = R0.B (Z);
R5 = R0.B (Z);
R6 = R0.B (Z);
R7 = R0.B (Z);
CHECKREG r0, 0x000000BC;
CHECKREG r1, 0x000000BC;
CHECKREG r2, 0x000000BC;
CHECKREG r3, 0x000000BC;
CHECKREG r4, 0x000000BC;
CHECKREG r5, 0x000000BC;
CHECKREG r6, 0x000000BC;
CHECKREG r7, 0x000000BC;
imm32 r0, 0x01230002;
imm32 r1, 0x00374659;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R0 = R1.B (Z);
R2 = R1.B (Z);
R3 = R1.B (Z);
R4 = R1.B (Z);
R5 = R1.B (Z);
R6 = R1.B (Z);
R7 = R1.B (Z);
R1 = R1.B (Z);
CHECKREG r0, 0x00000059;
CHECKREG r1, 0x00000059;
CHECKREG r2, 0x00000059;
CHECKREG r3, 0x00000059;
CHECKREG r4, 0x00000059;
CHECKREG r5, 0x00000059;
CHECKREG r6, 0x00000059;
CHECKREG r7, 0x00000059;
imm32 r0, 0x10789abc;
imm32 r1, 0x11345678;
imm32 r2, 0x93156789;
imm32 r3, 0xd451789a;
imm32 r4, 0x856719ab;
imm32 r5, 0x267891bc;
imm32 r6, 0xa789ab1d;
imm32 r7, 0x989ab1de;
R0 = R2.B (Z);
R1 = R2.B (Z);
R3 = R2.B (Z);
R4 = R2.B (Z);
R5 = R2.B (Z);
R6 = R2.B (Z);
R7 = R2.B (Z);
R2 = R2.B (Z);
CHECKREG r0, 0x00000089;
CHECKREG r1, 0x00000089;
CHECKREG r2, 0x00000089;
CHECKREG r3, 0x00000089;
CHECKREG r4, 0x00000089;
CHECKREG r5, 0x00000089;
CHECKREG r6, 0x00000089;
CHECKREG r7, 0x00000089;
imm32 r0, 0x21230002;
imm32 r1, 0x02374659;
imm32 r2, 0x93256789;
imm32 r3, 0xa952789a;
imm32 r4, 0xb59729ab;
imm32 r5, 0xc67992bc;
imm32 r6, 0xd7899b2d;
imm32 r7, 0xe89ab9d2;
R0 = R3.B (Z);
R1 = R3.B (Z);
R2 = R3.B (Z);
R4 = R3.B (Z);
R5 = R3.B (Z);
R6 = R3.B (Z);
R7 = R3.B (Z);
R3 = R3.B (Z);
CHECKREG r0, 0x0000009A;
CHECKREG r1, 0x0000009A;
CHECKREG r2, 0x0000009A;
CHECKREG r3, 0x0000009A;
CHECKREG r4, 0x0000009A;
CHECKREG r5, 0x0000009A;
CHECKREG r6, 0x0000009A;
CHECKREG r7, 0x0000009A;
imm32 r0, 0xa0789abc;
imm32 r1, 0x1a345678;
imm32 r2, 0x23a56789;
imm32 r3, 0x645a789a;
imm32 r4, 0x8667a9ab;
imm32 r5, 0x96689abc;
imm32 r6, 0xa787abad;
imm32 r7, 0xb89a7cda;
R0 = R4.B (Z);
R1 = R4.B (Z);
R2 = R4.B (Z);
R3 = R4.B (Z);
R4 = R4.B (Z);
R5 = R4.B (Z);
R6 = R4.B (Z);
R7 = R4.B (Z);
CHECKREG r0, 0x000000AB;
CHECKREG r1, 0x000000AB;
CHECKREG r2, 0x000000AB;
CHECKREG r3, 0x000000AB;
CHECKREG r4, 0x000000AB;
CHECKREG r5, 0x000000AB;
CHECKREG r6, 0x000000AB;
CHECKREG r7, 0x000000AB;
imm32 r0, 0xf1230002;
imm32 r1, 0x0f374659;
imm32 r2, 0x93f56789;
imm32 r3, 0xa45f789a;
imm32 r4, 0xb567f9ab;
imm32 r5, 0xc6789fbc;
imm32 r6, 0xd789abfd;
imm32 r7, 0xe89abcdf;
R0 = R5.B (Z);
R1 = R5.B (Z);
R2 = R5.B (Z);
R3 = R5.B (Z);
R4 = R5.B (Z);
R6 = R5.B (Z);
R7 = R5.B (Z);
R5 = R5.B (Z);
CHECKREG r0, 0x000000BC;
CHECKREG r1, 0x000000BC;
CHECKREG r2, 0x000000BC;
CHECKREG r3, 0x000000BC;
CHECKREG r4, 0x000000BC;
CHECKREG r5, 0x000000BC;
CHECKREG r6, 0x000000BC;
CHECKREG r7, 0x000000BC;
imm32 r0, 0xe0789abc;
imm32 r1, 0xe2345678;
imm32 r2, 0x2e456789;
imm32 r3, 0x34e6789a;
imm32 r4, 0x856e89ab;
imm32 r5, 0x9678eabc;
imm32 r6, 0xa789aecd;
imm32 r7, 0xb89abcee;
R0 = R6.B (Z);
R1 = R6.B (Z);
R2 = R6.B (Z);
R3 = R6.B (Z);
R4 = R6.B (Z);
R5 = R6.B (Z);
R7 = R6.B (Z);
R6 = R6.B (Z);
CHECKREG r0, 0x000000CD;
CHECKREG r1, 0x000000CD;
CHECKREG r2, 0x000000CD;
CHECKREG r3, 0x000000CD;
CHECKREG r4, 0x000000CD;
CHECKREG r5, 0x000000CD;
CHECKREG r6, 0x000000CD;
CHECKREG r7, 0x000000CD;
imm32 r0, 0x012300f5;
imm32 r1, 0x80374659;
imm32 r2, 0x98456589;
imm32 r3, 0xa486589a;
imm32 r4, 0xb56589ab;
imm32 r5, 0xc6588abc;
imm32 r6, 0xd589a8cd;
imm32 r7, 0x589abc88;
R0 = R7.B (Z);
R1 = R7.B (Z);
R2 = R7.B (Z);
R3 = R7.B (Z);
R4 = R7.B (Z);
R5 = R7.B (Z);
R6 = R7.B (Z);
R7 = R7.B (Z);
CHECKREG r0, 0x00000088;
CHECKREG r1, 0x00000088;
CHECKREG r2, 0x00000088;
CHECKREG r3, 0x00000088;
CHECKREG r4, 0x00000088;
CHECKREG r5, 0x00000088;
CHECKREG r6, 0x00000088;
CHECKREG r7, 0x00000088;
pass

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//Original:/testcases/core/c_alu2op_conv_h/c_alu2op_conv_h.dsp
// Spec Reference: alu2op convert h
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0 = R0.L (Z);
R1 = R0.L (Z);
R2 = R0.L (Z);
R3 = R0.L (Z);
R4 = R0.L (Z);
R5 = R0.L (Z);
R6 = R0.L (Z);
R7 = R0.L (Z);
CHECKREG r0, 0x00009ABC;
CHECKREG r1, 0x00009ABC;
CHECKREG r2, 0x00009ABC;
CHECKREG r3, 0x00009ABC;
CHECKREG r4, 0x00009ABC;
CHECKREG r5, 0x00009ABC;
CHECKREG r6, 0x00009ABC;
CHECKREG r7, 0x00009ABC;
imm32 r0, 0x01230002;
imm32 r1, 0x00374659;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R0 = R1.L (Z);
R2 = R1.L (Z);
R3 = R1.L (Z);
R4 = R1.L (Z);
R5 = R1.L (Z);
R6 = R1.L (Z);
R7 = R1.L (Z);
R1 = R1.L (Z);
CHECKREG r0, 0x00004659;
CHECKREG r1, 0x00004659;
CHECKREG r2, 0x00004659;
CHECKREG r3, 0x00004659;
CHECKREG r4, 0x00004659;
CHECKREG r5, 0x00004659;
CHECKREG r6, 0x00004659;
CHECKREG r7, 0x00004659;
imm32 r0, 0x10789abc;
imm32 r1, 0x11345678;
imm32 r2, 0x93156789;
imm32 r3, 0xd451789a;
imm32 r4, 0x856719ab;
imm32 r5, 0x267891bc;
imm32 r6, 0xa789ab1d;
imm32 r7, 0x989ab1de;
R0 = R2.L (Z);
R1 = R2.L (Z);
R3 = R2.L (Z);
R4 = R2.L (Z);
R5 = R2.L (Z);
R6 = R2.L (Z);
R7 = R2.L (Z);
R2 = R2.L (Z);
CHECKREG r0, 0x00006789;
CHECKREG r1, 0x00006789;
CHECKREG r2, 0x00006789;
CHECKREG r3, 0x00006789;
CHECKREG r4, 0x00006789;
CHECKREG r5, 0x00006789;
CHECKREG r6, 0x00006789;
CHECKREG r7, 0x00006789;
imm32 r0, 0x21230002;
imm32 r1, 0x02374659;
imm32 r2, 0x93256789;
imm32 r3, 0xa952789a;
imm32 r4, 0xb59729ab;
imm32 r5, 0xc67992bc;
imm32 r6, 0xd7899b2d;
imm32 r7, 0xe89ab9d2;
R0 = R3.L (Z);
R1 = R3.L (Z);
R2 = R3.L (Z);
R4 = R3.L (Z);
R5 = R3.L (Z);
R6 = R3.L (Z);
R7 = R3.L (Z);
R3 = R3.L (Z);
CHECKREG r0, 0x0000789A;
CHECKREG r1, 0x0000789A;
CHECKREG r2, 0x0000789A;
CHECKREG r3, 0x0000789A;
CHECKREG r4, 0x0000789A;
CHECKREG r5, 0x0000789A;
CHECKREG r6, 0x0000789A;
CHECKREG r7, 0x0000789A;
imm32 r0, 0xa0789abc;
imm32 r1, 0x1a345678;
imm32 r2, 0x23a56789;
imm32 r3, 0x645a789a;
imm32 r4, 0x8667a9ab;
imm32 r5, 0x96689abc;
imm32 r6, 0xa787abad;
imm32 r7, 0xb89a7cda;
R0 = R4.L (Z);
R1 = R4.L (Z);
R2 = R4.L (Z);
R3 = R4.L (Z);
R4 = R4.L (Z);
R5 = R4.L (Z);
R6 = R4.L (Z);
R7 = R4.L (Z);
CHECKREG r0, 0x0000A9AB;
CHECKREG r1, 0x0000A9AB;
CHECKREG r2, 0x0000A9AB;
CHECKREG r3, 0x0000A9AB;
CHECKREG r4, 0x0000A9AB;
CHECKREG r5, 0x0000A9AB;
CHECKREG r6, 0x0000A9AB;
CHECKREG r7, 0x0000A9AB;
imm32 r0, 0xf1230002;
imm32 r1, 0x0f374659;
imm32 r2, 0x93f56789;
imm32 r3, 0xa45f789a;
imm32 r4, 0xb567f9ab;
imm32 r5, 0xc6789fbc;
imm32 r6, 0xd789abfd;
imm32 r7, 0xe89abcdf;
R0 = R5.L (Z);
R1 = R5.L (Z);
R2 = R5.L (Z);
R3 = R5.L (Z);
R4 = R5.L (Z);
R6 = R5.L (Z);
R7 = R5.L (Z);
R5 = R5.L (Z);
CHECKREG r0, 0x00009FBC;
CHECKREG r1, 0x00009FBC;
CHECKREG r2, 0x00009FBC;
CHECKREG r3, 0x00009FBC;
CHECKREG r4, 0x00009FBC;
CHECKREG r5, 0x00009FBC;
CHECKREG r6, 0x00009FBC;
CHECKREG r7, 0x00009FBC;
imm32 r0, 0xe0789abc;
imm32 r1, 0xe2345678;
imm32 r2, 0x2e456789;
imm32 r3, 0x34e6789a;
imm32 r4, 0x856e89ab;
imm32 r5, 0x9678eabc;
imm32 r6, 0xa789aecd;
imm32 r7, 0xb89abcee;
R0 = R6.L (Z);
R1 = R6.L (Z);
R2 = R6.L (Z);
R3 = R6.L (Z);
R4 = R6.L (Z);
R5 = R6.L (Z);
R7 = R6.L (Z);
R6 = R6.L (Z);
CHECKREG r0, 0x0000AECD;
CHECKREG r1, 0x0000AECD;
CHECKREG r2, 0x0000AECD;
CHECKREG r3, 0x0000AECD;
CHECKREG r4, 0x0000AECD;
CHECKREG r5, 0x0000AECD;
CHECKREG r6, 0x0000AECD;
CHECKREG r7, 0x0000AECD;
imm32 r0, 0x012300f5;
imm32 r1, 0x80374659;
imm32 r2, 0x98456589;
imm32 r3, 0xa486589a;
imm32 r4, 0xb56589ab;
imm32 r5, 0xc6588abc;
imm32 r6, 0xd589a8cd;
imm32 r7, 0x589abc88;
R0 = R7.L (Z);
R1 = R7.L (Z);
R2 = R7.L (Z);
R3 = R7.L (Z);
R4 = R7.L (Z);
R5 = R7.L (Z);
R6 = R7.L (Z);
R7 = R7.L (Z);
CHECKREG r0, 0x0000BC88;
CHECKREG r1, 0x0000BC88;
CHECKREG r2, 0x0000BC88;
CHECKREG r3, 0x0000BC88;
CHECKREG r4, 0x0000BC88;
CHECKREG r5, 0x0000BC88;
CHECKREG r6, 0x0000BC88;
CHECKREG r7, 0x0000BC88;
pass

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//Original:/testcases/core/c_alu2op_conv_mix/c_alu2op_conv_mix.dsp
// Spec Reference: alu2op convert mix
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0 = R0.B (X);
R1 = R1.L (X);
R2 = R2.L (Z);
R3 = R3.B (X);
R4 = R4.B (Z);
R5 = - R5;
R6 = ~ R6;
R7 = R7.L (X);
CHECKREG r0, 0xFFFFFFBC;
CHECKREG r1, 0x00005678;
CHECKREG r2, 0x00006789;
CHECKREG r3, 0xFFFFFF9A;
CHECKREG r4, 0x000000AB;
CHECKREG r5, 0x69876544;
CHECKREG r6, 0x58765432;
CHECKREG r7, 0xFFFFBCDE;
imm32 r0, 0x01230002;
imm32 r1, 0x00374659;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R6 = R0.B (X);
R7 = R1.L (X);
R0 = R2.L (Z);
R1 = R3.B (X);
R2 = R4.B (Z);
R3 = - R5;
R4 = ~ R6;
R5 = R7.L (X);
CHECKREG r0, 0x00006789;
CHECKREG r1, 0xFFFFFF9A;
CHECKREG r2, 0x000000AB;
CHECKREG r3, 0x39876544;
CHECKREG r4, 0xFFFFFFFD;
CHECKREG r5, 0x00004659;
CHECKREG r6, 0x00000002;
CHECKREG r7, 0x00004659;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0x91203450;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0x789abcde;
R5 = R0.B (X);
R6 = R1.L (X);
R7 = R2.L (Z);
R0 = R3.B (X);
R1 = R4.B (Z);
R2 = - R5;
R3 = ~ R6;
R4 = R7.L (X);
CHECKREG r0, 0xFFFFFF9A;
CHECKREG r1, 0x000000AB;
CHECKREG r2, 0xFFFFFFFE;
CHECKREG r3, 0xFFFFA987;
CHECKREG r4, 0x00003450;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0x00005678;
CHECKREG r7, 0x00003450;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0x00000000;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R4 = R0.B (X);
R5 = R1.L (X);
R6 = R2.L (Z);
R7 = R3.B (X);
R0 = R4.B (Z);
R1 = - R5;
R2 = ~ R6;
R3 = R7.L (X);
CHECKREG r0, 0x00000002;
CHECKREG r1, 0xFFFFA988;
CHECKREG r2, 0xFFFF9876;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000002;
CHECKREG r5, 0x00005678;
CHECKREG r6, 0x00006789;
CHECKREG r7, 0x00000000;
imm32 r0, 0xadf00001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x00000000;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R3 = R0.B (X);
R4 = R1.L (X);
R5 = R2.L (Z);
R6 = R3.B (X);
R7 = R4.B (Z);
R0 = - R5;
R1 = ~ R6;
R2 = R7.L (X);
CHECKREG r0, 0xFFFF9877;
CHECKREG r1, 0xFFFFFFFE;
CHECKREG r2, 0x00000078;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00005678;
CHECKREG r5, 0x00006789;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000078;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0x54238900;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R2 = R0.B (X);
R3 = R1.L (X);
R4 = R2.L (Z);
R5 = R3.B (X);
R6 = R4.B (Z);
R7 = - R5;
R0 = ~ R6;
R1 = R7.L (X);
CHECKREG r0, 0xFFFFFFFD;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000002;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000002;
CHECKREG r7, 0x00000000;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0x00000000;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x00000000;
imm32 r7, 0x789abcde;
R1 = R0.B (X);
R2 = R1.L (X);
R3 = R2.L (Z);
R4 = R3.B (X);
R5 = R4.B (Z);
R6 = - R5;
R0 = ~ R6;
R7 = R7.L (X);
CHECKREG r0, 0x00000001;
CHECKREG r1, 0x00000002;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000002;
CHECKREG r4, 0x00000002;
CHECKREG r5, 0x00000002;
CHECKREG r6, 0xFFFFFFFE;
CHECKREG r7, 0xFFFFBCDE;
pass

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//Original:/testcases/core/c_alu2op_conv_neg/c_alu2op_conv_neg.dsp
// Spec Reference: alu2op (-) negative
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0 = - R0;
R1 = - R0;
R2 = - R0;
R3 = - R0;
R4 = - R0;
R5 = - R0;
R6 = - R0;
R7 = - R0;
CHECKREG r0, 0xFF876544;
CHECKREG r1, 0x00789ABC;
CHECKREG r2, 0x00789ABC;
CHECKREG r3, 0x00789ABC;
CHECKREG r4, 0x00789ABC;
CHECKREG r5, 0x00789ABC;
CHECKREG r6, 0x00789ABC;
CHECKREG r7, 0x00789ABC;
imm32 r0, 0x01230002;
imm32 r1, 0x00374659;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R0 = - R1;
R1 = - R1;
R2 = - R1;
R3 = - R1;
R4 = - R1;
R5 = - R1;
R6 = - R1;
R7 = - R1;
CHECKREG r0, 0xFFC8B9A7;
CHECKREG r1, 0xFFC8B9A7;
CHECKREG r2, 0x00374659;
CHECKREG r3, 0x00374659;
CHECKREG r4, 0x00374659;
CHECKREG r5, 0x00374659;
CHECKREG r6, 0x00374659;
CHECKREG r7, 0x00374659;
imm32 r0, 0x10789abc;
imm32 r1, 0x11345678;
imm32 r2, 0x93156789;
imm32 r3, 0xd451789a;
imm32 r4, 0x856719ab;
imm32 r5, 0x267891bc;
imm32 r6, 0xa789ab1d;
imm32 r7, 0x989ab1de;
R0 = - R2;
R1 = - R2;
R2 = - R2;
R3 = - R2;
R4 = - R2;
R5 = - R2;
R6 = - R2;
R7 = - R2;
CHECKREG r0, 0x6CEA9877;
CHECKREG r1, 0x6CEA9877;
CHECKREG r2, 0x6CEA9877;
CHECKREG r3, 0x93156789;
CHECKREG r4, 0x93156789;
CHECKREG r5, 0x93156789;
CHECKREG r6, 0x93156789;
CHECKREG r7, 0x93156789;
imm32 r0, 0x21230002;
imm32 r1, 0x02374659;
imm32 r2, 0x93256789;
imm32 r3, 0xa952789a;
imm32 r4, 0xb59729ab;
imm32 r5, 0xc67992bc;
imm32 r6, 0xd7899b2d;
imm32 r7, 0xe89ab9d2;
R0 = - R3;
R1 = - R3;
R2 = - R3;
R3 = - R3;
R4 = - R3;
R5 = - R3;
R6 = - R3;
R7 = - R3;
CHECKREG r0, 0x56AD8766;
CHECKREG r1, 0x56AD8766;
CHECKREG r2, 0x56AD8766;
CHECKREG r3, 0x56AD8766;
CHECKREG r4, 0xA952789A;
CHECKREG r5, 0xA952789A;
CHECKREG r6, 0xA952789A;
CHECKREG r7, 0xA952789A;
imm32 r0, 0xa0789abc;
imm32 r1, 0x1a345678;
imm32 r2, 0x23a56789;
imm32 r3, 0x645a789a;
imm32 r4, 0x8667a9ab;
imm32 r5, 0x96689abc;
imm32 r6, 0xa787abad;
imm32 r7, 0xb89a7cda;
R0 = - R4;
R1 = - R4;
R2 = - R4;
R3 = - R4;
R4 = - R4;
R5 = - R4;
R6 = - R4;
R7 = - R4;
CHECKREG r0, 0x79985655;
CHECKREG r1, 0x79985655;
CHECKREG r2, 0x79985655;
CHECKREG r3, 0x79985655;
CHECKREG r4, 0x79985655;
CHECKREG r5, 0x8667A9AB;
CHECKREG r6, 0x8667A9AB;
CHECKREG r7, 0x8667A9AB;
imm32 r0, 0xf1230002;
imm32 r1, 0x0f374659;
imm32 r2, 0x93f56789;
imm32 r3, 0xa45f789a;
imm32 r4, 0xb567f9ab;
imm32 r5, 0xc6789fbc;
imm32 r6, 0xd789abfd;
imm32 r7, 0xe89abcdf;
R0 = - R5;
R1 = - R5;
R2 = - R5;
R3 = - R5;
R4 = - R5;
R5 = - R5;
R6 = - R5;
R7 = - R5;
CHECKREG r0, 0x39876044;
CHECKREG r1, 0x39876044;
CHECKREG r2, 0x39876044;
CHECKREG r3, 0x39876044;
CHECKREG r4, 0x39876044;
CHECKREG r5, 0x39876044;
CHECKREG r6, 0xC6789FBC;
CHECKREG r7, 0xC6789FBC;
imm32 r0, 0xe0789abc;
imm32 r1, 0xe2345678;
imm32 r2, 0x2e456789;
imm32 r3, 0x34e6789a;
imm32 r4, 0x856e89ab;
imm32 r5, 0x9678eabc;
imm32 r6, 0xa789aecd;
imm32 r7, 0xb89abcee;
R0 = - R6;
R1 = - R6;
R2 = - R6;
R3 = - R6;
R4 = - R6;
R5 = - R6;
R6 = - R6;
R7 = - R6;
CHECKREG r0, 0x58765133;
CHECKREG r1, 0x58765133;
CHECKREG r2, 0x58765133;
CHECKREG r3, 0x58765133;
CHECKREG r4, 0x58765133;
CHECKREG r5, 0x58765133;
CHECKREG r6, 0x58765133;
CHECKREG r7, 0xA789AECD;
imm32 r0, 0x012300f5;
imm32 r1, 0x80374659;
imm32 r2, 0x98456589;
imm32 r3, 0xa486589a;
imm32 r4, 0xb56589ab;
imm32 r5, 0xc6588abc;
imm32 r6, 0xd589a8cd;
imm32 r7, 0x589abc88;
R0 = - R7;
R1 = - R7;
R2 = - R7;
R3 = - R7;
R4 = - R7;
R5 = - R7;
R7 = - R7;
R6 = - R7;
CHECKREG r0, 0xA7654378;
CHECKREG r1, 0xA7654378;
CHECKREG r2, 0xA7654378;
CHECKREG r3, 0xA7654378;
CHECKREG r4, 0xA7654378;
CHECKREG r5, 0xA7654378;
CHECKREG r6, 0x589ABC88;
CHECKREG r7, 0xA7654378;
pass

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//Original:/testcases/core/c_alu2op_conv_toggle/c_alu2op_conv_toggle.dsp
// Spec Reference: alu2op (~) toggle
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0 = ~ R0;
R1 = ~ R0;
R2 = ~ R0;
R3 = ~ R0;
R4 = ~ R0;
R5 = ~ R0;
R6 = ~ R0;
R7 = ~ R0;
CHECKREG r0, 0xFF876543;
CHECKREG r1, 0x00789ABC;
CHECKREG r2, 0x00789ABC;
CHECKREG r3, 0x00789ABC;
CHECKREG r4, 0x00789ABC;
CHECKREG r5, 0x00789ABC;
CHECKREG r6, 0x00789ABC;
CHECKREG r7, 0x00789ABC;
imm32 r0, 0x01230002;
imm32 r1, 0x00374659;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R0 = ~ R1;
R1 = ~ R1;
R2 = ~ R1;
R3 = ~ R1;
R4 = ~ R1;
R5 = ~ R1;
R6 = ~ R1;
R7 = ~ R1;
CHECKREG r0, 0xFFC8B9A6;
CHECKREG r1, 0xFFC8B9A6;
CHECKREG r2, 0x00374659;
CHECKREG r3, 0x00374659;
CHECKREG r4, 0x00374659;
CHECKREG r5, 0x00374659;
CHECKREG r6, 0x00374659;
CHECKREG r7, 0x00374659;
imm32 r0, 0x10789abc;
imm32 r1, 0x11345678;
imm32 r2, 0x93156789;
imm32 r3, 0xd451789a;
imm32 r4, 0x856719ab;
imm32 r5, 0x267891bc;
imm32 r6, 0xa789ab1d;
imm32 r7, 0x989ab1de;
R0 = ~ R2;
R1 = ~ R2;
R2 = ~ R2;
R3 = ~ R2;
R4 = ~ R2;
R5 = ~ R2;
R6 = ~ R2;
R7 = ~ R2;
CHECKREG r0, 0x6CEA9876;
CHECKREG r1, 0x6CEA9876;
CHECKREG r2, 0x6CEA9876;
CHECKREG r3, 0x93156789;
CHECKREG r4, 0x93156789;
CHECKREG r5, 0x93156789;
CHECKREG r6, 0x93156789;
CHECKREG r7, 0x93156789;
imm32 r0, 0x21230002;
imm32 r1, 0x02374659;
imm32 r2, 0x93256789;
imm32 r3, 0xa952789a;
imm32 r4, 0xb59729ab;
imm32 r5, 0xc67992bc;
imm32 r6, 0xd7899b2d;
imm32 r7, 0xe89ab9d2;
R0 = ~ R3;
R1 = ~ R3;
R2 = ~ R3;
R3 = ~ R3;
R4 = ~ R3;
R5 = ~ R3;
R6 = ~ R3;
R7 = ~ R3;
CHECKREG r0, 0x56AD8765;
CHECKREG r1, 0x56AD8765;
CHECKREG r2, 0x56AD8765;
CHECKREG r3, 0x56AD8765;
CHECKREG r4, 0xA952789A;
CHECKREG r5, 0xA952789A;
CHECKREG r6, 0xA952789A;
CHECKREG r7, 0xA952789A;
imm32 r0, 0xa0789abc;
imm32 r1, 0x1a345678;
imm32 r2, 0x23a56789;
imm32 r3, 0x645a789a;
imm32 r4, 0x8667a9ab;
imm32 r5, 0x96689abc;
imm32 r6, 0xa787abad;
imm32 r7, 0xb89a7cda;
R0 = ~ R4;
R1 = ~ R4;
R2 = ~ R4;
R3 = ~ R4;
R4 = ~ R4;
R5 = ~ R4;
R6 = ~ R4;
R7 = ~ R4;
CHECKREG r0, 0x79985654;
CHECKREG r1, 0x79985654;
CHECKREG r2, 0x79985654;
CHECKREG r3, 0x79985654;
CHECKREG r4, 0x79985654;
CHECKREG r5, 0x8667A9AB;
CHECKREG r6, 0x8667A9AB;
CHECKREG r7, 0x8667A9AB;
imm32 r0, 0xf1230002;
imm32 r1, 0x0f374659;
imm32 r2, 0x93f56789;
imm32 r3, 0xa45f789a;
imm32 r4, 0xb567f9ab;
imm32 r5, 0xc6789fbc;
imm32 r6, 0xd789abfd;
imm32 r7, 0xe89abcdf;
R0 = ~ R5;
R1 = ~ R5;
R2 = ~ R5;
R3 = ~ R5;
R4 = ~ R5;
R5 = ~ R5;
R6 = ~ R5;
R7 = ~ R5;
CHECKREG r0, 0x39876043;
CHECKREG r1, 0x39876043;
CHECKREG r2, 0x39876043;
CHECKREG r3, 0x39876043;
CHECKREG r4, 0x39876043;
CHECKREG r5, 0x39876043;
CHECKREG r6, 0xC6789FBC;
CHECKREG r7, 0xC6789FBC;
imm32 r0, 0xe0789abc;
imm32 r1, 0xe2345678;
imm32 r2, 0x2e456789;
imm32 r3, 0x34e6789a;
imm32 r4, 0x856e89ab;
imm32 r5, 0x9678eabc;
imm32 r6, 0xa789aecd;
imm32 r7, 0xb89abcee;
R0 = ~ R6;
R1 = ~ R6;
R2 = ~ R6;
R3 = ~ R6;
R4 = ~ R6;
R5 = ~ R6;
R6 = ~ R6;
R7 = ~ R6;
CHECKREG r0, 0x58765132;
CHECKREG r1, 0x58765132;
CHECKREG r2, 0x58765132;
CHECKREG r3, 0x58765132;
CHECKREG r4, 0x58765132;
CHECKREG r5, 0x58765132;
CHECKREG r6, 0x58765132;
CHECKREG r7, 0xA789AECD;
imm32 r0, 0x012300f5;
imm32 r1, 0x80374659;
imm32 r2, 0x98456589;
imm32 r3, 0xa486589a;
imm32 r4, 0xb56589ab;
imm32 r5, 0xc6588abc;
imm32 r6, 0xd589a8cd;
imm32 r7, 0x589abc88;
R0 = ~ R7;
R1 = ~ R7;
R2 = ~ R7;
R3 = ~ R7;
R4 = ~ R7;
R5 = ~ R7;
R7 = ~ R7;
R6 = ~ R7;
CHECKREG r0, 0xA7654377;
CHECKREG r1, 0xA7654377;
CHECKREG r2, 0xA7654377;
CHECKREG r3, 0xA7654377;
CHECKREG r4, 0xA7654377;
CHECKREG r5, 0xA7654377;
CHECKREG r6, 0x589ABC88;
CHECKREG r7, 0xA7654377;
pass

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//Original:/testcases/core/c_alu2op_conv_xb/c_alu2op_conv_xb.dsp
// Spec Reference: alu2op convert xb
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0 = R0.B (X);
R1 = R0.B (X);
R2 = R0.B (X);
R3 = R0.B (X);
R4 = R0.B (X);
R5 = R0.B (X);
R6 = R0.B (X);
R7 = R0.B (X);
CHECKREG r0, 0xFFFFFFBC;
CHECKREG r1, 0xFFFFFFBC;
CHECKREG r2, 0xFFFFFFBC;
CHECKREG r3, 0xFFFFFFBC;
CHECKREG r4, 0xFFFFFFBC;
CHECKREG r5, 0xFFFFFFBC;
CHECKREG r6, 0xFFFFFFBC;
CHECKREG r7, 0xFFFFFFBC;
imm32 r0, 0x01230002;
imm32 r1, 0x00374659;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R0 = R1.B (X);
R2 = R1.B (X);
R3 = R1.B (X);
R4 = R1.B (X);
R5 = R1.B (X);
R6 = R1.B (X);
R7 = R1.B (X);
R1 = R1.B (X);
CHECKREG r0, 0x00000059;
CHECKREG r1, 0x00000059;
CHECKREG r2, 0x00000059;
CHECKREG r3, 0x00000059;
CHECKREG r4, 0x00000059;
CHECKREG r5, 0x00000059;
CHECKREG r6, 0x00000059;
CHECKREG r7, 0x00000059;
imm32 r0, 0x10789abc;
imm32 r1, 0x11345678;
imm32 r2, 0x93156789;
imm32 r3, 0xd451789a;
imm32 r4, 0x856719ab;
imm32 r5, 0x267891bc;
imm32 r6, 0xa789ab1d;
imm32 r7, 0x989ab1de;
R0 = R2.B (X);
R1 = R2.B (X);
R3 = R2.B (X);
R4 = R2.B (X);
R5 = R2.B (X);
R6 = R2.B (X);
R7 = R2.B (X);
R2 = R2.B (X);
CHECKREG r0, 0xFFFFFF89;
CHECKREG r1, 0xFFFFFF89;
CHECKREG r2, 0xFFFFFF89;
CHECKREG r3, 0xFFFFFF89;
CHECKREG r4, 0xFFFFFF89;
CHECKREG r5, 0xFFFFFF89;
CHECKREG r6, 0xFFFFFF89;
CHECKREG r7, 0xFFFFFF89;
imm32 r0, 0x21230002;
imm32 r1, 0x02374659;
imm32 r2, 0x93256789;
imm32 r3, 0xa952789a;
imm32 r4, 0xb59729ab;
imm32 r5, 0xc67992bc;
imm32 r6, 0xd7899b2d;
imm32 r7, 0xe89ab9d2;
R0 = R3.B (X);
R1 = R3.B (X);
R2 = R3.B (X);
R4 = R3.B (X);
R5 = R3.B (X);
R6 = R3.B (X);
R7 = R3.B (X);
R3 = R3.B (X);
CHECKREG r0, 0xFFFFFF9A;
CHECKREG r1, 0xFFFFFF9A;
CHECKREG r2, 0xFFFFFF9A;
CHECKREG r3, 0xFFFFFF9A;
CHECKREG r4, 0xFFFFFF9A;
CHECKREG r5, 0xFFFFFF9A;
CHECKREG r6, 0xFFFFFF9A;
CHECKREG r7, 0xFFFFFF9A;
imm32 r0, 0xa0789abc;
imm32 r1, 0x1a345678;
imm32 r2, 0x23a56789;
imm32 r3, 0x645a789a;
imm32 r4, 0x8667a9ab;
imm32 r5, 0x96689abc;
imm32 r6, 0xa787abad;
imm32 r7, 0xb89a7cda;
R0 = R4.B (X);
R1 = R4.B (X);
R2 = R4.B (X);
R3 = R4.B (X);
R4 = R4.B (X);
R5 = R4.B (X);
R6 = R4.B (X);
R7 = R4.B (X);
CHECKREG r0, 0xFFFFFFAB;
CHECKREG r1, 0xFFFFFFAB;
CHECKREG r2, 0xFFFFFFAB;
CHECKREG r3, 0xFFFFFFAB;
CHECKREG r4, 0xFFFFFFAB;
CHECKREG r5, 0xFFFFFFAB;
CHECKREG r6, 0xFFFFFFAB;
CHECKREG r7, 0xFFFFFFAB;
imm32 r0, 0xf1230002;
imm32 r1, 0x0f374659;
imm32 r2, 0x93f56789;
imm32 r3, 0xa45f789a;
imm32 r4, 0xb567f9ab;
imm32 r5, 0xc6789fbc;
imm32 r6, 0xd789abfd;
imm32 r7, 0xe89abcdf;
R0 = R5.B (X);
R1 = R5.B (X);
R2 = R5.B (X);
R3 = R5.B (X);
R4 = R5.B (X);
R6 = R5.B (X);
R7 = R5.B (X);
R5 = R5.B (X);
CHECKREG r0, 0xFFFFFFBC;
CHECKREG r1, 0xFFFFFFBC;
CHECKREG r2, 0xFFFFFFBC;
CHECKREG r3, 0xFFFFFFBC;
CHECKREG r4, 0xFFFFFFBC;
CHECKREG r5, 0xFFFFFFBC;
CHECKREG r6, 0xFFFFFFBC;
CHECKREG r7, 0xFFFFFFBC;
imm32 r0, 0xe0789abc;
imm32 r1, 0xe2345678;
imm32 r2, 0x2e456789;
imm32 r3, 0x34e6789a;
imm32 r4, 0x856e89ab;
imm32 r5, 0x9678eabc;
imm32 r6, 0xa789aecd;
imm32 r7, 0xb89abcee;
R0 = R6.B (X);
R1 = R6.B (X);
R2 = R6.B (X);
R3 = R6.B (X);
R4 = R6.B (X);
R5 = R6.B (X);
R7 = R6.B (X);
R6 = R6.B (X);
CHECKREG r0, 0xFFFFFFCD;
CHECKREG r1, 0xFFFFFFCD;
CHECKREG r2, 0xFFFFFFCD;
CHECKREG r3, 0xFFFFFFCD;
CHECKREG r4, 0xFFFFFFCD;
CHECKREG r5, 0xFFFFFFCD;
CHECKREG r6, 0xFFFFFFCD;
CHECKREG r7, 0xFFFFFFCD;
imm32 r0, 0x012300f5;
imm32 r1, 0x80374659;
imm32 r2, 0x98456589;
imm32 r3, 0xa486589a;
imm32 r4, 0xb56589ab;
imm32 r5, 0xc6588abc;
imm32 r6, 0xd589a8cd;
imm32 r7, 0x589abc88;
R0 = R7.B (X);
R1 = R7.B (X);
R2 = R7.B (X);
R3 = R7.B (X);
R4 = R7.B (X);
R5 = R7.B (X);
R6 = R7.B (X);
R7 = R7.B (X);
CHECKREG r0, 0xFFFFFF88;
CHECKREG r1, 0xFFFFFF88;
CHECKREG r2, 0xFFFFFF88;
CHECKREG r3, 0xFFFFFF88;
CHECKREG r4, 0xFFFFFF88;
CHECKREG r5, 0xFFFFFF88;
CHECKREG r6, 0xFFFFFF88;
CHECKREG r7, 0xFFFFFF88;
pass

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sim/testsuite/sim/bfin/c_alu2op_conv_xh.s Normal file
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//Original:/testcases/core/c_alu2op_conv_xh/c_alu2op_conv_xh.dsp
// Spec Reference: alu2op convert xh
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00789abc;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0 = R0.L (X);
R1 = R0.L (X);
R2 = R0.L (X);
R3 = R0.L (X);
R4 = R0.L (X);
R5 = R0.L (X);
R6 = R0.L (X);
R7 = R0.L (X);
CHECKREG r0, 0xFFFF9ABC;
CHECKREG r1, 0xFFFF9ABC;
CHECKREG r2, 0xFFFF9ABC;
CHECKREG r3, 0xFFFF9ABC;
CHECKREG r4, 0xFFFF9ABC;
CHECKREG r5, 0xFFFF9ABC;
CHECKREG r6, 0xFFFF9ABC;
CHECKREG r7, 0xFFFF9ABC;
imm32 r0, 0x01230002;
imm32 r1, 0x00374659;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R0 = R1.L (X);
R2 = R1.L (X);
R3 = R1.L (X);
R4 = R1.L (X);
R5 = R1.L (X);
R6 = R1.L (X);
R7 = R1.L (X);
R1 = R1.L (X);
CHECKREG r0, 0x00004659;
CHECKREG r1, 0x00004659;
CHECKREG r2, 0x00004659;
CHECKREG r3, 0x00004659;
CHECKREG r4, 0x00004659;
CHECKREG r5, 0x00004659;
CHECKREG r6, 0x00004659;
CHECKREG r7, 0x00004659;
imm32 r0, 0x10789abc;
imm32 r1, 0x11345678;
imm32 r2, 0x93156789;
imm32 r3, 0xd451789a;
imm32 r4, 0x856719ab;
imm32 r5, 0x267891bc;
imm32 r6, 0xa789ab1d;
imm32 r7, 0x989ab1de;
R0 = R2.L (X);
R1 = R2.L (X);
R3 = R2.L (X);
R4 = R2.L (X);
R5 = R2.L (X);
R6 = R2.L (X);
R7 = R2.L (X);
R2 = R2.L (X);
CHECKREG r0, 0x00006789;
CHECKREG r1, 0x00006789;
CHECKREG r2, 0x00006789;
CHECKREG r3, 0x00006789;
CHECKREG r4, 0x00006789;
CHECKREG r5, 0x00006789;
CHECKREG r6, 0x00006789;
CHECKREG r7, 0x00006789;
imm32 r0, 0x21230002;
imm32 r1, 0x02374659;
imm32 r2, 0x93256789;
imm32 r3, 0xa952789a;
imm32 r4, 0xb59729ab;
imm32 r5, 0xc67992bc;
imm32 r6, 0xd7899b2d;
imm32 r7, 0xe89ab9d2;
R0 = R3.L (X);
R1 = R3.L (X);
R2 = R3.L (X);
R4 = R3.L (X);
R5 = R3.L (X);
R6 = R3.L (X);
R7 = R3.L (X);
R3 = R3.L (X);
CHECKREG r0, 0x0000789A;
CHECKREG r1, 0x0000789A;
CHECKREG r2, 0x0000789A;
CHECKREG r3, 0x0000789A;
CHECKREG r4, 0x0000789A;
CHECKREG r5, 0x0000789A;
CHECKREG r6, 0x0000789A;
CHECKREG r7, 0x0000789A;
imm32 r0, 0xa0789abc;
imm32 r1, 0x1a345678;
imm32 r2, 0x23a56789;
imm32 r3, 0x645a789a;
imm32 r4, 0x8667a9ab;
imm32 r5, 0x96689abc;
imm32 r6, 0xa787abad;
imm32 r7, 0xb89a7cda;
R0 = R4.L (X);
R1 = R4.L (X);
R2 = R4.L (X);
R3 = R4.L (X);
R4 = R4.L (X);
R5 = R4.L (X);
R6 = R4.L (X);
R7 = R4.L (X);
CHECKREG r0, 0xFFFFA9AB;
CHECKREG r1, 0xFFFFA9AB;
CHECKREG r2, 0xFFFFA9AB;
CHECKREG r3, 0xFFFFA9AB;
CHECKREG r4, 0xFFFFA9AB;
CHECKREG r5, 0xFFFFA9AB;
CHECKREG r6, 0xFFFFA9AB;
CHECKREG r7, 0xFFFFA9AB;
imm32 r0, 0xf1230002;
imm32 r1, 0x0f374659;
imm32 r2, 0x93f56789;
imm32 r3, 0xa45f789a;
imm32 r4, 0xb567f9ab;
imm32 r5, 0xc6789fbc;
imm32 r6, 0xd789abfd;
imm32 r7, 0xe89abcdf;
R0 = R5.L (X);
R1 = R5.L (X);
R2 = R5.L (X);
R3 = R5.L (X);
R4 = R5.L (X);
R6 = R5.L (X);
R7 = R5.L (X);
R5 = R5.L (X);
CHECKREG r0, 0xFFFF9FBC;
CHECKREG r1, 0xFFFF9FBC;
CHECKREG r2, 0xFFFF9FBC;
CHECKREG r3, 0xFFFF9FBC;
CHECKREG r4, 0xFFFF9FBC;
CHECKREG r5, 0xFFFF9FBC;
CHECKREG r6, 0xFFFF9FBC;
CHECKREG r7, 0xFFFF9FBC;
imm32 r0, 0xe0789abc;
imm32 r1, 0xe2345678;
imm32 r2, 0x2e456789;
imm32 r3, 0x34e6789a;
imm32 r4, 0x856e89ab;
imm32 r5, 0x9678eabc;
imm32 r6, 0xa789aecd;
imm32 r7, 0xb89abcee;
R0 = R6.L (X);
R1 = R6.L (X);
R2 = R6.L (X);
R3 = R6.L (X);
R4 = R6.L (X);
R5 = R6.L (X);
R7 = R6.L (X);
R6 = R6.L (X);
CHECKREG r0, 0xFFFFAECD;
CHECKREG r1, 0xFFFFAECD;
CHECKREG r2, 0xFFFFAECD;
CHECKREG r3, 0xFFFFAECD;
CHECKREG r4, 0xFFFFAECD;
CHECKREG r5, 0xFFFFAECD;
CHECKREG r6, 0xFFFFAECD;
CHECKREG r7, 0xFFFFAECD;
imm32 r0, 0x012300f5;
imm32 r1, 0x80374659;
imm32 r2, 0x98456589;
imm32 r3, 0xa486589a;
imm32 r4, 0xb56589ab;
imm32 r5, 0xc6588abc;
imm32 r6, 0xd589a8cd;
imm32 r7, 0x589abc88;
R0 = R7.L (X);
R1 = R7.L (X);
R2 = R7.L (X);
R3 = R7.L (X);
R4 = R7.L (X);
R5 = R7.L (X);
R6 = R7.L (X);
R7 = R7.L (X);
CHECKREG r0, 0xFFFFBC88;
CHECKREG r1, 0xFFFFBC88;
CHECKREG r2, 0xFFFFBC88;
CHECKREG r3, 0xFFFFBC88;
CHECKREG r4, 0xFFFFBC88;
CHECKREG r5, 0xFFFFBC88;
CHECKREG r6, 0xFFFFBC88;
CHECKREG r7, 0xFFFFBC88;
pass

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sim/testsuite/sim/bfin/c_alu2op_divq.s Normal file
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//Original:/testcases/core/c_alu2op_divq/c_alu2op_divq.dsp
// Spec Reference: alu2op divide q
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0.L = 1;
DIVQ ( R1 , R0 );
DIVQ ( R2 , R0 );
DIVQ ( R3 , R0 );
DIVQ ( R4 , R0 );
DIVQ ( R5 , R0 );
DIVQ ( R6 , R0 );
DIVQ ( R7 , R0 );
DIVQ ( R4 , R0 );
DIVQ ( R0 , R0 );
CHECKREG r1, 0x2466ACF1;
CHECKREG r2, 0x4688CF13;
CHECKREG r3, 0x68AAF135;
CHECKREG r4, 0x159C26AD;
CHECKREG r5, 0x2CF33578;
CHECKREG r6, 0x4F15579A;
CHECKREG r7, 0x713779BC;
CHECKREG r0, 0xFFFE0002;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R1.L = -1;
DIVQ ( R0 , R1 );
DIVQ ( R2 , R1 );
DIVQ ( R3 , R1 );
DIVQ ( R4 , R1 );
DIVQ ( R5 , R1 );
DIVQ ( R6 , R1 );
DIVQ ( R7 , R1 );
DIVQ ( R1 , R1 );
CHECKREG r0, 0x02440004;
CHECKREG r1, 0x0003FFFE;
CHECKREG r2, 0x2688CF13;
CHECKREG r3, 0x48AEF135;
CHECKREG r4, 0x6AD11357;
CHECKREG r5, 0x8CF33579;
CHECKREG r6, 0xAF15579B;
CHECKREG r7, 0xD13779BD;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0x00000000;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 31;
DIVQ ( R0 , R2 );
DIVQ ( R1 , R2 );
DIVQ ( R3 , R2 );
DIVQ ( R4 , R2 );
DIVQ ( R5 , R2 );
DIVQ ( R6 , R2 );
DIVQ ( R7 , R2 );
DIVQ ( R2 , R2 );
CHECKREG r0, 0xA2840005;
CHECKREG r1, 0x242AACF1;
CHECKREG r2, 0xFFC2003E;
CHECKREG r3, 0x686EF135;
CHECKREG r4, 0x2A911356;
CHECKREG r5, 0x0D2F3578;
CHECKREG r6, 0xCF51579B;
CHECKREG r7, 0xF0F779BD;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0x00000000;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R3.L = -31;
DIVQ ( R0 , R3 );
DIVQ ( R1 , R3 );
DIVQ ( R2 , R3 );
DIVQ ( R4 , R3 );
DIVQ ( R5 , R3 );
DIVQ ( R6 , R3 );
DIVQ ( R7 , R3 );
DIVQ ( R3 , R3 );
CHECKREG r0, 0x02080004;
CHECKREG r1, 0x042AACF1;
CHECKREG r2, 0x26C8CF13;
CHECKREG r3, 0x003FFFC2;
CHECKREG r4, 0x6B0D1357;
CHECKREG r5, 0x8D2F3579;
CHECKREG r6, 0xAF51579B;
CHECKREG r7, 0xD17379BD;
imm32 r0, 0x00000001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x00000000;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R4.L = 15;
DIVQ ( R1 , R4 );
DIVQ ( R2 , R4 );
DIVQ ( R3 , R4 );
DIVQ ( R0 , R4 );
DIVQ ( R5 , R4 );
DIVQ ( R6 , R4 );
DIVQ ( R7 , R4 );
DIVQ ( R4 , R4 );
CHECKREG r0, 0xFFE20002;
CHECKREG r1, 0x2486ACF1;
CHECKREG r2, 0x466CCF13;
CHECKREG r3, 0x688EF135;
CHECKREG r4, 0x001E001F;
CHECKREG r5, 0x2D0F3578;
CHECKREG r6, 0x4F31579A;
CHECKREG r7, 0x715379BC;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0x00000000;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R5.L = -15;
DIVQ ( R0 , R5 );
DIVQ ( R1 , R5 );
DIVQ ( R2 , R5 );
DIVQ ( R3 , R5 );
DIVQ ( R4 , R5 );
DIVQ ( R6 , R5 );
DIVQ ( R7 , R5 );
DIVQ ( R5 , R5 );
CHECKREG r0, 0x02640004;
CHECKREG r1, 0xFFE20001;
CHECKREG r2, 0x26A8CF13;
CHECKREG r3, 0x48CAF135;
CHECKREG r4, 0x6AED1357;
CHECKREG r5, 0x001FFFE2;
CHECKREG r6, 0xAF31579B;
CHECKREG r7, 0xD15379BD;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0xb1256790;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x00000000;
imm32 r7, 0x789abcde;
R6.L = 24;
DIVQ ( R0 , R6 );
DIVQ ( R1 , R6 );
DIVQ ( R2 , R6 );
DIVQ ( R3 , R6 );
DIVQ ( R4 , R6 );
DIVQ ( R5 , R6 );
DIVQ ( R7 , R6 );
DIVQ ( R6 , R6 );
CHECKREG r0, 0xA2760005;
CHECKREG r1, 0x2438ACF1;
CHECKREG r2, 0x621ACF20;
CHECKREG r3, 0x68DCF135;
CHECKREG r4, 0x2A9F1356;
CHECKREG r5, 0x0D213578;
CHECKREG r6, 0xFFD00030;
CHECKREG r7, 0xF16579BD;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0x00000000;
R7.L = -24;
DIVQ ( R0 , R7 );
DIVQ ( R1 , R7 );
DIVQ ( R2 , R7 );
DIVQ ( R3 , R7 );
DIVQ ( R4 , R7 );
DIVQ ( R5 , R7 );
DIVQ ( R6 , R7 );
DIVQ ( R7 , R7 );
CHECKREG r0, 0x02160004;
CHECKREG r1, 0x0438ACF1;
CHECKREG r2, 0x26BACF13;
CHECKREG r3, 0x48DCF135;
CHECKREG r4, 0x6AFF1357;
CHECKREG r5, 0x8D213579;
CHECKREG r6, 0xAF43579B;
CHECKREG r7, 0x0031FFD0;
pass

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sim/testsuite/sim/bfin/c_alu2op_divs.s Normal file
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//Original:/testcases/core/c_alu2op_divs/c_alu2op_divs.dsp
// Spec Reference: alu2op divide s
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0.L = 1;
DIVS ( R1 , R0 );
DIVS ( R2 , R0 );
DIVS ( R3 , R0 );
DIVS ( R4 , R0 );
DIVS ( R5 , R0 );
DIVS ( R6 , R0 );
DIVS ( R7 , R0 );
DIVS ( R4 , R0 );
DIVS ( R0 , R0 );
CHECKREG r1, 0x2468ACF0;
CHECKREG r2, 0x468ACF12;
CHECKREG r3, 0x68ACF134;
CHECKREG r4, 0x159E26AE;
CHECKREG r5, 0x2CF13579;
CHECKREG r6, 0x4F13579B;
CHECKREG r7, 0x713579BD;
CHECKREG r0, 0x00000002;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R1.L = -1;
DIVS ( R0 , R1 );
DIVS ( R2 , R1 );
DIVS ( R3 , R1 );
DIVS ( R4 , R1 );
DIVS ( R5 , R1 );
DIVS ( R6 , R1 );
DIVS ( R7 , R1 );
DIVS ( R1 , R1 );
CHECKREG r0, 0x02460005;
CHECKREG r1, 0x0001FFFF;
CHECKREG r2, 0x268ACF12;
CHECKREG r3, 0x48ACF134;
CHECKREG r4, 0x6ACF1356;
CHECKREG r5, 0x8CF13578;
CHECKREG r6, 0xAF13579A;
CHECKREG r7, 0xD13579BC;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0x00000000;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 31;
DIVS ( R0 , R2 );
DIVS ( R1 , R2 );
DIVS ( R3 , R2 );
DIVS ( R4 , R2 );
DIVS ( R5 , R2 );
DIVS ( R6 , R2 );
DIVS ( R7 , R2 );
DIVS ( R2 , R2 );
CHECKREG r0, 0xA2460004;
CHECKREG r1, 0x2468ACF0;
CHECKREG r2, 0x0000003E;
CHECKREG r3, 0x68ACF134;
CHECKREG r4, 0x2ACF1357;
CHECKREG r5, 0x0CF13579;
CHECKREG r6, 0xCF13579A;
CHECKREG r7, 0xF13579BC;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0x00000000;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R3.L = -31;
DIVS ( R0 , R3 );
DIVS ( R1 , R3 );
DIVS ( R2 , R3 );
DIVS ( R4 , R3 );
DIVS ( R5 , R3 );
DIVS ( R6 , R3 );
DIVS ( R7 , R3 );
DIVS ( R3 , R3 );
CHECKREG r0, 0x02460005;
CHECKREG r1, 0x0468ACF0;
CHECKREG r2, 0x268ACF12;
CHECKREG r3, 0x0001FFC3;
CHECKREG r4, 0x6ACF1356;
CHECKREG r5, 0x8CF13578;
CHECKREG r6, 0xAF13579A;
CHECKREG r7, 0xD13579BC;
imm32 r0, 0x00000001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x00000000;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R4.L = 15;
DIVS ( R1 , R4 );
DIVS ( R2 , R4 );
DIVS ( R3 , R4 );
DIVS ( R0 , R4 );
DIVS ( R5 , R4 );
DIVS ( R6 , R4 );
DIVS ( R7 , R4 );
DIVS ( R4 , R4 );
CHECKREG r0, 0x00000002;
CHECKREG r1, 0x2468ACF0;
CHECKREG r2, 0x468ACF12;
CHECKREG r3, 0x68ACF134;
CHECKREG r4, 0x0000001E;
CHECKREG r5, 0x2CF13579;
CHECKREG r6, 0x4F13579B;
CHECKREG r7, 0x713579BD;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0x00000000;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R5.L = -15;
DIVS ( R0 , R5 );
DIVS ( R1 , R5 );
DIVS ( R2 , R5 );
DIVS ( R3 , R5 );
DIVS ( R4 , R5 );
DIVS ( R6 , R5 );
DIVS ( R7 , R5 );
DIVS ( R5 , R5 );
CHECKREG r0, 0x02460005;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x268ACF12;
CHECKREG r3, 0x48ACF134;
CHECKREG r4, 0x6ACF1356;
CHECKREG r5, 0x0001FFE3;
CHECKREG r6, 0xAF13579A;
CHECKREG r7, 0xD13579BC;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0xb1256790;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x00000000;
imm32 r7, 0x789abcde;
R6.L = 24;
DIVS ( R0 , R6 );
DIVS ( R1 , R6 );
DIVS ( R2 , R6 );
DIVS ( R3 , R6 );
DIVS ( R4 , R6 );
DIVS ( R5 , R6 );
DIVS ( R7 , R6 );
DIVS ( R6 , R6 );
CHECKREG r0, 0xA2460004;
CHECKREG r1, 0x2468ACF0;
CHECKREG r2, 0x624ACF21;
CHECKREG r3, 0x68ACF134;
CHECKREG r4, 0x2ACF1357;
CHECKREG r5, 0x0CF13579;
CHECKREG r6, 0x00000030;
CHECKREG r7, 0xF13579BC;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0x00000000;
R7.L = -24;
DIVS ( R0 , R7 );
DIVS ( R1 , R7 );
DIVS ( R2 , R7 );
DIVS ( R3 , R7 );
DIVS ( R4 , R7 );
DIVS ( R5 , R7 );
DIVS ( R6 , R7 );
DIVS ( R7 , R7 );
CHECKREG r0, 0x02460005;
CHECKREG r1, 0x0468ACF0;
CHECKREG r2, 0x268ACF12;
CHECKREG r3, 0x48ACF134;
CHECKREG r4, 0x6ACF1356;
CHECKREG r5, 0x8CF13578;
CHECKREG r6, 0xAF13579A;
CHECKREG r7, 0x0001FFD1;
pass

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//Original:/proj/frio/dv/testcases/core/c_alu2op_log_l_sft/c_alu2op_log_l_sft.dsp
// Spec Reference: alu2op logical left
# mach: bfin
.include "testutils.inc"
start
R0 = 0;
ASTAT = R0;
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0.L = 1;
R1 <<= R0;
R2 <<= R0;
R3 <<= R0;
R4 <<= R0;
R5 <<= R0;
R6 <<= R0;
R7 <<= R0;
R4 <<= R0;
R0 <<= R0;
CHECKREG r1, 0x2468ACF0;
CHECKREG r2, 0x468ACF12;
CHECKREG r3, 0x68ACF134;
CHECKREG r4, 0x159E26AC;
CHECKREG r5, 0x2CF13578;
CHECKREG r6, 0x4F13579A;
CHECKREG r7, 0x713579BC;
CHECKREG r0, 0x00000002;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R1.L = -1;
R0 <<= R1;
R2 <<= R1;
R3 <<= R1;
R4 <<= R1;
R5 <<= R1;
R6 <<= R1;
R7 <<= R1;
R1 <<= R1;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0x00000000;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 31;
R0 <<= R2;
R1 <<= R2;
R3 <<= R2;
R4 <<= R2;
R5 <<= R2;
R6 <<= R2;
R7 <<= R2;
R2 <<= R2;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x80000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x80000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0x00000000;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R3.L = -31;
R0 <<= R3;
R1 <<= R3;
R2 <<= R3;
R4 <<= R3;
R5 <<= R3;
R6 <<= R3;
R7 <<= R3;
R3 <<= R3;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x00000001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x00000000;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R4.L = 15;
R1 <<= R4;
R2 <<= R4;
R3 <<= R4;
R0 <<= R4;
R5 <<= R4;
R6 <<= R4;
R7 <<= R4;
R4 <<= R4;
CHECKREG r0, 0x00008000;
CHECKREG r1, 0x2B3C0000;
CHECKREG r2, 0xB3C48000;
CHECKREG r3, 0x3C4D0000;
CHECKREG r4, 0x00078000;
CHECKREG r5, 0x4D5E0000;
CHECKREG r6, 0xD5E68000;
CHECKREG r7, 0x5E6F0000;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0x00000000;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R5.L = -15;
R0 <<= R5;
R1 <<= R5;
R2 <<= R5;
R3 <<= R5;
R4 <<= R5;
R6 <<= R5;
R7 <<= R5;
R5 <<= R5;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0xb1256790;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x00000000;
imm32 r7, 0x789abcde;
R6.L = 24;
R0 <<= R6;
R1 <<= R6;
R2 <<= R6;
R3 <<= R6;
R4 <<= R6;
R5 <<= R6;
R7 <<= R6;
R6 <<= R6;
CHECKREG r0, 0x02000000;
CHECKREG r1, 0x78000000;
CHECKREG r2, 0x90000000;
CHECKREG r3, 0x9A000000;
CHECKREG r4, 0xAB000000;
CHECKREG r5, 0xBC000000;
CHECKREG r6, 0x18000000;
CHECKREG r7, 0xDE000000;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0x00000000;
R7.L = -24;
R0 <<= R7;
R1 <<= R7;
R2 <<= R7;
R3 <<= R7;
R4 <<= R7;
R5 <<= R7;
R6 <<= R7;
R7 <<= R7;
CHECKREG r0, 0x00;
CHECKREG r1, 0x00;
CHECKREG r2, 0x00;
CHECKREG r3, 0x00;
CHECKREG r4, 0x00;
CHECKREG r5, 0x00;
CHECKREG r6, 0x00;
CHECKREG r7, 0x00;
pass

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//Original:/proj/frio/dv/testcases/core/c_alu2op_log_r_sft/c_alu2op_log_r_sft.dsp
// Spec Reference: alu2op logical right
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x856789ab;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R0.L = 1;
R1 >>= R0;
R2 >>= R0;
R3 >>= R0;
R4 >>= R0;
R5 >>= R0;
R6 >>= R0;
R7 >>= R0;
R4 >>= R0;
R0 >>= R0;
CHECKREG r1, 0x091A2B3C;
CHECKREG r2, 0x11A2B3C4;
CHECKREG r3, 0x1A2B3C4D;
CHECKREG r4, 0x2159E26A;
CHECKREG r5, 0x4B3C4D5E;
CHECKREG r6, 0x53C4D5E6;
CHECKREG r7, 0x5C4D5E6F;
CHECKREG r0, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R1.L = -1;
R0 >>= R1;
R2 >>= R1;
R3 >>= R1;
R4 >>= R1;
R5 >>= R1;
R6 >>= R1;
R7 >>= R1;
R1 >>= R1;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0x00000000;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x6789abcd;
imm32 r7, 0x789abcde;
R2.L = 31;
R0 >>= R2;
R1 >>= R2;
R3 >>= R2;
R4 >>= R2;
R5 >>= R2;
R6 >>= R2;
R7 >>= R2;
R2 >>= R2;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000001;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0x00000000;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R3.L = -31;
R0 >>= R3;
R1 >>= R3;
R2 >>= R3;
R4 >>= R3;
R5 >>= R3;
R6 >>= R3;
R7 >>= R3;
R3 >>= R3;
CHECKREG r0, 0x00;
CHECKREG r1, 0x0;
CHECKREG r2, 0x0;
CHECKREG r3, 0x0;
CHECKREG r4, 0x0;
CHECKREG r5, 0x0;
CHECKREG r6, 0x0;
CHECKREG r7, 0x0;
imm32 r0, 0x00000001;
imm32 r1, 0x12345678;
imm32 r2, 0x23456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x00000000;
imm32 r5, 0x96789abc;
imm32 r6, 0xa789abcd;
imm32 r7, 0xb89abcde;
R4.L = 15;
R1 >>= R4;
R2 >>= R4;
R3 >>= R4;
R0 >>= R4;
R5 >>= R4;
R6 >>= R4;
R7 >>= R4;
R4 >>= R4;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00002468;
CHECKREG r2, 0x0000468A;
CHECKREG r3, 0x000068AC;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00012CF1;
CHECKREG r6, 0x00014F13;
CHECKREG r7, 0x00017135;
imm32 r0, 0x01230002;
imm32 r1, 0x00000000;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0x00000000;
imm32 r6, 0xd789abcd;
imm32 r7, 0xe89abcde;
R5.L = -15;
R0 >>= R5;
R1 >>= R5;
R2 >>= R5;
R3 >>= R5;
R4 >>= R5;
R6 >>= R5;
R7 >>= R5;
R5 >>= R5;
CHECKREG r0, 0x000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x0000;
CHECKREG r3, 0x0000;
CHECKREG r4, 0x0000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x0000;
CHECKREG r7, 0x0000;
imm32 r0, 0x51230002;
imm32 r1, 0x12345678;
imm32 r2, 0xb1256790;
imm32 r3, 0x3456789a;
imm32 r4, 0x956789ab;
imm32 r5, 0x86789abc;
imm32 r6, 0x00000000;
imm32 r7, 0x789abcde;
R6.L = 24;
R0 >>= R6;
R1 >>= R6;
R2 >>= R6;
R3 >>= R6;
R4 >>= R6;
R5 >>= R6;
R7 >>= R6;
R6 >>= R6;
CHECKREG r0, 0x00000051;
CHECKREG r1, 0x00000012;
CHECKREG r2, 0x000000B1;
CHECKREG r3, 0x00000034;
CHECKREG r4, 0x00000095;
CHECKREG r5, 0x00000086;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000078;
imm32 r0, 0x01230002;
imm32 r1, 0x82345678;
imm32 r2, 0x93456789;
imm32 r3, 0xa456789a;
imm32 r4, 0xb56789ab;
imm32 r5, 0xc6789abc;
imm32 r6, 0xd789abcd;
imm32 r7, 0x00000000;
R7.L = -24;
R0 >>= R7;
R1 >>= R7;
R2 >>= R7;
R3 >>= R7;
R4 >>= R7;
R5 >>= R7;
R6 >>= R7;
R7 >>= R7;
CHECKREG r0, 0x00;
CHECKREG r1, 0x00;
CHECKREG r2, 0x00;
CHECKREG r3, 0x00;
CHECKREG r4, 0x00;
CHECKREG r5, 0x00;
CHECKREG r6, 0x00;
CHECKREG r7, 0x00;
pass

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//Original:/testcases/core/c_alu2op_shadd_1/c_alu2op_shadd_1.dsp
// Spec Reference: alu2op shadd 1
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x03417990;
imm32 r1, 0x12315678;
imm32 r2, 0x23416789;
imm32 r3, 0x3451789a;
imm32 r4, 0x856189ab;
imm32 r5, 0x96719abc;
imm32 r6, 0xa781abcd;
imm32 r7, 0xb891bcde;
R1 = ( R1 + R0 ) << 1;
R2 = ( R2 + R0 ) << 1;
R3 = ( R3 + R0 ) << 1;
R4 = ( R4 + R0 ) << 1;
R5 = ( R5 + R0 ) << 1;
R6 = ( R6 + R0 ) << 1;
R7 = ( R7 + R0 ) << 1;
R0 = ( R0 + R0 ) << 1;
CHECKREG r0, 0x0D05E640;
CHECKREG r1, 0x2AE5A010;
CHECKREG r2, 0x4D05C232;
CHECKREG r3, 0x6F25E454;
CHECKREG r4, 0x11460676;
CHECKREG r5, 0x33662898;
CHECKREG r6, 0x55864ABA;
CHECKREG r7, 0x77A66CDC;
imm32 r0, 0x03457290;
imm32 r1, 0x12345278;
imm32 r2, 0x23456289;
imm32 r3, 0x3456729a;
imm32 r4, 0x856782ab;
imm32 r5, 0x967892bc;
imm32 r6, 0xa789a2cd;
imm32 r7, 0xb89ab2de;
R0 = ( R0 + R1 ) << 1;
R2 = ( R2 + R1 ) << 1;
R3 = ( R3 + R1 ) << 1;
R4 = ( R4 + R1 ) << 1;
R5 = ( R5 + R1 ) << 1;
R6 = ( R6 + R1 ) << 1;
R7 = ( R7 + R1 ) << 1;
R1 = ( R1 + R1 ) << 1;
CHECKREG r0, 0x2AF38A10;
CHECKREG r1, 0x48D149E0;
CHECKREG r2, 0x6AF36A02;
CHECKREG r3, 0x8D158A24;
CHECKREG r4, 0x2F37AA46;
CHECKREG r5, 0x5159CA68;
CHECKREG r6, 0x737BEA8A;
CHECKREG r7, 0x959E0AAC;
imm32 r0, 0x03457930;
imm32 r1, 0x12345638;
imm32 r2, 0x23456739;
imm32 r3, 0x3456783a;
imm32 r4, 0x8567893b;
imm32 r5, 0x96789a3c;
imm32 r6, 0xa789ab3d;
imm32 r7, 0xb89abc3e;
R0 = ( R0 + R2 ) << 1;
R1 = ( R1 + R2 ) << 1;
R3 = ( R3 + R2 ) << 1;
R4 = ( R4 + R2 ) << 1;
R5 = ( R5 + R2 ) << 1;
R6 = ( R6 + R2 ) << 1;
R7 = ( R7 + R2 ) << 1;
R2 = ( R2 + R2 ) << 1;
CHECKREG r0, 0x4D15C0D2;
CHECKREG r1, 0x6AF37AE2;
CHECKREG r2, 0x8D159CE4;
CHECKREG r3, 0xAF37BEE6;
CHECKREG r4, 0x5159E0E8;
CHECKREG r5, 0x737C02EA;
CHECKREG r6, 0x959E24EC;
CHECKREG r7, 0xB7C046EE;
imm32 r0, 0x04457990;
imm32 r1, 0x14345678;
imm32 r2, 0x24456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x846789ab;
imm32 r5, 0x94789abc;
imm32 r6, 0xa489abcd;
imm32 r7, 0xb49abcde;
R0 = ( R0 + R3 ) << 1;
R1 = ( R1 + R3 ) << 1;
R2 = ( R2 + R3 ) << 1;
R4 = ( R4 + R3 ) << 1;
R5 = ( R5 + R3 ) << 1;
R6 = ( R6 + R3 ) << 1;
R7 = ( R7 + R3 ) << 1;
R3 = ( R3 + R3 ) << 1;
CHECKREG r0, 0x7137E454;
CHECKREG r1, 0x91159E24;
CHECKREG r2, 0xB137C046;
CHECKREG r3, 0xD159E268;
CHECKREG r4, 0x717C048A;
CHECKREG r5, 0x919E26AC;
CHECKREG r6, 0xB1C048CE;
CHECKREG r7, 0xD1E26AF0;
imm32 r0, 0x03417990;
imm32 r1, 0x12315678;
imm32 r2, 0x23416789;
imm32 r3, 0x3451789a;
imm32 r4, 0x856189ab;
imm32 r5, 0x96719abc;
imm32 r6, 0xa781abcd;
imm32 r7, 0xb891bcde;
R0 = ( R0 + R4 ) << 1;
R1 = ( R1 + R4 ) << 1;
R2 = ( R2 + R4 ) << 1;
R3 = ( R3 + R4 ) << 1;
R5 = ( R5 + R4 ) << 1;
R6 = ( R6 + R4 ) << 1;
R7 = ( R7 + R4 ) << 1;
R4 = ( R4 + R4 ) << 1;
CHECKREG r0, 0x11460676;
CHECKREG r1, 0x2F25C046;
CHECKREG r2, 0x5145E268;
CHECKREG r3, 0x7366048A;
CHECKREG r4, 0x158626AC;
CHECKREG r5, 0x37A648CE;
CHECKREG r6, 0x59C66AF0;
CHECKREG r7, 0x7BE68D12;
imm32 r0, 0x03457290;
imm32 r1, 0x12345278;
imm32 r2, 0x23456289;
imm32 r3, 0x3456729a;
imm32 r4, 0x856782ab;
imm32 r5, 0x967892bc;
imm32 r6, 0xa789a2cd;
imm32 r7, 0xb89ab2de;
R0 = ( R0 + R5 ) << 1;
R1 = ( R1 + R5 ) << 1;
R2 = ( R2 + R5 ) << 1;
R3 = ( R3 + R5 ) << 1;
R4 = ( R4 + R5 ) << 1;
R6 = ( R6 + R5 ) << 1;
R7 = ( R7 + R5 ) << 1;
R5 = ( R5 + R5 ) << 1;
CHECKREG r0, 0x337C0A98;
CHECKREG r1, 0x5159CA68;
CHECKREG r2, 0x737BEA8A;
CHECKREG r3, 0x959E0AAC;
CHECKREG r4, 0x37C02ACE;
CHECKREG r5, 0x59E24AF0;
CHECKREG r6, 0x7C046B12;
CHECKREG r7, 0x9E268B34;
imm32 r0, 0x03457930;
imm32 r1, 0x12345638;
imm32 r2, 0x23456739;
imm32 r3, 0x3456783a;
imm32 r4, 0x8567893b;
imm32 r5, 0x96789a3c;
imm32 r6, 0xa789ab3d;
imm32 r7, 0xb89abc3e;
R0 = ( R0 + R6 ) << 1;
R1 = ( R1 + R6 ) << 1;
R2 = ( R2 + R6 ) << 1;
R3 = ( R3 + R6 ) << 1;
R4 = ( R4 + R6 ) << 1;
R5 = ( R5 + R6 ) << 1;
R7 = ( R7 + R6 ) << 1;
R6 = ( R6 + R6 ) << 1;
CHECKREG r0, 0x559E48DA;
CHECKREG r1, 0x737C02EA;
CHECKREG r2, 0x959E24EC;
CHECKREG r3, 0xB7C046EE;
CHECKREG r4, 0x59E268F0;
CHECKREG r5, 0x7C048AF2;
CHECKREG r6, 0x9E26ACF4;
CHECKREG r7, 0xC048CEF6;
imm32 r0, 0x04457990;
imm32 r1, 0x14345678;
imm32 r2, 0x24456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x846789ab;
imm32 r5, 0x94789abc;
imm32 r6, 0xa489abcd;
imm32 r7, 0xb49abcde;
R0 = ( R0 + R7 ) << 1;
R1 = ( R1 + R7 ) << 1;
R2 = ( R2 + R7 ) << 1;
R3 = ( R3 + R7 ) << 1;
R4 = ( R4 + R7 ) << 1;
R5 = ( R5 + R7 ) << 1;
R6 = ( R6 + R7 ) << 1;
R7 = ( R7 + R7 ) << 1;
CHECKREG r0, 0x71C06CDC;
CHECKREG r1, 0x919E26AC;
CHECKREG r2, 0xB1C048CE;
CHECKREG r3, 0xD1E26AF0;
CHECKREG r4, 0x72048D12;
CHECKREG r5, 0x9226AF34;
CHECKREG r6, 0xB248D156;
CHECKREG r7, 0xD26AF378;
pass

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//Original:/testcases/core/c_alu2op_shadd_2/c_alu2op_shadd_2.dsp
// Spec Reference: alu2op shadd 2
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x03417990;
imm32 r1, 0x12315678;
imm32 r2, 0x23416789;
imm32 r3, 0x3451789a;
imm32 r4, 0x856189ab;
imm32 r5, 0x96719abc;
imm32 r6, 0xa781abcd;
imm32 r7, 0xb891bcde;
R1 = ( R1 + R0 ) << 2;
R2 = ( R2 + R0 ) << 2;
R3 = ( R3 + R0 ) << 2;
R4 = ( R4 + R0 ) << 2;
R5 = ( R5 + R0 ) << 2;
R6 = ( R6 + R0 ) << 2;
R7 = ( R7 + R0 ) << 2;
R0 = ( R0 + R0 ) << 2;
CHECKREG r0, 0x1A0BCC80;
CHECKREG r1, 0x55CB4020;
CHECKREG r2, 0x9A0B8464;
CHECKREG r3, 0xDE4BC8A8;
CHECKREG r4, 0x228C0CEC;
CHECKREG r5, 0x66CC5130;
CHECKREG r6, 0xAB0C9574;
CHECKREG r7, 0xEF4CD9B8;
imm32 r0, 0x03457290;
imm32 r1, 0x12345278;
imm32 r2, 0x23456289;
imm32 r3, 0x3456729a;
imm32 r4, 0x856782ab;
imm32 r5, 0x967892bc;
imm32 r6, 0xa789a2cd;
imm32 r7, 0xb89ab2de;
R0 = ( R0 + R1 ) << 2;
R2 = ( R2 + R1 ) << 2;
R3 = ( R3 + R1 ) << 2;
R4 = ( R4 + R1 ) << 2;
R5 = ( R5 + R1 ) << 2;
R6 = ( R6 + R1 ) << 2;
R7 = ( R7 + R1 ) << 2;
R1 = ( R1 + R1 ) << 2;
CHECKREG r0, 0x55E71420;
CHECKREG r1, 0x91A293C0;
CHECKREG r2, 0xD5E6D404;
CHECKREG r3, 0x1A2B1448;
CHECKREG r4, 0x5E6F548C;
CHECKREG r5, 0xA2B394D0;
CHECKREG r6, 0xE6F7D514;
CHECKREG r7, 0x2B3C1558;
imm32 r0, 0x03457930;
imm32 r1, 0x12345638;
imm32 r2, 0x23456739;
imm32 r3, 0x3456783a;
imm32 r4, 0x8567893b;
imm32 r5, 0x96789a3c;
imm32 r6, 0xa789ab3d;
imm32 r7, 0xb89abc3e;
R0 = ( R0 + R2 ) << 2;
R1 = ( R1 + R2 ) << 2;
R3 = ( R3 + R2 ) << 2;
R4 = ( R4 + R2 ) << 2;
R5 = ( R5 + R2 ) << 2;
R6 = ( R6 + R2 ) << 2;
R7 = ( R7 + R2 ) << 2;
R2 = ( R2 + R2 ) << 2;
CHECKREG r0, 0x9A2B81A4;
CHECKREG r1, 0xD5E6F5C4;
CHECKREG r2, 0x1A2B39C8;
CHECKREG r3, 0x5E6F7DCC;
CHECKREG r4, 0xA2B3C1D0;
CHECKREG r5, 0xE6F805D4;
CHECKREG r6, 0x2B3C49D8;
CHECKREG r7, 0x6F808DDC;
imm32 r0, 0x04457990;
imm32 r1, 0x14345678;
imm32 r2, 0x24456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x846789ab;
imm32 r5, 0x94789abc;
imm32 r6, 0xa489abcd;
imm32 r7, 0xb49abcde;
R0 = ( R0 + R3 ) << 2;
R1 = ( R1 + R3 ) << 2;
R2 = ( R2 + R3 ) << 2;
R4 = ( R4 + R3 ) << 2;
R5 = ( R5 + R3 ) << 2;
R6 = ( R6 + R3 ) << 2;
R7 = ( R7 + R3 ) << 2;
R3 = ( R3 + R3 ) << 2;
CHECKREG r0, 0xE26FC8A8;
CHECKREG r1, 0x222B3C48;
CHECKREG r2, 0x626F808C;
CHECKREG r3, 0xA2B3C4D0;
CHECKREG r4, 0xE2F80914;
CHECKREG r5, 0x233C4D58;
CHECKREG r6, 0x6380919C;
CHECKREG r7, 0xA3C4D5E0;
imm32 r0, 0x03417990;
imm32 r1, 0x12315678;
imm32 r2, 0x23416789;
imm32 r3, 0x3451789a;
imm32 r4, 0x856189ab;
imm32 r5, 0x96719abc;
imm32 r6, 0xa781abcd;
imm32 r7, 0xb891bcde;
R0 = ( R0 + R4 ) << 2;
R1 = ( R1 + R4 ) << 2;
R2 = ( R2 + R4 ) << 2;
R3 = ( R3 + R4 ) << 2;
R5 = ( R5 + R4 ) << 2;
R6 = ( R6 + R4 ) << 2;
R7 = ( R7 + R4 ) << 2;
R4 = ( R4 + R4 ) << 2;
CHECKREG r0, 0x228C0CEC;
CHECKREG r1, 0x5E4B808C;
CHECKREG r2, 0xA28BC4D0;
CHECKREG r3, 0xE6CC0914;
CHECKREG r4, 0x2B0C4D58;
CHECKREG r5, 0x6F4C919C;
CHECKREG r6, 0xB38CD5E0;
CHECKREG r7, 0xF7CD1A24;
imm32 r0, 0x03457290;
imm32 r1, 0x12345278;
imm32 r2, 0x23456289;
imm32 r3, 0x3456729a;
imm32 r4, 0x856782ab;
imm32 r5, 0x967892bc;
imm32 r6, 0xa789a2cd;
imm32 r7, 0xb89ab2de;
R0 = ( R0 + R5 ) << 2;
R1 = ( R1 + R5 ) << 2;
R2 = ( R2 + R5 ) << 2;
R3 = ( R3 + R5 ) << 2;
R4 = ( R4 + R5 ) << 2;
R6 = ( R6 + R5 ) << 2;
R7 = ( R7 + R5 ) << 2;
R5 = ( R5 + R5 ) << 2;
CHECKREG r0, 0x66F81530;
CHECKREG r1, 0xA2B394D0;
CHECKREG r2, 0xE6F7D514;
CHECKREG r3, 0x2B3C1558;
CHECKREG r4, 0x6F80559C;
CHECKREG r5, 0xB3C495E0;
CHECKREG r6, 0xF808D624;
CHECKREG r7, 0x3C4D1668;
imm32 r0, 0x03457930;
imm32 r1, 0x12345638;
imm32 r2, 0x23456739;
imm32 r3, 0x3456783a;
imm32 r4, 0x8567893b;
imm32 r5, 0x96789a3c;
imm32 r6, 0xa789ab3d;
imm32 r7, 0xb89abc3e;
R0 = ( R0 + R6 ) << 2;
R1 = ( R1 + R6 ) << 2;
R2 = ( R2 + R6 ) << 2;
R3 = ( R3 + R6 ) << 2;
R4 = ( R4 + R6 ) << 2;
R5 = ( R5 + R6 ) << 2;
R7 = ( R7 + R6 ) << 2;
R6 = ( R6 + R6 ) << 2;
CHECKREG r0, 0xAB3C91B4;
CHECKREG r1, 0xE6F805D4;
CHECKREG r2, 0x2B3C49D8;
CHECKREG r3, 0x6F808DDC;
CHECKREG r4, 0xB3C4D1E0;
CHECKREG r5, 0xF80915E4;
CHECKREG r6, 0x3C4D59E8;
CHECKREG r7, 0x80919DEC;
imm32 r0, 0x04457990;
imm32 r1, 0x14345678;
imm32 r2, 0x24456789;
imm32 r3, 0x3456789a;
imm32 r4, 0x846789ab;
imm32 r5, 0x94789abc;
imm32 r6, 0xa489abcd;
imm32 r7, 0xb49abcde;
R0 = ( R0 + R7 ) << 2;
R1 = ( R1 + R7 ) << 2;
R2 = ( R2 + R7 ) << 2;
R3 = ( R3 + R7 ) << 2;
R4 = ( R4 + R7 ) << 2;
R5 = ( R5 + R7 ) << 2;
R6 = ( R6 + R7 ) << 2;
R7 = ( R7 + R7 ) << 2;
CHECKREG r0, 0xE380D9B8;
CHECKREG r1, 0x233C4D58;
CHECKREG r2, 0x6380919C;
CHECKREG r3, 0xA3C4D5E0;
CHECKREG r4, 0xE4091A24;
CHECKREG r5, 0x244D5E68;
CHECKREG r6, 0x6491A2AC;
CHECKREG r7, 0xA4D5E6F0;
pass

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//Original:/testcases/seq/c_br_preg_killed_ac/c_br_preg_killed_ac.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
imm32 p1, 0x00000011;
imm32 p2, 0x00000012;
P4 = 4;
P2 = 2;
loadsym P5, DATA0;
loadsym I0, DATA1;
begin:
ASTAT = R0; // clear CC
IF !CC JUMP LABEL1; // (bp);
CC = R4 < R5; // CC FLAG killed
R1 = 21;
LABEL1:
JUMP ( PC + P4 ); //brf LABEL2; // (bp);
CC = ! CC;
LABEL2:
JUMP ( PC + P4 ); //brf LABEL3; // (bp);
R2 = - R2; // ALU2op killed
LABEL3:
JUMP ( PC + P4 ); //brf LABEL4;
R3 <<= 2; // LOGI2op killed
LABEL4:
JUMP ( PC + P4 ); //brf LABEL5;
R0 = R1 + R2; // COMP3op killed
LABEL5:
JUMP ( PC + P4 ); //brf LABEL6;
R4 += 3; // COMPI2opD killed
LABEL6:
JUMP ( PC + P4 ); //brf LABEL7; // (bp);
R5 = 25; // LDIMMHALF killed
LABEL7:
JUMP ( PC + P4 ); //brf LABEL8;
R6 = CC; // CC2REG killed
LABEL8:
JUMP ( PC + P4 ); //brf LABEL9;
JUMP ( PC + P2 ); //BAD1; // UJUMP killed
LABEL9:
JUMP ( PC + P4 ); //brf LABELCHK1;
BAD1:
R7 = [ P5 ]; // LDST killed
LABELCHK1:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103

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//Original:/testcases/seq/c_br_preg_killed_ex1/c_br_preg_killed_ex1.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
imm32 p1, 0x00000011;
imm32 p2, 0x00000012;
.ifndef BFIN_HOST
imm32 p3, 0x00000013;
.endif
imm32 p4, 0x00000014;
P2 = 4;
loadsym p5, DATA0;
loadsym I0, DATA1;
begin:
ASTAT = R0; // clear CC
IF !CC JUMP LABEL1; // (bp);
CC = R4 < R5; // CC FLAG killed
R1 = 21;
LABEL1:
JUMP ( PC + P2 ); //brf LABEL2; // (bp);
CC = ! CC;
LABEL2:
IF !CC JUMP LABEL3; // (bp);
R2 = - R2; // ALU2op killed
LABEL3:
IF !CC JUMP LABEL4;
R3 <<= 2; // LOGI2op killed
LABEL4:
IF !CC JUMP LABEL5;
R0 = R1 + R2; // COMP3op killed
LABEL5:
IF !CC JUMP LABEL6;
R4 += 3; // COMPI2opD killed
LABEL6:
IF !CC JUMP LABEL7; // (bp);
R5 = 25; // LDIMMHALF killed
LABEL7:
IF !CC JUMP LABEL8;
R6 = CC; // CC2REG killed
LABEL8:
IF !CC JUMP LABEL9;
JUMP.S BAD1; // UJUMP killed
LABEL9:
IF !CC JUMP LABELCHK1;
BAD1:
R7 = [ P5 ]; // LDST killed
LABELCHK1:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103

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//Original:/testcases/seq/c_br_preg_stall_ac/c_br_preg_stall_ac.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
/* This test likes to assume the current [SP] is valid */
SP += -12;
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
imm32 p1, 0x00000011;
imm32 p2, 0x00000012;
.ifndef BFIN_HOST;
imm32 p3, 0x00000013;
.endif
imm32 p4, 0x00000014;
P1 = 4;
P2 = 6;
loadsym P5, DATA0;
loadsym I0, DATA1;
begin:
ASTAT = R0; // clear CC
R0 = CC;
IF CC R1 = R0;
[ SP ] = P2;
P2 = [ SP ];
JUMP ( PC + P2 ); //brf LABEL1; // (bp);
CC = R4 < R5; // CC FLAG killed
R1 = 21;
LABEL1:
JUMP ( PC + P1 ); // EX1 relative to 'brf LABEL1'
CC = ! CC;
LABEL2:
JUMP ( PC + P1 ); //brf LABEL3;
JUMP ( PC + P2 ); //BAD1; // UJUMP killed
LABEL3:
JUMP ( PC + P1 ); //brf LABELCHK1;
BAD1:
R7 = [ P5 ]; // LDST killed
LABELCHK1:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103

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//Original:/testcases/seq/c_br_preg_stall_ex1/c_br_preg_stall_ex1.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
imm32 p1, 0x00000011;
imm32 p2, 0x00000012;
.ifndef BFIN_HOST
imm32 p3, 0x00000013;
.endif
imm32 p4, 0x00000014;
P1 = 4;
P2 = 6;
loadsym p5, DATA0;
loadsym I0, DATA1;
begin:
ASTAT = R0; // clear CC
R0 = CC;
IF CC R1 = R0;
IF !CC JUMP LABEL1;
R0 = LC0;
R2 = R1 + R0;
LABEL1:
JUMP ( PC + P1 ); // EX1 relative to 'brf LABEL1'
CC = ! CC;
LABEL2:
JUMP ( PC + P1 ); //brf LABEL3;
JUMP ( PC + P2 ); //BAD1; // UJUMP killed
LABEL3:
JUMP ( PC + P1 ); //brf LABELCHK1;
BAD1:
R7 = [ P5 ]; // LDST killed
LABELCHK1:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103

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//Original:/testcases/core/c_brcc_bp1/c_brcc_bp1.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
CC = ! CC; // set cc=1
IF CC JUMP good1 (BP); // branch on true (should branch)
R1 = 1; // if go here, error
good1: IF !CC JUMP bad1; // branch on false (should not branch)
JUMP.S good2; // should branch here
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; // clear cc=0
IF !CC JUMP good3; // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF CC JUMP bad2; // branch on true (should not branch)
JUMP.S end; // we're done
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass

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//Original:/testcases/core/c_brcc_bp2/c_brcc_bp2.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
CC = ! CC; // set cc=1
IF CC JUMP good1 (BP); // branch on true (should branch)
R1 = 1; // if go here, error
good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch)
JUMP.S good2; // should branch here
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; // clear cc=0
IF !CC JUMP good3; // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF CC JUMP bad2; // branch on true (should not branch)
JUMP.S end; // we're done
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass

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//Original:/testcases/core/c_brcc_bp3/c_brcc_bp3.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
CC = ! CC; // set cc=1
IF CC JUMP good1 (BP); // branch on true (should branch)
R1 = 1; // if go here, error
good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch)
JUMP.S good2; // should branch here
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; // clear cc=0
IF !CC JUMP good3 (BP); // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF CC JUMP bad2; // branch on true (should not branch)
JUMP.S end; // we're done
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass

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//Original:/testcases/core/c_brcc_bp4/c_brcc_bp4.dsp
// Spec Reference: brcc bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
CC = ! CC; // set cc=1
IF CC JUMP good1 (BP); // branch on true (should branch)
R1 = 1; // if go here, error
good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch)
JUMP.S good2; // should branch here
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; // clear cc=0
IF !CC JUMP good3 (BP); // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF CC JUMP bad2 (BP); // branch on true (should not branch)
JUMP.S end; // we're done
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass

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//Original:/testcases/core/c_brcc_brf_bp/c_brcc_brf_bp.dsp
// Spec Reference: brcc brf bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
IF !CC JUMP good1 (BP); // branch on false (should branch)
CC = ! CC; // set cc=1
R1 = 1; // if go here, error
good1: IF !CC JUMP good2 (BP); // branch on false (should branch)
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; //
IF !CC JUMP bad2 (BP); // branch on false (should not branch)
CC = ! CC;
IF !CC JUMP good3 (BP); // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF !CC JUMP end; // branch on true (should branch)
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass

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//Original:/testcases/core/c_brcc_brf_brt_bp/c_brcc_brf_brt_bp.dsp
// Spec Reference: brcc brfbrt
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000444;
imm32 r5, 0x00000555;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
CC = R4 < R5;
IF CC JUMP good1 (BP); // branch on true (should branch)
R1 = 1; // if go here, error
good1: IF !CC JUMP bad1 (BP); // branch on false (should not branch)
CC = ! CC;
IF !CC JUMP good2; // should branch here
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; // clear cc=0
IF CC JUMP good3 (BP); // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF !CC JUMP bad2 (BP); // branch on true (should not branch)
IF CC JUMP end; // we're done
bad2: R0 = 8; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000444;
CHECKREG r5, 0x00000555;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass

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//Original:/testcases/core/c_brcc_brf_brt_nbp/c_brcc_brf_brt_nbp.dsp
// Spec Reference: brcc brf brt no bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
CC = ! CC; // set cc=1
IF CC JUMP good1; // branch on true (should branch)
R1 = 1; // if go here, error
good1: IF !CC JUMP bad1; // branch on false (should not branch)
JUMP.S good2; // should branch here
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; // clear cc=0
IF !CC JUMP good3; // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF CC JUMP bad2; // branch on true (should not branch)
JUMP.S end; // we're done
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass

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//Original:/testcases/core/c_brcc_brf_fbkwd/c_brcc_brf_fbkwd.dsp
// Spec Reference: brcc brf forward/backward
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
ASTAT = R0;
IF !CC JUMP SUBR;
R1.L = 0xeeee;
R2.L = 0x2222;
R3.L = 0x3333;
JBACK:
R4.L = 0x4444;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00001111;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00004444;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
//.code 0x448
SUBR:
R1.L = 0x1111;
IF !CC JUMP JBACK;

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//Original:/testcases/core/c_brcc_brf_nbp/c_brcc_brf_nbp.dsp
// Spec Reference: brcc brf no bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
IF !CC JUMP good1; // branch on false (should branch)
CC = ! CC; // set cc=1
R1 = 1; // if go here, error
good1: IF !CC JUMP good2; // branch on false (should branch)
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; //
IF !CC JUMP bad2; // branch on false (should not branch)
CC = ! CC;
IF !CC JUMP good3; // branch on false (should branch)
R3 = 3; // if go here, error
good3: IF !CC JUMP end; // branch on true (should branch)
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass

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//Original:/testcases/core/c_brcc_brt_bp/c_brcc_brt_bp.dsp
// Spec Reference: brcc brt bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
CC = ! CC; // set cc=1
IF CC JUMP good1 (BP); // (should branch)
R1 = 1; // if go here, error
good1: IF CC JUMP good2 (BP); // (should branch)
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; //
IF CC JUMP bad2 (BP); // (should not branch)
CC = ! CC;
IF CC JUMP good3 (BP); // (should branch)
R3 = 3; // if go here, error
good3: IF CC JUMP end (BP); // (should branch)
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass

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//Original:/testcases/core/c_brcc_brt_nbp/c_brcc_brt_nbp.dsp
// Spec Reference: brcc brt no bp
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000000;
imm32 r2, 0x00000000;
imm32 r3, 0x00000000;
imm32 r4, 0x00000000;
imm32 r5, 0x00000000;
imm32 r6, 0x00000000;
imm32 r7, 0x00000000;
begin:
ASTAT = R0; // clear cc
CC = ! CC; // set cc=1
IF CC JUMP good1; // (should branch)
R1 = 1; // if go here, error
good1: IF CC JUMP good2; // (should branch)
bad1: R2 = 2; // if go here, error
good2: CC = ! CC; //
IF CC JUMP bad2; // (should not branch)
CC = ! CC;
IF CC JUMP good3; // (should branch)
R3 = 3; // if go here, error
good3: IF CC JUMP end; // (should branch)
bad2: R4 = 4; // if go here error
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000000;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass

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//Original:/testcases/core/c_brcc_kills_dhits/c_brcc_kills_dhits.dsp
// Spec Reference: brcc kills data cache hits
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
imm32 p1, 0x00000011;
imm32 p2, 0x00000012;
.ifndef BFIN_HOST
imm32 p3, 0x00000013;
.endif
imm32 p4, 0x00000014;
loadsym P5, DATA0;
loadsym I0, DATA1;
begin:
ASTAT = R0; // clear CC
IF !CC JUMP LABEL1; // (bp);
CC = R4 < R5; // CC FLAG killed
R1 = 21;
LABEL1:
IF !CC JUMP LABEL2; // (bp);
CC = ! CC;
LABEL2:
IF !CC JUMP LABEL3; // (bp);
R2 = - R2; // ALU2op killed
LABEL3:
IF !CC JUMP LABEL4;
R3 <<= 2; // LOGI2op killed
LABEL4:
IF !CC JUMP LABEL5;
R0 = R1 + R2; // COMP3op killed
LABEL5:
IF !CC JUMP LABEL6;
R4 += 3; // COMPI2opD killed
LABEL6:
IF !CC JUMP LABEL7; // (bp);
R5 = 25; // LDIMMHALF killed
LABEL7:
IF !CC JUMP LABEL8;
R6 = CC; // CC2REG killed
LABEL8:
IF !CC JUMP LABEL9;
JUMP.S BAD1; // UJUMP killed
LABEL9:
IF !CC JUMP LABELCHK1;
BAD1:
R7 = [ P5 ]; // LDST killed
LABELCHK1:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
LABEL10:
IF !CC JUMP LABEL11;
R1 = ( A1 += R4.L * R5.H ), A0 += R4.H * R5.L;
// DSP32MAC killed
LABEL11:
IF !CC JUMP LABEL12;
R2 = R2 +|+ R3; // DSP32ALU killed
LABEL12:
IF !CC JUMP LABEL13;
R3 = LSHIFT R2 BY R3.L (V); // dsp32shift killed
LABEL13:
IF !CC JUMP LABEL14;
R4.H = R1.L << 6; // DSP32SHIFTIMM killed
LABEL14:
IF !CC JUMP LABEL15;
P2 = P1; // REGMV PREG-PREG killed
LABEL15:
IF !CC JUMP LABEL16;
R5 = P1; // REGMV Pr-to-Dr killed
LABEL16:
IF !CC JUMP LABEL17;
ASTAT = R2; // REGMV Dr-to-sys killed
LABEL17:
IF !CC JUMP LABEL18;
R6 = ASTAT; // REGMV sys-to-Dr killed
LABEL18:
IF !CC JUMP LABEL19;
[ I0 ] = R2; // DSPLDST store killed
LABEL19:
IF !CC JUMP end;
R7 = [ I0 ]; // DSPLDST load killed
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103

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//Original:/testcases/core/c_brcc_kills_dmiss/c_brcc_kills_dmiss.dsp
// Spec Reference: brcc kills data cache miss
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00000001;
imm32 r2, 0x00000002;
imm32 r3, 0x00000003;
imm32 r4, 0x00000004;
imm32 r5, 0x00000005;
imm32 r6, 0x00000006;
imm32 r7, 0x00000007;
imm32 p1, 0x00000011;
imm32 p2, 0x00000012;
.ifndef BFIN_HOST
imm32 p3, 0x00000013;
.endif
imm32 p4, 0x00000014;
loadsym P5, DATA0;
loadsym I0, DATA1;
begin:
ASTAT = R0; // clear CC
IF !CC JUMP LABEL1; // (bp);
CC = R4 < R5; // CC FLAG killed
R1 = 21;
LABEL1:
IF !CC JUMP LABEL2; // (bp);
CC = ! CC;
LABEL2:
IF !CC JUMP LABEL3; // (bp);
R2 = - R2; // ALU2op killed
LABEL3:
IF !CC JUMP LABEL4;
R3 <<= 2; // LOGI2op killed
LABEL4:
IF !CC JUMP LABEL5;
R0 = R1 + R2; // COMP3op killed
LABEL5:
IF !CC JUMP LABEL6;
R4 += 3; // COMPI2opD killed
LABEL6:
IF !CC JUMP LABEL7; // (bp);
R5 = 25; // LDIMMHALF killed
LABEL7:
IF !CC JUMP LABEL8;
R6 = CC; // CC2REG killed
LABEL8:
IF !CC JUMP LABEL9;
JUMP.S BAD1; // UJUMP killed
LABEL9:
IF !CC JUMP LABELCHK1;
BAD1:
R7 = [ P5 ]; // LDST killed
LABELCHK1:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
LABEL10:
IF !CC JUMP LABEL11;
R1 = ( A1 += R4.L * R5.H ), A0 += R4.H * R5.L;
// DSP32MAC killed
LABEL11:
IF !CC JUMP LABEL12;
R2 = R2 +|+ R3; // DSP32ALU killed
LABEL12:
IF !CC JUMP LABEL13;
R3 = LSHIFT R2 BY R3.L (V); // dsp32shift killed
LABEL13:
IF !CC JUMP LABEL14;
R4.H = R1.L << 6; // DSP32SHIFTIMM killed
LABEL14:
IF !CC JUMP LABEL15;
P2 = P1; // REGMV PREG-PREG killed
LABEL15:
IF !CC JUMP LABEL16;
R5 = P1; // REGMV Pr-to-Dr killed
LABEL16:
IF !CC JUMP LABEL17;
ASTAT = R2; // REGMV Dr-to-sys killed
LABEL17:
IF !CC JUMP LABEL18;
R6 = ASTAT; // REGMV sys-to-Dr killed
LABEL18:
IF !CC JUMP LABEL19;
[ I0 ] = R2; // DSPLDST store killed
LABEL19:
IF !CC JUMP end;
R7 = [ I0 ]; // DSPLDST load killed
end:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000002;
CHECKREG r3, 0x00000003;
CHECKREG r4, 0x00000004;
CHECKREG r5, 0x00000005;
CHECKREG r6, 0x00000006;
CHECKREG r7, 0x00000007;
pass
.data
DATA0:
.dd 0x000a0000
.dd 0x000b0001
.dd 0x000c0002
.dd 0x000d0003
.dd 0x000e0004
.data
DATA1:
.dd 0x00f00100
.dd 0x00e00101
.dd 0x00d00102
.dd 0x00c00103

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//Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr/c_cactrl_iflush_pr.dsp
// Spec Reference: c_cactrl iflush_pr
# mach: bfin
.include "testutils.inc"
start
// initial values
//p1=0x448;
//imm32 p1, CODE_ADDR_1;
loadsym p1, SUBR1;
// set all regs
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
// The result accumulated in A0 and A1, and stored to a reg half
R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L;
R3.H = A1 , A0 = R7.H * R6.L (T);
// begin of iflush
IFLUSH [ P1 ]; // p1 = 0xf00
R7 = 0;
ASTAT = R7;
IF !CC JUMP SUBR1;
JBACK:
R6 = 0;
//r4 = (a1 = l*h) M, a0 = h*l (r3,r2);
//r5 a1 = l*h, = (a0 = h*l) (r1,r0) IS;
CHECKREG r2, 0xFFD15679;
CHECKREG r3, 0xFFD00007;
CHECKREG r4, 0x00074569;
CHECKREG r5, 0x12358000;
pass
//.code 0x448
//.code CODE_ADDR_1
SUBR1:
R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L;
A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2);
IF !CC JUMP JBACK;
NOP; NOP; NOP; NOP; NOP;
// Pre-load memory with known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F

100
sim/testsuite/sim/bfin/c_cactrl_iflush_pr_pp.s Normal file
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//Original:/proj/frio/dv/testcases/core/c_cactrl_iflush_pr_pp/c_cactrl_iflush_pr_pp.dsp
// Spec Reference: c_cactrl iflush_pr [p++]
# mach: bfin
.include "testutils.inc"
start
loadsym p2, SUBR1;
// set all regs
imm32 r0, 0x13545abd;
imm32 r1, 0xadbcfec7;
imm32 r2, 0xa1245679;
imm32 r3, 0x00060007;
imm32 r4, 0xefbc4569;
imm32 r5, 0x1235000b;
imm32 r6, 0x000c000d;
imm32 r7, 0x678e000f;
// The result accumulated in A0 and A1, and stored to a reg half
R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L;
R3.H = A1 , A0 = R7.H * R6.L (T);
// begin of iflush
IFLUSH [ P2 ++ ]; // p2 = 0x448
R7 = 0;
ASTAT = R7;
IF !CC JUMP SUBR1;
JBACK:
R6 = 0;
//r4 = (a1 = l*h) M, a0 = h*l (r3,r2);
//r5 a1 = l*h, = (a0 = h*l) (r1,r0) IS;
CHECKREG r2, 0xFFD15679;
CHECKREG r3, 0xFFD00007;
CHECKREG r4, 0x00074569;
CHECKREG r5, 0x12358000;
//CHECKREG p2, 0x00000468;
pass
//.code 0x448
//.code CODE_ADDR_1
SUBR1:
R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L;
A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2);
IF !CC JUMP JBACK;
NOP; NOP; NOP; NOP; NOP;
// Pre-load memory witb known data
// More data is defined than will actually be used
.data
DATA_ADDR_1:
.dd 0x00010203
.dd 0x04050607
.dd 0x08090A0B
.dd 0x0C0D0E0F
.dd 0x10111213
.dd 0x14151617
.dd 0x18191A1B
.dd 0x1C1D1E1F
DATA_ADDR_2:
.dd 0x20212223
.dd 0x24252627
.dd 0x28292A2B
.dd 0x2C2D2E2F
.dd 0x30313233
.dd 0x34353637
.dd 0x38393A3B
.dd 0x3C3D3E3F
DATA_ADDR_3:
.dd 0x40414243
.dd 0x44454647
.dd 0x48494A4B
.dd 0x4C4D4E4F
.dd 0x50515253
.dd 0x54555657
.dd 0x58595A5B
.dd 0x5C5D5E5F
DATA_ADDR_4:
.dd 0x60616263
.dd 0x64656667
.dd 0x68696A6B
.dd 0x6C6D6E6F
.dd 0x70717273
.dd 0x74757677
.dd 0x78797A7B
.dd 0x7C7D7E7F
DATA_ADDR_5:
.dd 0x80818283
.dd 0x84858687
.dd 0x88898A8B
.dd 0x8C8D8E8F
.dd 0x90919293
.dd 0x94959697
.dd 0x98999A9B
.dd 0x9C9D9E9F

31
sim/testsuite/sim/bfin/c_calla_ljump.s Normal file
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//Original:/testcases/core/c_calla_ljump/c_calla_ljump.dsp
// Spec Reference: progctrl calla ljump
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
JUMP.L SUBR;
JBACK:
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00001111;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
SUBR: // should jump here
R1.L = 0x1111;
JUMP.L JBACK;
R2.L = 0x2222; // should not go here
JUMP.L JBACK;
RTS;

28
sim/testsuite/sim/bfin/c_calla_subr.s Normal file
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//Original:/testcases/core/c_calla_subr/c_calla_subr.dsp
// Spec Reference: progctrl calla subr
# mach: bfin
.include "testutils.inc"
start
INIT_R_REGS 0;
CALL SUBR;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00001111;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000000;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;
pass
SUBR: // should jump here
R1.L = 0x1111;
RTS;
R2.L = 0x2222; // should not go here
RTS;

56
sim/testsuite/sim/bfin/c_cc2dreg.s Normal file
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//Original:/testcases/core/c_cc2dreg/c_cc2dreg.dsp
// Spec Reference: cc2dreg
# mach: bfin
.include "testutils.inc"
start
imm32 r0, 0x00000000;
imm32 r1, 0x00120000;
imm32 r2, 0x00000003;
imm32 r3, 0x00000004;
imm32 r4, 0x00770088;
imm32 r5, 0x009900aa;
imm32 r6, 0x00bb00cc;
imm32 r7, 0x00000000;
ASTAT = R0;
CC = R1;
R1 = CC;
CC = R1;
CC = ! CC;
R2 = CC;
CC = R2;
CC = ! CC;
R3 = CC;
CC = R3;
CC = ! CC;
R4 = CC;
CC = R5;
R5 = CC;
CC = R6;
R6 = CC;
CC = ! CC;
R7 = CC;
R0 = CC;
CHECKREG r0, 0x00000000;
CHECKREG r1, 0x00000001;
CHECKREG r2, 0x00000000;
CHECKREG r3, 0x00000001;
CHECKREG r4, 0x00000000;
CHECKREG r5, 0x00000001;
CHECKREG r6, 0x00000001;
CHECKREG r7, 0x00000000;
pass

240
sim/testsuite/sim/bfin/c_cc2stat_cc_ac.S Normal file
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//Original:/testcases/core/c_cc2stat_cc_ac/c_cc2stat_cc_ac.dsp
// Spec Reference: cc2stat cc ac
# mach: bfin
#include "test.h"
.include "testutils.inc"
start
imm32 r0, _UNSET;
imm32 r1, _UNSET;
imm32 r2, _UNSET;
imm32 r3, _UNSET;
imm32 r4, _UNSET;
imm32 r5, _UNSET;
imm32 r6, _UNSET;
imm32 r7, _UNSET;
// test CC = AC 0-0, 0-1, 1-0, 1-1
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
CC = AC0; //
R0 = CC; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
CC = AC0; //
R1 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
CC = AC0; //
R2 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
CC = AC0; //
R3 = CC; //
// test cc |= AC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
CC |= AC0; //
R4 = CC; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
CC |= AC0; //
R5 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 0
CC |= AC0; //
R6 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
CC |= AC0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _SET;
CHECKREG r6, _SET;
CHECKREG r7, _SET;
// test CC &= AC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
CC &= AC0; //
R4 = CC; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
CC &= AC0; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
CC &= AC0; //
R6 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
CC &= AC0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _UNSET;
CHECKREG r6, _UNSET;
CHECKREG r7, _SET;
// test CC ^= AC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
CC ^= AC0; //
R4 = CC; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
CC ^= AC0; //
R5 = CC; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
CC ^= AC0; //
R6 = CC; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
CC ^= AC0; //
R7 = CC; //
CHECKREG r0, _UNSET;
CHECKREG r1, _SET;
CHECKREG r2, _UNSET;
CHECKREG r3, _SET;
CHECKREG r4, _UNSET;
CHECKREG r5, _SET;
CHECKREG r6, _SET;
CHECKREG r7, _UNSET;
// test AC0 = CC 0-0, 0-1, 1-0, 1-1
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
AC0 = CC; //
R0 = ASTAT; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
AC0 = CC; //
R1 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
AC0 = CC; //
R2 = ASTAT; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
AC0 = CC; //
R3 = ASTAT; //
// test AC0 |= CC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
AC0 |= CC; //
R4 = ASTAT; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
AC0 |= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
AC0 |= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
AC0 |= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_AC0|_CC);
CHECKREG r3, (_CC|_AC0);
CHECKREG r4, _UNSET;
CHECKREG r5, (_AC0);
CHECKREG r6, (_AC0|_CC);
CHECKREG r7, (_CC|_AC0);
// test AC0 &= CC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
AC0 &= CC; //
R4 = ASTAT; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
AC0 &= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
AC0 &= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
AC0 &= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AC0);
CHECKREG r3, (_CC|_AC0);
CHECKREG r4, _UNSET;
CHECKREG r5, _UNSET;
CHECKREG r6, _CC;
CHECKREG r7, (_CC|_AC0);
// test AC0 ^= CC (0-0, 0-1, 1-0, 1-1)
imm32 R7, 0x00;
ASTAT = R7; // cc = 0, AC0 = 0
AC0 ^= CC; //
R4 = ASTAT; //
imm32 R7, _AC0;
ASTAT = R7; // cc = 0, AC0 = 1
AC0 ^= CC; //
R5 = ASTAT; //
imm32 R7, _CC;
ASTAT = R7; // cc = 1, AC0 = 0
AC0 ^= CC; //
R6 = ASTAT; //
imm32 R7, (_CC|_AC0);
ASTAT = R7; // cc = 1, AC0 = 1
AC0 ^= CC; //
R7 = ASTAT; //
CHECKREG r0, _UNSET;
CHECKREG r1, _UNSET;
CHECKREG r2, (_CC|_AC0);
CHECKREG r3, (_CC|_AC0);
CHECKREG r4, _UNSET;
CHECKREG r5, (_AC0);
CHECKREG r6, (_CC|_AC0);
CHECKREG r7, _CC;
pass

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