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x86: allow 32-bit reg to be used with U{RD,WR}MSR

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... as MSR index specifier: It is unreasonable to demand that people
write less readable / understandable code, just because the present
documentation mentions only Reg64. Whether to also adjust the
disassembler is a separate question, perhaps indeed more tightly tied
to what the spec says.
This commit is contained in:
Jan Beulich 2023-12-01 08:26:36 +01:00
parent a521809d9b
commit 1f865bae65
3 changed files with 8 additions and 8 deletions
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8
gas/testsuite/gas/i386/x86-64-user_msr.s
View File

@ -5,7 +5,7 @@ _start:
urdmsr %r14, %r12
urdmsr %r14, %rax
urdmsr %rdx, %r12
urdmsr %rdx, %rax
urdmsr %edx, %rax
urdmsr $51515151, %r12
urdmsr $51515151, %rax
urdmsr $0x7f, %r12
@ -14,7 +14,7 @@ _start:
uwrmsr %r12, %r14
uwrmsr %rax, %r14
uwrmsr %r12, %rdx
uwrmsr %rax, %rdx
uwrmsr %rax, %edx
uwrmsr %r12, $51515151
uwrmsr %rax, $51515151
uwrmsr %r12, $0x7f
@ -24,7 +24,7 @@ _start:
.intel_syntax noprefix
urdmsr r12, r14
urdmsr rax, r14
urdmsr r12, rdx
urdmsr r12, edx
urdmsr rax, rdx
urdmsr r12, 51515151
urdmsr rax, 51515151
@ -33,7 +33,7 @@ _start:
urdmsr r12, 0x80000000
uwrmsr r14, r12
uwrmsr r14, rax
uwrmsr rdx, r12
uwrmsr edx, r12
uwrmsr rdx, rax
uwrmsr 51515151, r12
uwrmsr 51515151, rax

4
opcodes/i386-opc.tbl
View File

@ -3359,9 +3359,9 @@ eretu, 0xf30f01ca, FRED, NoSuf, {}
// USER_MSR instructions.
urdmsr, 0xf20f38f8, USER_MSR, RegMem|NoSuf|NoRex64, { Reg64, Reg64 }
urdmsr, 0xf20f38f8, USER_MSR, RegMem|NoSuf|NoRex64, { Reg32|Reg64, Reg64 }
urdmsr, 0xf2f8/0, USER_MSR, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 }
uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg64 }
uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg32|Reg64 }
// Immediates want to be first; md_assemble() takes care of swapping operands
// accordingly.
uwrmsr, 0xf3f8/0, USER_MSR, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 }

4
opcodes/i386-tbl.h
View File

@ -39638,7 +39638,7 @@ static const insn_template i386_optab[] =
0 },
{ { 98, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
@ -39660,7 +39660,7 @@ static const insn_template i386_optab[] =
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
0, 0, 0, 0, 0, 0 } },
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_uwrmsr, 0xf8, 2, SPACE_VEXMAP7, 0,
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,