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aarch64: Add +jscvt flag for existing fjcvtzs instruction

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This commit is contained in:
Andrew Carlotti 2024-01-12 01:42:36 +00:00 committed by Nick Clifton
parent c17c7aaf40
commit 227af30e49
4 changed files with 12 additions and 2 deletions
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1
gas/config/tc-aarch64.c
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@ -10284,6 +10284,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_FEATURES (2, F16, SIMD)}, AARCH64_FEATURES (2, F16, SIMD)},
{"compnum", AARCH64_FEATURE (COMPNUM), {"compnum", AARCH64_FEATURE (COMPNUM),
AARCH64_FEATURES (2, F16, SIMD)}, AARCH64_FEATURES (2, F16, SIMD)},
{"jscvt", AARCH64_FEATURE (JSCVT), AARCH64_FEATURE (FP)},
{"rcpc", AARCH64_FEATURE (RCPC), AARCH64_NO_FEATURES}, {"rcpc", AARCH64_FEATURE (RCPC), AARCH64_NO_FEATURES},
{"dotprod", AARCH64_FEATURE (DOTPROD), AARCH64_FEATURE (SIMD)}, {"dotprod", AARCH64_FEATURE (DOTPROD), AARCH64_FEATURE (SIMD)},
{"sha2", AARCH64_FEATURE (SHA2), AARCH64_FEATURE (FP)}, {"sha2", AARCH64_FEATURE (SHA2), AARCH64_FEATURE (FP)},

1
gas/testsuite/gas/aarch64/fp-armv8_3.d
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@ -1,5 +1,6 @@
#objdump: -dr #objdump: -dr
#as: -march=armv8.3-a #as: -march=armv8.3-a
#as: -march=armv8-a+jscvt
.*: file .* .*: file .*

5
include/opcode/aarch64.h
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@ -99,6 +99,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_RCPC, AARCH64_FEATURE_RCPC,
/* Complex # instructions. */ /* Complex # instructions. */
AARCH64_FEATURE_COMPNUM, AARCH64_FEATURE_COMPNUM,
/* JavaScript conversion instructions. */
AARCH64_FEATURE_JSCVT,
/* Dot Product instructions. */ /* Dot Product instructions. */
AARCH64_FEATURE_DOTPROD, AARCH64_FEATURE_DOTPROD,
/* SM3 & SM4 instructions. */ /* SM3 & SM4 instructions. */
@ -246,7 +248,8 @@ enum aarch64_feature_bit {
#define AARCH64_ARCH_V8_3A_FEATURES(X) (AARCH64_FEATBIT (X, V8_3A) \ #define AARCH64_ARCH_V8_3A_FEATURES(X) (AARCH64_FEATBIT (X, V8_3A) \
| AARCH64_FEATBIT (X, PAC) \ | AARCH64_FEATBIT (X, PAC) \
| AARCH64_FEATBIT (X, RCPC) \ | AARCH64_FEATBIT (X, RCPC) \
| AARCH64_FEATBIT (X, COMPNUM)) | AARCH64_FEATBIT (X, COMPNUM) \
| AARCH64_FEATBIT (X, JSCVT))
#define AARCH64_ARCH_V8_4A_FEATURES(X) (AARCH64_FEATBIT (X, V8_4A) \ #define AARCH64_ARCH_V8_4A_FEATURES(X) (AARCH64_FEATBIT (X, V8_4A) \
| AARCH64_FEATBIT (X, DOTPROD) \ | AARCH64_FEATBIT (X, DOTPROD) \
| AARCH64_FEATBIT (X, FLAGM) \ | AARCH64_FEATBIT (X, FLAGM) \

7
opcodes/aarch64-tbl.h
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@ -2518,6 +2518,8 @@ static const aarch64_feature_set aarch64_feature_pac =
AARCH64_FEATURE (PAC); AARCH64_FEATURE (PAC);
static const aarch64_feature_set aarch64_feature_compnum = static const aarch64_feature_set aarch64_feature_compnum =
AARCH64_FEATURE (COMPNUM); AARCH64_FEATURE (COMPNUM);
static const aarch64_feature_set aarch64_feature_jscvt =
AARCH64_FEATURE (JSCVT);
static const aarch64_feature_set aarch64_feature_rcpc = static const aarch64_feature_set aarch64_feature_rcpc =
AARCH64_FEATURE (RCPC); AARCH64_FEATURE (RCPC);
static const aarch64_feature_set aarch64_feature_dotprod = static const aarch64_feature_set aarch64_feature_dotprod =
@ -2631,6 +2633,7 @@ static const aarch64_feature_set aarch64_feature_d128_the =
#define FP_V8_3A &aarch64_feature_fp_v8_3a #define FP_V8_3A &aarch64_feature_fp_v8_3a
#define PAC &aarch64_feature_pac #define PAC &aarch64_feature_pac
#define COMPNUM &aarch64_feature_compnum #define COMPNUM &aarch64_feature_compnum
#define JSCVT &aarch64_feature_jscvt
#define RCPC &aarch64_feature_rcpc #define RCPC &aarch64_feature_rcpc
#define SHA2 &aarch64_feature_sha2 #define SHA2 &aarch64_feature_sha2
#define AES &aarch64_feature_aes #define AES &aarch64_feature_aes
@ -2717,6 +2720,8 @@ static const aarch64_feature_set aarch64_feature_d128_the =
{ NAME, OPCODE, MASK, CLASS, 0, PAC, OPS, QUALS, FLAGS, 0, 0, NULL } { NAME, OPCODE, MASK, CLASS, 0, PAC, OPS, QUALS, FLAGS, 0, 0, NULL }
#define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ #define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, 0, NULL } { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, 0, NULL }
#define JSCVT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, JSCVT, OPS, QUALS, FLAGS, 0, 0, NULL }
#define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ #define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, 0, NULL } { NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, 0, NULL }
#define SHA2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ #define SHA2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@ -3741,7 +3746,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
FF16_INSN ("fcvtzu",0x1ef90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF), FF16_INSN ("fcvtzu",0x1ef90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
__FP_INSN ("fmov", 0x9eae0000, 0xfffffc00, float2int, 0, OP2 (Rd, VnD1), QL_XVD1, 0), __FP_INSN ("fmov", 0x9eae0000, 0xfffffc00, float2int, 0, OP2 (Rd, VnD1), QL_XVD1, 0),
__FP_INSN ("fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, OP2 (VdD1, Rn), QL_VD1X, 0), __FP_INSN ("fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, OP2 (VdD1, Rn), QL_VD1X, 0),
{"fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, 0, FP_V8_3A, OP2 (Rd, Fn), QL_FP2INT_W_D, 0, 0, 0, NULL }, JSCVT_INSN ("fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_W_D, 0),
/* Floating-point conditional compare. */ /* Floating-point conditional compare. */
__FP_INSN ("fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE), __FP_INSN ("fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE),
FF16_INSN ("fccmp", 0x1ee00400, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE), FF16_INSN ("fccmp", 0x1ee00400, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE),