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aarch64: Add support for new SME instructions

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This patch adds support for three new SME instructions: ADDSPL,
ADDSVL and RDSVL.  They behave like ADDPL, ADDVL and RDVL, but read
the streaming vector length instead of the current vector length.

opcodes/
	* aarch64-tbl.h (aarch64_opcode_table): Add ADDSPL, ADDSVL and RDSVL.
	* aarch64-dis-2.c: Regenerate.

gas/
	* testsuite/gas/aarch64/sme.s, testsuite/gas/aarch64/sme.d: Add tests
	for ADDSPL, ADDSVL and RDSVL.
This commit is contained in:
Richard Sandiford 2022-01-06 16:22:54 +00:00
parent 41e321a897
commit 27297937e0
4 changed files with 394 additions and 302 deletions
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25
gas/testsuite/gas/aarch64/sme.d
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@ -91,3 +91,28 @@ Disassembly of section \.text:
144: a1a1f893 umops za3.s, p6/m, p7/m, z4.b, z1.b
148: a1817083 usmopa za3.s, p4/m, p3/m, z4.b, z1.b
14c: a181f893 usmops za3.s, p6/m, p7/m, z4.b, z1.b
[^:]+: 04605800 addspl x0, x0, #0
[^:]+: 04605801 addspl x1, x0, #0
[^:]+: 0460581f addspl sp, x0, #0
[^:]+: 04625800 addspl x0, x2, #0
[^:]+: 047f5800 addspl x0, sp, #0
[^:]+: 04605be0 addspl x0, x0, #31
[^:]+: 04605c00 addspl x0, x0, #-32
[^:]+: 04605c20 addspl x0, x0, #-31
[^:]+: 04605fe0 addspl x0, x0, #-1
[^:]+: 04205800 addsvl x0, x0, #0
[^:]+: 04205801 addsvl x1, x0, #0
[^:]+: 0420581f addsvl sp, x0, #0
[^:]+: 04225800 addsvl x0, x2, #0
[^:]+: 043f5800 addsvl x0, sp, #0
[^:]+: 04205be0 addsvl x0, x0, #31
[^:]+: 04205c00 addsvl x0, x0, #-32
[^:]+: 04205c20 addsvl x0, x0, #-31
[^:]+: 04205fe0 addsvl x0, x0, #-1
[^:]+: 04bf5800 rdsvl x0, #0
[^:]+: 04bf5801 rdsvl x1, #0
[^:]+: 04bf581f rdsvl xzr, #0
[^:]+: 04bf5be0 rdsvl x0, #31
[^:]+: 04bf5c00 rdsvl x0, #-32
[^:]+: 04bf5c20 rdsvl x0, #-31
[^:]+: 04bf5fe0 rdsvl x0, #-1

31
gas/testsuite/gas/aarch64/sme.s
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@ -121,3 +121,34 @@ umopa foo.s, p6/m, p7/m, z4.b, z1.b
umops foo.s, p6/m, p7/m, z4.b, z1.b
usmopa foo.s, p4/m, p3/m, z4.b, z1.b
usmops foo.s, p6/m, p7/m, z4.b, z1.b
/* ADDSPL. */
addspl x0, x0, #0
addspl x1, x0, #0
addspl sp, x0, #0
addspl x0, x2, #0
addspl x0, sp, #0
addspl x0, x0, #31
addspl x0, x0, #-32
addspl x0, x0, #-31
addspl x0, x0, #-1
/* ADDSVL. */
addsvl x0, x0, #0
addsvl x1, x0, #0
addsvl sp, x0, #0
addsvl x0, x2, #0
addsvl x0, sp, #0
addsvl x0, x0, #31
addsvl x0, x0, #-32
addsvl x0, x0, #-31
addsvl x0, x0, #-1
/* RDSVL. */
rdsvl x0, #0
rdsvl x1, #0
rdsvl xzr, #0
rdsvl x0, #31
rdsvl x0, #-32
rdsvl x0, #-31
rdsvl x0, #-1

637
opcodes/aarch64-dis-2.c
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File diff suppressed because it is too large Load Diff

3
opcodes/aarch64-tbl.h
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@ -5193,6 +5193,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
/* SME instructions. */
SME_INSN ("addha", 0xc0900000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_S, 0, 0),
SME_I64_INSN ("addha", 0xc0d00000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0),
SME_INSN ("addspl", 0x04605800, 0xffe0f800, sme_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0),
SME_INSN ("addsvl", 0x04205800, 0xffe0f800, sme_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0),
SME_INSN ("addva", 0xc0910000, 0xffff001c, sme_misc, 0, OP4 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_S, 0, 0),
SME_I64_INSN ("addva", 0xc0d10000, 0xffff0018, sme_misc, 0, OP4 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn), OP_SME_ZADA_PN_PM_ZN_D, 0, 0),
SME_INSN ("bfmopa", 0x81800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_PN_PM_ZN_ZM, 0, 0),
@ -5203,6 +5205,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME_INSN ("fmops", 0x80800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_S_S, 0, 0),
SME_F64_INSN ("fmops", 0x80c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_D_D, 0, 0),
SME_INSN ("fmops", 0x81a00010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_H_H, 0, 0),
SME_INSN ("rdsvl", 0x04bf5800, 0xfffff800, sme_misc, 0, OP2 (Rd, SVE_SIMM6), OP_SVE_XU, 0, 0),
SME_INSN ("smopa", 0xa0800000, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
SME_I64_INSN ("smopa", 0xa0c00000, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
SME_INSN ("smops", 0xa0800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),