ppc: Document the -mfuture and -Mfuture options and make them usable

The -mfuture and -Mfuture options which are used for adding potential
new ISA instructions were not documented.  They also lacked a bitmask
so new instructions could not be enabled by those options.  Fixed.

binutils/
	* doc/binutils.texi: Document -Mfuture.

gas/
	* config/tc-ppc.c: Document -mfuture
	* doc/c-ppc.texi: Likewise.

include/
	* opcode/ppc.h (PPC_OPCODE_FUTURE): Define.

opcodes/
	* ppc-dis.c (ppc_opts) <future>: Use it.
	* ppc-opc.c (FUTURE): Define.

binutils/doc/binutils.texi

@@ -2638,7 +2638,7 @@ rather than @code{li}.  All of the @option{-m} arguments for
 @option{ppc32}, @option{ppc64}, @option{ppc64bridge}, @option{ppcps},
 @option{pwr}, @option{pwr2}, @option{pwr4}, @option{pwr5}, @option{pwr5x},
 @option{pwr6}, @option{pwr7}, @option{pwr8}, @option{pwr9}, @option{pwr10},
-@option{pwrx}, @option{titan}, and @option{vle}.
+@option{pwrx}, @option{titan}, @option{vle}, and @option{future}.
 @option{32} and @option{64} modify the default or a prior CPU
 selection, disabling and enabling 64-bit insns respectively.  In
 addition, @option{altivec}, @option{any}, @option{htm}, @option{vsx},

gas/config/tc-ppc.c

@@ -1384,6 +1384,8 @@ PowerPC options:\n"));
   fprintf (stream, _("\
 -mlibresoc              generate code for Libre-SOC architecture\n"));
   fprintf (stream, _("\
+-mfuture                generate code for 'future' architecture\n"));
+  fprintf (stream, _("\
 -mcell                  generate code for Cell Broadband Engine architecture\n"));
   fprintf (stream, _("\
 -mcom                   generate code for Power/PowerPC common instructions\n"));

gas/doc/c-ppc.texi

@@ -150,6 +150,9 @@ Generate code for Power9 architecture.
 @item -mpower10, -mpwr10
 Generate code for Power10 architecture.
 
+@item -mfuture
+Generate code for 'future' architecture.
+
 @item -mcell
 @item -mcell
 Generate code for Cell Broadband Engine architecture.

include/opcode/ppc.h

@@ -240,6 +240,9 @@ extern const unsigned int spe2_num_opcodes;
 /* Opcode is only supported by SVP64 extensions (LibreSOC architecture).  */
 #define PPC_OPCODE_SVP64    0x800000000000ull
 
+/* Opcode is only supported by 'future' architecture.  */
+#define PPC_OPCODE_FUTURE  0x1000000000000ull
+
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 

opcodes/ppc-dis.c

@@ -208,7 +208,8 @@ struct ppc_mopt ppc_opts[] = {
   { "future",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
 		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 		| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_POWER9
-		| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
+		| PPC_OPCODE_POWER10 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX
+		| PPC_OPCODE_FUTURE),
     0 },
   { "ppc",     PPC_OPCODE_PPC,
     0 },

opcodes/ppc-opc.c

@@ -4847,6 +4847,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
 #define POWER8	PPC_OPCODE_POWER8
 #define POWER9	PPC_OPCODE_POWER9
 #define POWER10 PPC_OPCODE_POWER10
+#define FUTURE	PPC_OPCODE_FUTURE
 #define CELL	PPC_OPCODE_CELL
 #define PPC64	PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
 #define NON32	(PPC_OPCODE_64 | PPC_OPCODE_POWER4	\