Fix sparc opcode encoding for 4-arg crypto instructions.
include/opcode * sparc.h (F3F4): New macro. opcodes * sparc-opc.c (4-argument crypto instructions): Fix encoding using F3F4 macro. gas/testsuite * gas/sparc/crypto.d: Fix opcodes for 4-arg crypto instructions.
This commit is contained in:
David S. Miller
parent
1d5dfe78f9
commit
2c63854f55
@ -1,3 +1,7 @@
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2012-08-21 David S. Miller <davem@davemloft.net>
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* gas/sparc/crypto.d: Fix opcodes for 4-arg crypto instructions.
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2012-08-20 Edmar Wienskoski <edmar@freescale.com>
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* gas/ppc/e6500.d: Changed opcode for vabsdub, vabsduh, vabsduw,
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@ -13,27 +13,27 @@ Disassembly of section .text:
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c: 81 b0 28 60 sha512
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10: 8d b0 a8 e4 crc32c %f2, %f4, %f6
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14: 91 b1 26 06 aes_kexpand0 %f4, %f6, %f8
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18: 94 41 8f 08 aes_kexpand1 %f6, %f8, 0x7, %f10
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1c: 94 41 8d 08 aes_kexpand1 %f6, %f8, 0x6, %f10
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18: 94 c9 8f 08 aes_kexpand1 %f6, %f8, 0x7, %f10
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1c: 94 c9 8d 08 aes_kexpand1 %f6, %f8, 0x6, %f10
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20: 99 b2 26 2a aes_kexpand2 %f8, %f10, %f12
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24: a0 42 9c 0c aes_eround01 %f10, %f12, %f14, %f16
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28: a4 43 20 2e aes_eround23 %f12, %f14, %f16, %f18
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2c: a8 43 a4 50 aes_dround01 %f14, %f16, %f18, %f20
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30: ac 44 28 72 aes_dround23 %f16, %f18, %f20, %f22
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34: b0 44 ac 94 aes_eround01_l %f18, %f20, %f22, %f24
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38: b4 45 30 b6 aes_eround23_l %f20, %f22, %f24, %f26
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3c: b8 45 b4 d8 aes_dround01_l %f22, %f24, %f26, %f28
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40: bc 46 38 fa aes_dround23_l %f24, %f26, %f28, %f30
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24: a0 ca 9c 0c aes_eround01 %f10, %f12, %f14, %f16
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28: a4 cb 20 2e aes_eround23 %f12, %f14, %f16, %f18
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2c: a8 cb a4 50 aes_dround01 %f14, %f16, %f18, %f20
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30: ac cc 28 72 aes_dround23 %f16, %f18, %f20, %f22
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34: b0 cc ac 94 aes_eround01_l %f18, %f20, %f22, %f24
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38: b4 cd 30 b6 aes_eround23_l %f20, %f22, %f24, %f26
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3c: b8 cd b4 d8 aes_dround01_l %f22, %f24, %f26, %f28
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40: bc ce 38 fa aes_dround23_l %f24, %f26, %f28, %f30
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44: 87 b0 66 80 des_ip %f32, %f34
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48: 8b b0 e6 a0 des_iip %f34, %f36
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4c: 8f b1 66 c7 des_kexpand %f36, 7, %f38
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50: 9a 41 d7 29 des_round %f38, %f40, %f42, %f44
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50: 9a c9 d7 29 des_round %f38, %f40, %f42, %f44
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54: 9f b2 e7 0d kasumi_fi_fi %f42, %f44, %f46
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58: a6 43 63 4f kasumi_fl_xor %f44, %f46, %f48, %f50
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5c: aa 43 e7 71 kasumi_fi_xor %f46, %f48, %f50, %f52
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58: a6 cb 63 4f kasumi_fl_xor %f44, %f46, %f48, %f50
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5c: aa cb e7 71 kasumi_fi_xor %f46, %f48, %f50, %f52
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60: af b4 e7 95 camellia_fi %f50, %f52, %f54
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64: b3 b5 67 b7 camellia_fli %f52, %f54, %f56
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68: ba 45 f7 99 camellia_f %f54, %f56, %f58, %f60
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68: ba cd f7 99 camellia_f %f54, %f56, %f58, %f60
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6c: 81 b0 29 00 mpmul 0
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70: 81 b0 29 01 mpmul 1
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74: 81 b0 29 02 mpmul 2
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@ -1,3 +1,7 @@
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2012-08-21 David S. Miller <davem@davemloft.net>
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* sparc.h (F3F4): New macro.
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2012-08-13 Ian Bolton <ian.bolton@arm.com>
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Laurent Desnogues <laurent.desnogues@arm.com>
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Jim MacArthur <jim.macarthur@arm.com>
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@ -234,6 +234,7 @@ typedef struct sparc_opcode
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#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
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#define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */
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#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
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#define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z))
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#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
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#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
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#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
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@ -1,3 +1,8 @@
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2012-08-21 David S. Miller <davem@davemloft.net>
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* sparc-opc.c (4-argument crypto instructions): Fix encoding using
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F3F4 macro.
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2012-08-20 Edmar Wienskoski <edmar@freescale.com>
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* ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
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@ -1960,19 +1960,19 @@ SLCBCC("cbnefr", 15),
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{ "mpmul", F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT, HWCAP_MPMUL, v9b },
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{ "montmul", F3F(2, 0x36, 0x149), F3F(~2, ~0x36, ~0x149), "X", F_FLOAT, HWCAP_MONT, v9b },
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{ "montsqr", F3F(2, 0x36, 0x14a), F3F(~2, ~0x36, ~0x14a), "X", F_FLOAT, HWCAP_MONT, v9b },
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{"aes_eround01", F2(2, 0x19)|OPF_LOW4(0), F2(~2, ~0x19)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_eround23", F2(2, 0x19)|OPF_LOW4(1), F2(~2, ~0x19)|OPF_LOW4(~1), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_dround01", F2(2, 0x19)|OPF_LOW4(2), F2(~2, ~0x19)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_dround23", F2(2, 0x19)|OPF_LOW4(3), F2(~2, ~0x19)|OPF_LOW4(~3), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_eround01_l",F2(2, 0x19)|OPF_LOW4(4), F2(~2, ~0x19)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_eround23_l",F2(2, 0x19)|OPF_LOW4(5), F2(~2, ~0x19)|OPF_LOW4(~5), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_dround01_l",F2(2, 0x19)|OPF_LOW4(6), F2(~2, ~0x19)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_dround23_l",F2(2, 0x19)|OPF_LOW4(7), F2(~2, ~0x19)|OPF_LOW4(~7), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_kexpand1", F2(2, 0x19)|OPF_LOW4(8), F2(~2, ~0x19)|OPF_LOW4(~8), "v,B,),H", F_FLOAT, HWCAP_AES, v9b },
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{"des_round", F2(2, 0x19)|OPF_LOW4(9), F2(~2, ~0x19)|OPF_LOW4(~9), "v,B,5,H", F_FLOAT, HWCAP_DES, v9b },
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{"kasumi_fl_xor", F2(2, 0x19)|OPF_LOW4(10), F2(~2, ~0x19)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
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{"kasumi_fi_xor", F2(2, 0x19)|OPF_LOW4(11), F2(~2, ~0x19)|OPF_LOW4(~11), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
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{"camellia_f", F2(2, 0x19)|OPF_LOW4(12), F2(~2, ~0x19)|OPF_LOW4(~12), "v,B,5,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
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{"aes_eround01", F3F4(2, 0x19, 0), F3F4(~2, ~0x19, ~0), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_eround23", F3F4(2, 0x19, 1), F3F4(~2, ~0x19, ~1), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_dround01", F3F4(2, 0x19, 2), F3F4(~2, ~0x19, ~2), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_dround23", F3F4(2, 0x19, 3), F3F4(~2, ~0x19, ~3), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_eround01_l",F3F4(2, 0x19, 4), F3F4(~2, ~0x19, ~4), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_eround23_l",F3F4(2, 0x19, 5), F3F4(~2, ~0x19, ~5), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_dround01_l",F3F4(2, 0x19, 6), F3F4(~2, ~0x19, ~6), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_dround23_l",F3F4(2, 0x19, 7), F3F4(~2, ~0x19, ~7), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
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{"aes_kexpand1", F3F4(2, 0x19, 8), F3F4(~2, ~0x19, ~8), "v,B,),H", F_FLOAT, HWCAP_AES, v9b },
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{"des_round", F3F4(2, 0x19, 9), F3F4(~2, ~0x19, ~9), "v,B,5,H", F_FLOAT, HWCAP_DES, v9b },
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{"kasumi_fl_xor", F3F4(2, 0x19, 10), F3F4(~2, ~0x19, ~10), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
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{"kasumi_fi_xor", F3F4(2, 0x19, 11), F3F4(~2, ~0x19, ~11), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
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{"camellia_f", F3F4(2, 0x19, 12), F3F4(~2, ~0x19, ~12), "v,B,5,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
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{ "flcmps", CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT, HWCAP_HPC, v9b },
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{ "flcmps", CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT, HWCAP_HPC, v9b },
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{ "flcmps", CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT, HWCAP_HPC, v9b },
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