Support APX NDD
opcodes/ChangeLog: * opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF. * opcodes/i386-dis-evex.h: Add NDD insn. * opcodes/i386-dis.c (nd): New define. (VexGb): Ditto. (VexGv): Ditto. (get_valid_dis386): Change for NDD decode. (print_insn): Ditto. (putop): Ditto. (intel_operand_size): Ditto. (OP_E_memory): Ditto. (OP_VEX): Ditto. * opcodes/i386-opc.h (VexVVVV_DST): New. * opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV. * opcodes/i386-tbl.h: Regenerated. gas/ChangeLog: * gas/config/tc-i386.c (operand_size_match): Support APX NDD that the number of operands is 3. (build_apx_evex_prefix): Change for ndd encode. (process_operands): Ditto. (build_modrm_byte): Ditto. (match_template): Support swap the first two operands for APX NDD. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd. * testsuite/gas/i386/x86-64-apx-ndd.d: New test. * testsuite/gas/i386/x86-64-apx-ndd.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
This commit is contained in:
konglin1
Cui, Lili
parent
ce9cddf5dd
commit
3083f37643
@ -2240,8 +2240,10 @@ operand_size_match (const insn_template *t)
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unsigned int given = i.operands - j - 1;
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/* For FMA4 and XOP insns VEX.W controls just the first two
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register operands. */
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if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP))
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register operands. And APX_F insns just swap the two source operands,
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with the 3rd one being the destination. */
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if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP)
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|| is_cpu (t, CpuAPX_F))
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given = j < 2 ? 1 - j : j;
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if (t->operand_types[j].bitfield.class == Reg
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@ -4200,6 +4202,11 @@ build_apx_evex_prefix (void)
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if (i.vex.register_specifier
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&& i.vex.register_specifier->reg_flags & RegRex2)
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i.vex.bytes[3] &= ~0x08;
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/* Encode the NDD bit of the instruction promoted from the legacy
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space. */
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if (i.vex.register_specifier && i.tm.opcode_space == SPACE_EVEXMAP4)
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i.vex.bytes[3] |= 0x10;
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}
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static void establish_rex (void)
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@ -7473,18 +7480,22 @@ match_template (char mnem_suffix)
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- the store form is requested, and the template is a load form,
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- the non-default (swapped) form is requested. */
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overlap1 = operand_type_and (operand_types[0], operand_types[1]);
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j = i.operands - 1 - (t->opcode_space == SPACE_EVEXMAP4
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&& t->opcode_modifier.vexvvvv);
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if (t->opcode_modifier.d && i.reg_operands == i.operands
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&& !operand_type_all_zero (&overlap1))
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switch (i.dir_encoding)
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{
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case dir_encoding_load:
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if (operand_type_check (operand_types[i.operands - 1], anymem)
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if (operand_type_check (operand_types[j], anymem)
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|| t->opcode_modifier.regmem)
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goto check_reverse;
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break;
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case dir_encoding_store:
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if (!operand_type_check (operand_types[i.operands - 1], anymem)
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if (!operand_type_check (operand_types[j], anymem)
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&& !t->opcode_modifier.regmem)
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goto check_reverse;
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break;
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@ -7495,6 +7506,7 @@ match_template (char mnem_suffix)
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case dir_encoding_default:
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break;
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}
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/* If we want store form, we skip the current load. */
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if ((i.dir_encoding == dir_encoding_store
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|| i.dir_encoding == dir_encoding_swap)
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@ -7524,11 +7536,13 @@ match_template (char mnem_suffix)
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continue;
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/* Try reversing direction of operands. */
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j = is_cpu (t, CpuFMA4)
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|| is_cpu (t, CpuXOP) ? 1 : i.operands - 1;
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|| is_cpu (t, CpuXOP)
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|| is_cpu (t, CpuAPX_F) ? 1 : i.operands - 1;
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overlap0 = operand_type_and (i.types[0], operand_types[j]);
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overlap1 = operand_type_and (i.types[j], operand_types[0]);
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overlap2 = operand_type_and (i.types[1], operand_types[1]);
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gas_assert (t->operands != 3 || !check_register);
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gas_assert (t->operands != 3 || !check_register
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|| is_cpu (t, CpuAPX_F));
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if (!operand_type_match (overlap0, i.types[0])
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|| !operand_type_match (overlap1, i.types[j])
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|| (t->operands == 3
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@ -7563,6 +7577,11 @@ match_template (char mnem_suffix)
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found_reverse_match = Opcode_VexW;
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goto check_operands_345;
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}
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else if (is_cpu (t, CpuAPX_F) && i.operands == 3)
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{
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found_reverse_match = Opcode_D;
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goto check_operands_345;
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}
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else if (t->opcode_space != SPACE_BASE
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&& (t->opcode_space != SPACE_0F
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/* MOV to/from CR/DR/TR, as an exception, follow
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@ -7744,6 +7763,9 @@ match_template (char mnem_suffix)
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i.tm.base_opcode ^= found_reverse_match;
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if (i.tm.opcode_space == SPACE_EVEXMAP4)
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goto swap_first_2;
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/* Certain SIMD insns have their load forms specified in the opcode
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table, and hence we need to _set_ RegMem instead of clearing it.
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We need to avoid setting the bit though on insns like KMOVW. */
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@ -7763,6 +7785,7 @@ match_template (char mnem_suffix)
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flipping VEX.W. */
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i.tm.opcode_modifier.vexw ^= VEXW0 ^ VEXW1;
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swap_first_2:
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j = i.tm.operand_types[0].bitfield.imm8;
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i.tm.operand_types[j] = operand_types[j + 1];
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i.tm.operand_types[j + 1] = operand_types[j];
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@ -8584,12 +8607,9 @@ process_operands (void)
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unnecessary segment overrides. */
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const reg_entry *default_seg = NULL;
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/* We only need to check those implicit registers for instructions
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with 3 operands or less. */
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if (i.operands <= 3)
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for (unsigned int j = 0; j < i.operands; j++)
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if (i.types[j].bitfield.instance != InstanceNone)
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i.reg_operands--;
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for (unsigned int j = 0; j < i.operands; j++)
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if (i.types[j].bitfield.instance != InstanceNone)
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i.reg_operands--;
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if (i.tm.opcode_modifier.sse2avx)
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{
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@ -8943,11 +8963,19 @@ build_modrm_byte (void)
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|| i.vec_encoding == vex_encoding_evex));
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}
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for (v = source + 1; v < dest; ++v)
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if (v != reg_slot)
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break;
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if (v >= dest)
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v = ~0;
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if (i.tm.opcode_modifier.vexvvvv == VexVVVV_DST)
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{
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v = dest;
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dest-- ;
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}
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else
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{
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for (v = source + 1; v < dest; ++v)
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if (v != reg_slot)
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break;
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if (v >= dest)
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v = ~0;
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}
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if (i.tm.extension_opcode != None)
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{
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if (dest != source)
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@ -31,3 +31,6 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+:[ ]+0c 18[ ]+or.*
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[ ]*[a-f0-9]+:[ ]+62 f2 fc 18 f5[ ]+\(bad\)
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[ ]*[a-f0-9]+:[ ]+0c 18[ ]+or.*
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[ ]*[a-f0-9]+:[ ]+62 f4 e4[ ]+\(bad\)
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[ ]*[a-f0-9]+:[ ]+08 ff[ ]+.*
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[ ]*[a-f0-9]+:[ ]+04 08[ ]+.*
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@ -37,3 +37,6 @@ _start:
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#EVEX from VEX bzhi %rax,(%rax,%rbx),%rcx EVEX.P[20](EVEX.b) == 0b1
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.insn EVEX.L0.NP.0f38.W1 0xf5, %rax, (%rax,%rbx){1to8}, %rcx
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#{evex} inc %rax %rbx EVEX.vvvv != 1111 && EVEX.ND = 0.
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.insn EVEX.L0.NP.M4.W1 0xff/0, (%rax,%rcx), %rbx
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160
gas/testsuite/gas/i386/x86-64-apx-ndd.d
Normal file
160
gas/testsuite/gas/i386/x86-64-apx-ndd.d
Normal file
@ -0,0 +1,160 @@
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#as:
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#objdump: -dw
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#name: x86-64 APX NDD instructions with evex prefix encoding
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#source: x86-64-apx-ndd.s
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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\s*[a-f0-9]+:\s*62 f4 0d 10 81 d0 34 12 adc \$0x1234,%ax,%r30w
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\s*[a-f0-9]+:\s*62 7c 6c 10 10 f9 adc %r15b,%r17b,%r18b
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\s*[a-f0-9]+:\s*62 54 6c 10 11 38 adc %r15d,\(%r8\),%r18d
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\s*[a-f0-9]+:\s*62 c4 3c 18 12 04 07 adc \(%r15,%rax,1\),%r16b,%r8b
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\s*[a-f0-9]+:\s*62 c4 3d 18 13 04 07 adc \(%r15,%rax,1\),%r16w,%r8w
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\s*[a-f0-9]+:\s*62 fc 5c 10 83 14 83 11 adcl \$0x11,\(%r19,%rax,4\),%r20d
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\s*[a-f0-9]+:\s*62 54 6d 10 66 c7 adcx %r15d,%r8d,%r18d
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\s*[a-f0-9]+:\s*62 14 f9 08 66 04 3f adcx \(%r15,%r31,1\),%r8
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\s*[a-f0-9]+:\s*62 14 69 10 66 04 3f adcx \(%r15,%r31,1\),%r8d,%r18d
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\s*[a-f0-9]+:\s*62 f4 0d 10 81 c0 34 12 add \$0x1234,%ax,%r30w
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\s*[a-f0-9]+:\s*62 d4 fc 10 81 c7 33 44 34 12 add \$0x12344433,%r15,%r16
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\s*[a-f0-9]+:\s*62 d4 74 10 80 c5 34 add \$0x34,%r13b,%r17b
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\s*[a-f0-9]+:\s*62 f4 bc 18 81 c0 11 22 33 f4 add \$0xfffffffff4332211,%rax,%r8
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\s*[a-f0-9]+:\s*62 44 fc 10 01 f8 add %r31,%r8,%r16
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\s*[a-f0-9]+:\s*62 44 fc 10 01 38 add %r31,\(%r8\),%r16
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\s*[a-f0-9]+:\s*62 44 f8 10 01 3c c0 add %r31,\(%r8,%r16,8\),%r16
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\s*[a-f0-9]+:\s*62 44 7c 10 00 f8 add %r31b,%r8b,%r16b
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\s*[a-f0-9]+:\s*62 44 7c 10 01 f8 add %r31d,%r8d,%r16d
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\s*[a-f0-9]+:\s*62 44 7d 10 01 f8 add %r31w,%r8w,%r16w
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\s*[a-f0-9]+:\s*62 5c fc 10 03 07 add \(%r31\),%r8,%r16
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\s*[a-f0-9]+:\s*62 5c f8 10 03 84 07 90 90 00 00 add 0x9090\(%r31,%r16,1\),%r8,%r16
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\s*[a-f0-9]+:\s*62 44 7c 10 00 f8 add %r31b,%r8b,%r16b
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\s*[a-f0-9]+:\s*62 44 7c 10 01 f8 add %r31d,%r8d,%r16d
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\s*[a-f0-9]+:\s*62 fc 5c 10 83 04 83 11 addl \$0x11,\(%r19,%rax,4\),%r20d
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\s*[a-f0-9]+:\s*62 44 fc 10 01 f8 add %r31,%r8,%r16
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\s*[a-f0-9]+:\s*62 d4 fc 10 81 04 8f 33 44 34 12 addq \$0x12344433,\(%r15,%rcx,4\),%r16
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\s*[a-f0-9]+:\s*62 44 7d 10 01 f8 add %r31w,%r8w,%r16w
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\s*[a-f0-9]+:\s*62 54 6e 10 66 c7 adox %r15d,%r8d,%r18d
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\s*[a-f0-9]+:\s*62 5c fc 10 03 c7 add %r31,%r8,%r16
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\s*[a-f0-9]+:\s*62 44 fc 10 01 f8 add %r31,%r8,%r16
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\s*[a-f0-9]+:\s*62 14 fa 08 66 04 3f adox \(%r15,%r31,1\),%r8
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\s*[a-f0-9]+:\s*62 14 6a 10 66 04 3f adox \(%r15,%r31,1\),%r8d,%r18d
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\s*[a-f0-9]+:\s*62 f4 0d 10 81 e0 34 12 and \$0x1234,%ax,%r30w
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\s*[a-f0-9]+:\s*62 7c 6c 10 20 f9 and %r15b,%r17b,%r18b
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\s*[a-f0-9]+:\s*62 54 6c 10 21 38 and %r15d,\(%r8\),%r18d
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\s*[a-f0-9]+:\s*62 c4 3c 18 22 04 07 and \(%r15,%rax,1\),%r16b,%r8b
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\s*[a-f0-9]+:\s*62 c4 3d 18 23 04 07 and \(%r15,%rax,1\),%r16w,%r8w
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\s*[a-f0-9]+:\s*62 fc 5c 10 83 24 83 11 andl \$0x11,\(%r19,%rax,4\),%r20d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 47 90 90 90 90 90 cmova -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 43 90 90 90 90 90 cmovae -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 42 90 90 90 90 90 cmovb -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 46 90 90 90 90 90 cmovbe -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 44 90 90 90 90 90 cmove -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 4f 90 90 90 90 90 cmovg -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 4d 90 90 90 90 90 cmovge -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 4c 90 90 90 90 90 cmovl -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 4e 90 90 90 90 90 cmovle -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 45 90 90 90 90 90 cmovne -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 41 90 90 90 90 90 cmovno -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 49 90 90 90 90 90 cmovns -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 40 90 90 90 90 90 cmovo -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 48 90 90 90 90 90 cmovs -0x6f6f6f70\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*62 f4 f4 10 ff c8 dec %rax,%r17
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\s*[a-f0-9]+:\s*62 9c 3c 18 fe 0c 27 decb \(%r31,%r12,1\),%r8b
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\s*[a-f0-9]+:\s*62 b4 b0 10 af 94 f8 09 09 00 00 imul 0x909\(%rax,%r31,8\),%rdx,%r25
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\s*[a-f0-9]+:\s*67 62 f4 3c 18 af 90 09 09 09 00 imul 0x90909\(%eax\),%edx,%r8d
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\s*[a-f0-9]+:\s*62 dc fc 10 ff c7 inc %r31,%r16
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\s*[a-f0-9]+:\s*62 dc bc 18 ff c7 inc %r31,%r8
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\s*[a-f0-9]+:\s*62 f4 e4 18 ff c0 inc %rax,%rbx
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\s*[a-f0-9]+:\s*62 f4 f4 10 f7 d8 neg %rax,%r17
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\s*[a-f0-9]+:\s*62 9c 3c 18 f6 1c 27 negb \(%r31,%r12,1\),%r8b
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\s*[a-f0-9]+:\s*62 f4 f4 10 f7 d0 not %rax,%r17
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\s*[a-f0-9]+:\s*62 9c 3c 18 f6 14 27 notb \(%r31,%r12,1\),%r8b
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\s*[a-f0-9]+:\s*62 f4 0d 10 81 c8 34 12 or \$0x1234,%ax,%r30w
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\s*[a-f0-9]+:\s*62 7c 6c 10 08 f9 or %r15b,%r17b,%r18b
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\s*[a-f0-9]+:\s*62 54 6c 10 09 38 or %r15d,\(%r8\),%r18d
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\s*[a-f0-9]+:\s*62 c4 3c 18 0a 04 07 or \(%r15,%rax,1\),%r16b,%r8b
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\s*[a-f0-9]+:\s*62 c4 3d 18 0b 04 07 or \(%r15,%rax,1\),%r16w,%r8w
|
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\s*[a-f0-9]+:\s*62 fc 5c 10 83 0c 83 11 orl \$0x11,\(%r19,%rax,4\),%r20d
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\s*[a-f0-9]+:\s*62 d4 04 10 c0 d4 02 rcl \$0x2,%r12b,%r31b
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\s*[a-f0-9]+:\s*62 fc 3c 18 d2 d0 rcl %cl,%r16b,%r8b
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\s*[a-f0-9]+:\s*62 f4 04 10 d0 10 rclb \$1,\(%rax\),%r31b
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\s*[a-f0-9]+:\s*62 f4 04 10 c1 10 02 rcll \$0x2,\(%rax\),%r31d
|
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\s*[a-f0-9]+:\s*62 f4 05 10 d1 10 rclw \$1,\(%rax\),%r31w
|
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\s*[a-f0-9]+:\s*62 fc 05 10 d3 14 83 rclw %cl,\(%r19,%rax,4\),%r31w
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\s*[a-f0-9]+:\s*62 d4 04 10 c0 dc 02 rcr \$0x2,%r12b,%r31b
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\s*[a-f0-9]+:\s*62 fc 3c 18 d2 d8 rcr %cl,%r16b,%r8b
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\s*[a-f0-9]+:\s*62 f4 04 10 d0 18 rcrb \$1,\(%rax\),%r31b
|
||||
\s*[a-f0-9]+:\s*62 f4 04 10 c1 18 02 rcrl \$0x2,\(%rax\),%r31d
|
||||
\s*[a-f0-9]+:\s*62 f4 05 10 d1 18 rcrw \$1,\(%rax\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 fc 05 10 d3 1c 83 rcrw %cl,\(%r19,%rax,4\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 d4 04 10 c0 c4 02 rol \$0x2,%r12b,%r31b
|
||||
\s*[a-f0-9]+:\s*62 fc 3c 18 d2 c0 rol %cl,%r16b,%r8b
|
||||
\s*[a-f0-9]+:\s*62 f4 04 10 d0 00 rolb \$1,\(%rax\),%r31b
|
||||
\s*[a-f0-9]+:\s*62 f4 04 10 c1 00 02 roll \$0x2,\(%rax\),%r31d
|
||||
\s*[a-f0-9]+:\s*62 f4 05 10 d1 00 rolw \$1,\(%rax\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 fc 05 10 d3 04 83 rolw %cl,\(%r19,%rax,4\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 d4 04 10 c0 cc 02 ror \$0x2,%r12b,%r31b
|
||||
\s*[a-f0-9]+:\s*62 fc 3c 18 d2 c8 ror %cl,%r16b,%r8b
|
||||
\s*[a-f0-9]+:\s*62 f4 04 10 d0 08 rorb \$1,\(%rax\),%r31b
|
||||
\s*[a-f0-9]+:\s*62 f4 04 10 c1 08 02 rorl \$0x2,\(%rax\),%r31d
|
||||
\s*[a-f0-9]+:\s*62 f4 05 10 d1 08 rorw \$1,\(%rax\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 fc 05 10 d3 0c 83 rorw %cl,\(%r19,%rax,4\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 d4 04 10 c0 fc 02 sar \$0x2,%r12b,%r31b
|
||||
\s*[a-f0-9]+:\s*62 fc 3c 18 d2 f8 sar %cl,%r16b,%r8b
|
||||
\s*[a-f0-9]+:\s*62 f4 04 10 d0 38 sarb \$1,\(%rax\),%r31b
|
||||
\s*[a-f0-9]+:\s*62 f4 04 10 c1 38 02 sarl \$0x2,\(%rax\),%r31d
|
||||
\s*[a-f0-9]+:\s*62 f4 05 10 d1 38 sarw \$1,\(%rax\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 fc 05 10 d3 3c 83 sarw %cl,\(%r19,%rax,4\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 f4 0d 10 81 d8 34 12 sbb \$0x1234,%ax,%r30w
|
||||
\s*[a-f0-9]+:\s*62 7c 6c 10 18 f9 sbb %r15b,%r17b,%r18b
|
||||
\s*[a-f0-9]+:\s*62 54 6c 10 19 38 sbb %r15d,\(%r8\),%r18d
|
||||
\s*[a-f0-9]+:\s*62 c4 3c 18 1a 04 07 sbb \(%r15,%rax,1\),%r16b,%r8b
|
||||
\s*[a-f0-9]+:\s*62 c4 3d 18 1b 04 07 sbb \(%r15,%rax,1\),%r16w,%r8w
|
||||
\s*[a-f0-9]+:\s*62 fc 5c 10 83 1c 83 11 sbbl \$0x11,\(%r19,%rax,4\),%r20d
|
||||
\s*[a-f0-9]+:\s*62 d4 04 10 c0 e4 02 shl \$0x2,%r12b,%r31b
|
||||
\s*[a-f0-9]+:\s*62 d4 04 10 c0 e4 02 shl \$0x2,%r12b,%r31b
|
||||
\s*[a-f0-9]+:\s*62 fc 3c 18 d2 e0 shl %cl,%r16b,%r8b
|
||||
\s*[a-f0-9]+:\s*62 fc 3c 18 d2 e0 shl %cl,%r16b,%r8b
|
||||
\s*[a-f0-9]+:\s*62 f4 04 10 d0 20 shlb \$1,\(%rax\),%r31b
|
||||
\s*[a-f0-9]+:\s*62 f4 04 10 d0 20 shlb \$1,\(%rax\),%r31b
|
||||
\s*[a-f0-9]+:\s*62 74 84 10 24 20 01 shld \$0x1,%r12,\(%rax\),%r31
|
||||
\s*[a-f0-9]+:\s*62 74 04 10 24 38 02 shld \$0x2,%r15d,\(%rax\),%r31d
|
||||
\s*[a-f0-9]+:\s*62 54 05 10 24 c4 02 shld \$0x2,%r8w,%r12w,%r31w
|
||||
\s*[a-f0-9]+:\s*62 7c bc 18 a5 e0 shld %cl,%r12,%r16,%r8
|
||||
\s*[a-f0-9]+:\s*62 7c 05 10 a5 2c 83 shld %cl,%r13w,\(%r19,%rax,4\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 74 05 10 a5 08 shld %cl,%r9w,\(%rax\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 f4 04 10 c1 20 02 shll \$0x2,\(%rax\),%r31d
|
||||
\s*[a-f0-9]+:\s*62 f4 04 10 c1 20 02 shll \$0x2,\(%rax\),%r31d
|
||||
\s*[a-f0-9]+:\s*62 f4 05 10 d1 20 shlw \$1,\(%rax\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 f4 05 10 d1 20 shlw \$1,\(%rax\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 fc 05 10 d3 24 83 shlw %cl,\(%r19,%rax,4\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 fc 05 10 d3 24 83 shlw %cl,\(%r19,%rax,4\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 d4 04 10 c0 ec 02 shr \$0x2,%r12b,%r31b
|
||||
\s*[a-f0-9]+:\s*62 fc 3c 18 d2 e8 shr %cl,%r16b,%r8b
|
||||
\s*[a-f0-9]+:\s*62 f4 04 10 d0 28 shrb \$1,\(%rax\),%r31b
|
||||
\s*[a-f0-9]+:\s*62 74 84 10 2c 20 01 shrd \$0x1,%r12,\(%rax\),%r31
|
||||
\s*[a-f0-9]+:\s*62 74 04 10 2c 38 02 shrd \$0x2,%r15d,\(%rax\),%r31d
|
||||
\s*[a-f0-9]+:\s*62 54 05 10 2c c4 02 shrd \$0x2,%r8w,%r12w,%r31w
|
||||
\s*[a-f0-9]+:\s*62 7c bc 18 ad e0 shrd %cl,%r12,%r16,%r8
|
||||
\s*[a-f0-9]+:\s*62 7c 05 10 ad 2c 83 shrd %cl,%r13w,\(%r19,%rax,4\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 74 05 10 ad 08 shrd %cl,%r9w,\(%rax\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 f4 04 10 c1 28 02 shrl \$0x2,\(%rax\),%r31d
|
||||
\s*[a-f0-9]+:\s*62 f4 05 10 d1 28 shrw \$1,\(%rax\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 fc 05 10 d3 2c 83 shrw %cl,\(%r19,%rax,4\),%r31w
|
||||
\s*[a-f0-9]+:\s*62 f4 0d 10 81 e8 34 12 sub \$0x1234,%ax,%r30w
|
||||
\s*[a-f0-9]+:\s*62 7c 6c 10 28 f9 sub %r15b,%r17b,%r18b
|
||||
\s*[a-f0-9]+:\s*62 54 6c 10 29 38 sub %r15d,\(%r8\),%r18d
|
||||
\s*[a-f0-9]+:\s*62 c4 3c 18 2a 04 07 sub \(%r15,%rax,1\),%r16b,%r8b
|
||||
\s*[a-f0-9]+:\s*62 c4 3d 18 2b 04 07 sub \(%r15,%rax,1\),%r16w,%r8w
|
||||
\s*[a-f0-9]+:\s*62 fc 5c 10 83 2c 83 11 subl \$0x11,\(%r19,%rax,4\),%r20d
|
||||
\s*[a-f0-9]+:\s*62 f4 0d 10 81 f0 34 12 xor \$0x1234,%ax,%r30w
|
||||
\s*[a-f0-9]+:\s*62 7c 6c 10 30 f9 xor %r15b,%r17b,%r18b
|
||||
\s*[a-f0-9]+:\s*62 54 6c 10 31 38 xor %r15d,\(%r8\),%r18d
|
||||
\s*[a-f0-9]+:\s*62 c4 3c 18 32 04 07 xor \(%r15,%rax,1\),%r16b,%r8b
|
||||
\s*[a-f0-9]+:\s*62 c4 3d 18 33 04 07 xor \(%r15,%rax,1\),%r16w,%r8w
|
||||
\s*[a-f0-9]+:\s*62 fc 5c 10 83 34 83 11 xorl \$0x11,\(%r19,%rax,4\),%r20d
|
||||
155
gas/testsuite/gas/i386/x86-64-apx-ndd.s
Normal file
155
gas/testsuite/gas/i386/x86-64-apx-ndd.s
Normal file
@ -0,0 +1,155 @@
|
||||
# Check 64bit APX NDD instructions with evex prefix encoding
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
adc $0x1234,%ax,%r30w
|
||||
adc %r15b,%r17b,%r18b
|
||||
adc %r15d,(%r8),%r18d
|
||||
adc (%r15,%rax,1),%r16b,%r8b
|
||||
adc (%r15,%rax,1),%r16w,%r8w
|
||||
adcl $0x11,(%r19,%rax,4),%r20d
|
||||
adcx %r15d,%r8d,%r18d
|
||||
adcx (%r15,%r31,1),%r8
|
||||
adcx (%r15,%r31,1),%r8d,%r18d
|
||||
add $0x1234,%ax,%r30w
|
||||
add $0x12344433,%r15,%r16
|
||||
add $0x34,%r13b,%r17b
|
||||
add $0xfffffffff4332211,%rax,%r8
|
||||
add %r31,%r8,%r16
|
||||
add %r31,(%r8),%r16
|
||||
add %r31,(%r8,%r16,8),%r16
|
||||
add %r31b,%r8b,%r16b
|
||||
add %r31d,%r8d,%r16d
|
||||
add %r31w,%r8w,%r16w
|
||||
add (%r31),%r8,%r16
|
||||
add 0x9090(%r31,%r16,1),%r8,%r16
|
||||
addb %r31b,%r8b,%r16b
|
||||
addl %r31d,%r8d,%r16d
|
||||
addl $0x11,(%r19,%rax,4),%r20d
|
||||
addq %r31,%r8,%r16
|
||||
addq $0x12344433,(%r15,%rcx,4),%r16
|
||||
addw %r31w,%r8w,%r16w
|
||||
adox %r15d,%r8d,%r18d
|
||||
{load} add %r31,%r8,%r16
|
||||
{store} add %r31,%r8,%r16
|
||||
adox (%r15,%r31,1),%r8
|
||||
adox (%r15,%r31,1),%r8d,%r18d
|
||||
and $0x1234,%ax,%r30w
|
||||
and %r15b,%r17b,%r18b
|
||||
and %r15d,(%r8),%r18d
|
||||
and (%r15,%rax,1),%r16b,%r8b
|
||||
and (%r15,%rax,1),%r16w,%r8w
|
||||
andl $0x11,(%r19,%rax,4),%r20d
|
||||
cmova 0x90909090(%eax),%edx,%r8d
|
||||
cmovae 0x90909090(%eax),%edx,%r8d
|
||||
cmovb 0x90909090(%eax),%edx,%r8d
|
||||
cmovbe 0x90909090(%eax),%edx,%r8d
|
||||
cmove 0x90909090(%eax),%edx,%r8d
|
||||
cmovg 0x90909090(%eax),%edx,%r8d
|
||||
cmovge 0x90909090(%eax),%edx,%r8d
|
||||
cmovl 0x90909090(%eax),%edx,%r8d
|
||||
cmovle 0x90909090(%eax),%edx,%r8d
|
||||
cmovne 0x90909090(%eax),%edx,%r8d
|
||||
cmovno 0x90909090(%eax),%edx,%r8d
|
||||
cmovnp 0x90909090(%eax),%edx,%r8d
|
||||
cmovns 0x90909090(%eax),%edx,%r8d
|
||||
cmovo 0x90909090(%eax),%edx,%r8d
|
||||
cmovp 0x90909090(%eax),%edx,%r8d
|
||||
cmovs 0x90909090(%eax),%edx,%r8d
|
||||
dec %rax,%r17
|
||||
decb (%r31,%r12,1),%r8b
|
||||
imul 0x909(%rax,%r31,8),%rdx,%r25
|
||||
imul 0x90909(%eax),%edx,%r8d
|
||||
inc %r31,%r16
|
||||
inc %r31,%r8
|
||||
inc %rax,%rbx
|
||||
neg %rax,%r17
|
||||
negb (%r31,%r12,1),%r8b
|
||||
not %rax,%r17
|
||||
notb (%r31,%r12,1),%r8b
|
||||
or $0x1234,%ax,%r30w
|
||||
or %r15b,%r17b,%r18b
|
||||
or %r15d,(%r8),%r18d
|
||||
or (%r15,%rax,1),%r16b,%r8b
|
||||
or (%r15,%rax,1),%r16w,%r8w
|
||||
orl $0x11,(%r19,%rax,4),%r20d
|
||||
rcl $0x2,%r12b,%r31b
|
||||
rcl %cl,%r16b,%r8b
|
||||
rclb $0x1,(%rax),%r31b
|
||||
rcll $0x2,(%rax),%r31d
|
||||
rclw $0x1,(%rax),%r31w
|
||||
rclw %cl,(%r19,%rax,4),%r31w
|
||||
rcr $0x2,%r12b,%r31b
|
||||
rcr %cl,%r16b,%r8b
|
||||
rcrb $0x1,(%rax),%r31b
|
||||
rcrl $0x2,(%rax),%r31d
|
||||
rcrw $0x1,(%rax),%r31w
|
||||
rcrw %cl,(%r19,%rax,4),%r31w
|
||||
rol $0x2,%r12b,%r31b
|
||||
rol %cl,%r16b,%r8b
|
||||
rolb $0x1,(%rax),%r31b
|
||||
roll $0x2,(%rax),%r31d
|
||||
rolw $0x1,(%rax),%r31w
|
||||
rolw %cl,(%r19,%rax,4),%r31w
|
||||
ror $0x2,%r12b,%r31b
|
||||
ror %cl,%r16b,%r8b
|
||||
rorb $0x1,(%rax),%r31b
|
||||
rorl $0x2,(%rax),%r31d
|
||||
rorw $0x1,(%rax),%r31w
|
||||
rorw %cl,(%r19,%rax,4),%r31w
|
||||
sar $0x2,%r12b,%r31b
|
||||
sar %cl,%r16b,%r8b
|
||||
sarb $0x1,(%rax),%r31b
|
||||
sarl $0x2,(%rax),%r31d
|
||||
sarw $0x1,(%rax),%r31w
|
||||
sarw %cl,(%r19,%rax,4),%r31w
|
||||
sbb $0x1234,%ax,%r30w
|
||||
sbb %r15b,%r17b,%r18b
|
||||
sbb %r15d,(%r8),%r18d
|
||||
sbb (%r15,%rax,1),%r16b,%r8b
|
||||
sbb (%r15,%rax,1),%r16w,%r8w
|
||||
sbbl $0x11,(%r19,%rax,4),%r20d
|
||||
shl $0x2,%r12b,%r31b
|
||||
shl $0x2,%r12b,%r31b
|
||||
shl %cl,%r16b,%r8b
|
||||
shl %cl,%r16b,%r8b
|
||||
shlb $0x1,(%rax),%r31b
|
||||
shlb $0x1,(%rax),%r31b
|
||||
shld $0x1,%r12,(%rax),%r31
|
||||
shld $0x2,%r15d,(%rax),%r31d
|
||||
shld $0x2,%r8w,%r12w,%r31w
|
||||
shld %cl,%r12,%r16,%r8
|
||||
shld %cl,%r13w,(%r19,%rax,4),%r31w
|
||||
shld %cl,%r9w,(%rax),%r31w
|
||||
shll $0x2,(%rax),%r31d
|
||||
shll $0x2,(%rax),%r31d
|
||||
shlw $0x1,(%rax),%r31w
|
||||
shlw $0x1,(%rax),%r31w
|
||||
shlw %cl,(%r19,%rax,4),%r31w
|
||||
shlw %cl,(%r19,%rax,4),%r31w
|
||||
shr $0x2,%r12b,%r31b
|
||||
shr %cl,%r16b,%r8b
|
||||
shrb $0x1,(%rax),%r31b
|
||||
shrd $0x1,%r12,(%rax),%r31
|
||||
shrd $0x2,%r15d,(%rax),%r31d
|
||||
shrd $0x2,%r8w,%r12w,%r31w
|
||||
shrd %cl,%r12,%r16,%r8
|
||||
shrd %cl,%r13w,(%r19,%rax,4),%r31w
|
||||
shrd %cl,%r9w,(%rax),%r31w
|
||||
shrl $0x2,(%rax),%r31d
|
||||
shrw $0x1,(%rax),%r31w
|
||||
shrw %cl,(%r19,%rax,4),%r31w
|
||||
sub $0x1234,%ax,%r30w
|
||||
sub %r15b,%r17b,%r18b
|
||||
sub %r15d,(%r8),%r18d
|
||||
sub (%r15,%rax,1),%r16b,%r8b
|
||||
sub (%r15,%rax,1),%r16w,%r8w
|
||||
subl $0x11,(%r19,%rax,4),%r20d
|
||||
xor $0x1234,%ax,%r30w
|
||||
xor %r15b,%r17b,%r18b
|
||||
xor %r15d,(%r8),%r18d
|
||||
xor (%r15,%rax,1),%r16b,%r8b
|
||||
xor (%r15,%rax,1),%r16w,%r8w
|
||||
xorl $0x11,(%r19,%rax,4),%r20d
|
||||
|
||||
@ -137,6 +137,48 @@ Disassembly of section .text:
|
||||
+[a-f0-9]+: 33 07 xor \(%rdi\),%eax
|
||||
+[a-f0-9]+: 31 07 xor %eax,\(%rdi\)
|
||||
+[a-f0-9]+: 33 07 xor \(%rdi\),%eax
|
||||
+[a-f0-9]+: 62 44 fc 10 01 38 add %r31,\(%r8\),%r16
|
||||
+[a-f0-9]+: 62 44 fc 10 03 38 add \(%r8\),%r31,%r16
|
||||
+[a-f0-9]+: 62 44 fc 10 01 38 add %r31,\(%r8\),%r16
|
||||
+[a-f0-9]+: 62 44 fc 10 03 38 add \(%r8\),%r31,%r16
|
||||
+[a-f0-9]+: 62 54 6c 10 29 38 sub %r15d,\(%r8\),%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 2b 38 sub \(%r8\),%r15d,%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 29 38 sub %r15d,\(%r8\),%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 2b 38 sub \(%r8\),%r15d,%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 19 38 sbb %r15d,\(%r8\),%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 1b 38 sbb \(%r8\),%r15d,%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 19 38 sbb %r15d,\(%r8\),%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 1b 38 sbb \(%r8\),%r15d,%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 21 38 and %r15d,\(%r8\),%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 23 38 and \(%r8\),%r15d,%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 21 38 and %r15d,\(%r8\),%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 23 38 and \(%r8\),%r15d,%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 09 38 or %r15d,\(%r8\),%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 0b 38 or \(%r8\),%r15d,%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 09 38 or %r15d,\(%r8\),%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 0b 38 or \(%r8\),%r15d,%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 31 38 xor %r15d,\(%r8\),%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 33 38 xor \(%r8\),%r15d,%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 31 38 xor %r15d,\(%r8\),%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 33 38 xor \(%r8\),%r15d,%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 11 38 adc %r15d,\(%r8\),%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 13 38 adc \(%r8\),%r15d,%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 11 38 adc %r15d,\(%r8\),%r18d
|
||||
+[a-f0-9]+: 62 54 6c 10 13 38 adc \(%r8\),%r15d,%r18d
|
||||
+[a-f0-9]+: 62 44 fc 10 01 f8 add %r31,%r8,%r16
|
||||
+[a-f0-9]+: 62 5c fc 10 03 c7 add %r31,%r8,%r16
|
||||
+[a-f0-9]+: 62 7c 6c 10 28 f9 sub %r15b,%r17b,%r18b
|
||||
+[a-f0-9]+: 62 c4 6c 10 2a cf sub %r15b,%r17b,%r18b
|
||||
+[a-f0-9]+: 62 7c 6c 10 18 f9 sbb %r15b,%r17b,%r18b
|
||||
+[a-f0-9]+: 62 c4 6c 10 1a cf sbb %r15b,%r17b,%r18b
|
||||
+[a-f0-9]+: 62 7c 6c 10 20 f9 and %r15b,%r17b,%r18b
|
||||
+[a-f0-9]+: 62 c4 6c 10 22 cf and %r15b,%r17b,%r18b
|
||||
+[a-f0-9]+: 62 7c 6c 10 08 f9 or %r15b,%r17b,%r18b
|
||||
+[a-f0-9]+: 62 c4 6c 10 0a cf or %r15b,%r17b,%r18b
|
||||
+[a-f0-9]+: 62 7c 6c 10 30 f9 xor %r15b,%r17b,%r18b
|
||||
+[a-f0-9]+: 62 c4 6c 10 32 cf xor %r15b,%r17b,%r18b
|
||||
+[a-f0-9]+: 62 7c 6c 10 10 f9 adc %r15b,%r17b,%r18b
|
||||
+[a-f0-9]+: 62 c4 6c 10 12 cf adc %r15b,%r17b,%r18b
|
||||
+[a-f0-9]+: b0 12 mov \$0x12,%al
|
||||
+[a-f0-9]+: b8 45 03 00 00 mov \$0x345,%eax
|
||||
+[a-f0-9]+: b0 12 mov \$0x12,%al
|
||||
|
||||
@ -134,6 +134,49 @@ _start:
|
||||
{load} xor (%rdi), %eax
|
||||
{store} xor %eax, (%rdi)
|
||||
{store} xor (%rdi), %eax
|
||||
{load} add %r31,(%r8),%r16
|
||||
{load} add (%r8),%r31,%r16
|
||||
{store} add %r31,(%r8),%r16
|
||||
{store} add (%r8),%r31,%r16
|
||||
{load} sub %r15d,(%r8),%r18d
|
||||
{load} sub (%r8),%r15d,%r18d
|
||||
{store} sub %r15d,(%r8),%r18d
|
||||
{store} sub (%r8),%r15d,%r18d
|
||||
{load} sbb %r15d,(%r8),%r18d
|
||||
{load} sbb (%r8),%r15d,%r18d
|
||||
{store} sbb %r15d,(%r8),%r18d
|
||||
{store} sbb (%r8),%r15d,%r18d
|
||||
{load} and %r15d,(%r8),%r18d
|
||||
{load} and (%r8),%r15d,%r18d
|
||||
{store} and %r15d,(%r8),%r18d
|
||||
{store} and (%r8),%r15d,%r18d
|
||||
{load} or %r15d,(%r8),%r18d
|
||||
{load} or (%r8),%r15d,%r18d
|
||||
{store} or %r15d,(%r8),%r18d
|
||||
{store} or (%r8),%r15d,%r18d
|
||||
{load} xor %r15d,(%r8),%r18d
|
||||
{load} xor (%r8),%r15d,%r18d
|
||||
{store} xor %r15d,(%r8),%r18d
|
||||
{store} xor (%r8),%r15d,%r18d
|
||||
{load} adc %r15d,(%r8),%r18d
|
||||
{load} adc (%r8),%r15d,%r18d
|
||||
{store} adc %r15d,(%r8),%r18d
|
||||
{store} adc (%r8),%r15d,%r18d
|
||||
|
||||
{store} add %r31,%r8,%r16
|
||||
{load} add %r31,%r8,%r16
|
||||
{store} sub %r15b,%r17b,%r18b
|
||||
{load} sub %r15b,%r17b,%r18b
|
||||
{store} sbb %r15b,%r17b,%r18b
|
||||
{load} sbb %r15b,%r17b,%r18b
|
||||
{store} and %r15b,%r17b,%r18b
|
||||
{load} and %r15b,%r17b,%r18b
|
||||
{store} or %r15b,%r17b,%r18b
|
||||
{load} or %r15b,%r17b,%r18b
|
||||
{store} xor %r15b,%r17b,%r18b
|
||||
{load} xor %r15b,%r17b,%r18b
|
||||
{store} adc %r15b,%r17b,%r18b
|
||||
{load} adc %r15b,%r17b,%r18b
|
||||
|
||||
.irp m, mov, adc, add, and, cmp, or, sbb, sub, test, xor
|
||||
\m $0x12, %al
|
||||
|
||||
@ -370,6 +370,7 @@ run_dump_test "x86-64-apx-rex2"
|
||||
run_dump_test "x86-64-apx-evex-promoted"
|
||||
run_dump_test "x86-64-apx-evex-promoted-intel"
|
||||
run_dump_test "x86-64-apx-evex-egpr"
|
||||
run_dump_test "x86-64-apx-ndd"
|
||||
run_dump_test "x86-64-avx512f-rcigrz-intel"
|
||||
run_dump_test "x86-64-avx512f-rcigrz"
|
||||
run_dump_test "x86-64-clwb"
|
||||
|
||||
@ -49,3 +49,57 @@
|
||||
{ "vscatterpf0qp%XW", { MVexVSIBQWpX }, PREFIX_DATA },
|
||||
{ "vscatterpf1qp%XW", { MVexVSIBQWpX }, PREFIX_DATA },
|
||||
},
|
||||
/* REG_EVEX_MAP4_80 */
|
||||
{
|
||||
{ "addA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
{ "orA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
{ "adcA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
{ "sbbA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
{ "andA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
{ "subA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
{ "xorA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
},
|
||||
/* REG_EVEX_MAP4_81 */
|
||||
{
|
||||
{ "addQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
|
||||
{ "orQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
|
||||
{ "adcQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
|
||||
{ "sbbQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
|
||||
{ "andQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
|
||||
{ "subQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
|
||||
{ "xorQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA },
|
||||
},
|
||||
/* REG_EVEX_MAP4_83 */
|
||||
{
|
||||
{ "addQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
||||
{ "orQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
||||
{ "adcQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
||||
{ "sbbQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
||||
{ "andQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
||||
{ "subQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
||||
{ "xorQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
||||
},
|
||||
/* REG_EVEX_MAP4_F6 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "notA", { VexGb, Eb }, NO_PREFIX },
|
||||
{ "negA", { VexGb, Eb }, NO_PREFIX },
|
||||
},
|
||||
/* REG_EVEX_MAP4_F7 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "notQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "negQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
|
||||
},
|
||||
/* REG_EVEX_MAP4_FE */
|
||||
{
|
||||
{ "incA", { VexGb, Eb }, NO_PREFIX },
|
||||
{ "decA", { VexGb, Eb }, NO_PREFIX },
|
||||
},
|
||||
/* REG_EVEX_MAP4_FF */
|
||||
{
|
||||
{ "incQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "decQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
|
||||
},
|
||||
|
||||
@ -875,64 +875,64 @@ static const struct dis386 evex_table[][256] = {
|
||||
/* EVEX_MAP4_ */
|
||||
{
|
||||
/* 00 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "addB", { VexGb, Eb, Gb }, NO_PREFIX },
|
||||
{ "addS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
|
||||
{ "addB", { VexGb, Gb, EbS }, NO_PREFIX },
|
||||
{ "addS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
/* 08 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "orB", { VexGb, Eb, Gb }, NO_PREFIX },
|
||||
{ "orS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
|
||||
{ "orB", { VexGb, Gb, EbS }, NO_PREFIX },
|
||||
{ "orS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
/* 10 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "adcB", { VexGb, Eb, Gb }, NO_PREFIX },
|
||||
{ "adcS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
|
||||
{ "adcB", { VexGb, Gb, EbS }, NO_PREFIX },
|
||||
{ "adcS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
/* 18 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "sbbB", { VexGb, Eb, Gb }, NO_PREFIX },
|
||||
{ "sbbS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
|
||||
{ "sbbB", { VexGb, Gb, EbS }, NO_PREFIX },
|
||||
{ "sbbS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
/* 20 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "andB", { VexGb, Eb, Gb }, NO_PREFIX },
|
||||
{ "andS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
|
||||
{ "andB", { VexGb, Gb, EbS }, NO_PREFIX },
|
||||
{ "andS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
|
||||
{ "shldS", { VexGv, Ev, Gv, Ib }, PREFIX_NP_OR_DATA },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
/* 28 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "subB", { VexGb, Eb, Gb }, NO_PREFIX },
|
||||
{ "subS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
|
||||
{ "subB", { VexGb, Gb, EbS }, NO_PREFIX },
|
||||
{ "subS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
|
||||
{ "shrdS", { VexGv, Ev, Gv, Ib }, PREFIX_NP_OR_DATA },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
/* 30 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "xorB", { VexGb, Eb, Gb }, NO_PREFIX },
|
||||
{ "xorS", { VexGv, Ev, Gv }, PREFIX_NP_OR_DATA },
|
||||
{ "xorB", { VexGb, Gb, EbS }, NO_PREFIX },
|
||||
{ "xorS", { VexGv, Gv, EvS }, PREFIX_NP_OR_DATA },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
@ -947,23 +947,23 @@ static const struct dis386 evex_table[][256] = {
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
/* 40 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "%CFcmovoS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "%CFcmovnoS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "%CFcmovbS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "%CFcmovaeS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "%CFcmoveS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "%CFcmovneS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "%CFcmovbeS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "%CFcmovaS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
/* 48 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "%CFcmovsS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "%CFcmovnsS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "%CFcmovpS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "%CFcmovnpS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "%CFcmovlS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "%CFcmovgeS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "%CFcmovleS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "%CFcmovgS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
/* 50 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
@ -1019,10 +1019,10 @@ static const struct dis386 evex_table[][256] = {
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
/* 80 */
|
||||
{ REG_TABLE (REG_EVEX_MAP4_80) },
|
||||
{ REG_TABLE (REG_EVEX_MAP4_81) },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ REG_TABLE (REG_EVEX_MAP4_83) },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
@ -1060,7 +1060,7 @@ static const struct dis386 evex_table[][256] = {
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "shldS", { VexGv, Ev, Gv, CL }, PREFIX_NP_OR_DATA },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
/* A8 */
|
||||
@ -1069,9 +1069,9 @@ static const struct dis386 evex_table[][256] = {
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "shrdS", { VexGv, Ev, Gv, CL }, PREFIX_NP_OR_DATA },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "imulS", { VexGv, Gv, Ev }, PREFIX_NP_OR_DATA },
|
||||
/* B0 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
@ -1091,8 +1091,8 @@ static const struct dis386 evex_table[][256] = {
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
/* C0 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ REG_TABLE (REG_C0) },
|
||||
{ REG_TABLE (REG_C1) },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
@ -1109,10 +1109,10 @@ static const struct dis386 evex_table[][256] = {
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
/* D0 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ REG_TABLE (REG_D0) },
|
||||
{ REG_TABLE (REG_D1) },
|
||||
{ REG_TABLE (REG_D2) },
|
||||
{ REG_TABLE (REG_D3) },
|
||||
{ "sha1rnds4", { XM, EXxmm, Ib }, NO_PREFIX },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
@ -1151,8 +1151,8 @@ static const struct dis386 evex_table[][256] = {
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ REG_TABLE (REG_EVEX_MAP4_F6) },
|
||||
{ REG_TABLE (REG_EVEX_MAP4_F7) },
|
||||
/* F8 */
|
||||
{ PREFIX_TABLE (PREFIX_EVEX_MAP4_F8) },
|
||||
{ "movdiri", { Mdq, Gdq }, NO_PREFIX },
|
||||
@ -1160,8 +1160,8 @@ static const struct dis386 evex_table[][256] = {
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_0F38FC) },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ REG_TABLE (REG_EVEX_MAP4_FE) },
|
||||
{ REG_TABLE (REG_EVEX_MAP4_FF) },
|
||||
},
|
||||
/* EVEX_MAP5_ */
|
||||
{
|
||||
|
||||
@ -226,6 +226,9 @@ struct instr_info
|
||||
}
|
||||
vex;
|
||||
|
||||
/* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b. */
|
||||
#define nd b
|
||||
|
||||
enum evex_type evex_type;
|
||||
|
||||
/* Remember if the current op is a jump instruction. */
|
||||
@ -578,6 +581,8 @@ fetch_error (const instr_info *ins)
|
||||
#define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
|
||||
#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
|
||||
#define VexGdq { OP_VEX, dq_mode }
|
||||
#define VexGb { OP_VEX, b_mode }
|
||||
#define VexGv { OP_VEX, v_mode }
|
||||
#define VexTmm { OP_VEX, tmm_mode }
|
||||
#define XMVexI4 { OP_REG_VexI4, x_mode }
|
||||
#define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
|
||||
@ -892,6 +897,13 @@ enum
|
||||
REG_EVEX_0F73,
|
||||
REG_EVEX_0F38C6_L_2,
|
||||
REG_EVEX_0F38C7_L_2,
|
||||
REG_EVEX_MAP4_80,
|
||||
REG_EVEX_MAP4_81,
|
||||
REG_EVEX_MAP4_83,
|
||||
REG_EVEX_MAP4_F6,
|
||||
REG_EVEX_MAP4_F7,
|
||||
REG_EVEX_MAP4_FE,
|
||||
REG_EVEX_MAP4_FF,
|
||||
};
|
||||
|
||||
enum
|
||||
@ -2599,25 +2611,25 @@ static const struct dis386 reg_table[][8] = {
|
||||
},
|
||||
/* REG_C0 */
|
||||
{
|
||||
{ "rolA", { Eb, Ib }, 0 },
|
||||
{ "rorA", { Eb, Ib }, 0 },
|
||||
{ "rclA", { Eb, Ib }, 0 },
|
||||
{ "rcrA", { Eb, Ib }, 0 },
|
||||
{ "shlA", { Eb, Ib }, 0 },
|
||||
{ "shrA", { Eb, Ib }, 0 },
|
||||
{ "shlA", { Eb, Ib }, 0 },
|
||||
{ "sarA", { Eb, Ib }, 0 },
|
||||
{ "rolA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
{ "rorA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
{ "rclA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
{ "rcrA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
{ "shlA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
{ "shrA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
{ "shlA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
{ "sarA", { VexGb, Eb, Ib }, NO_PREFIX },
|
||||
},
|
||||
/* REG_C1 */
|
||||
{
|
||||
{ "rolQ", { Ev, Ib }, 0 },
|
||||
{ "rorQ", { Ev, Ib }, 0 },
|
||||
{ "rclQ", { Ev, Ib }, 0 },
|
||||
{ "rcrQ", { Ev, Ib }, 0 },
|
||||
{ "shlQ", { Ev, Ib }, 0 },
|
||||
{ "shrQ", { Ev, Ib }, 0 },
|
||||
{ "shlQ", { Ev, Ib }, 0 },
|
||||
{ "sarQ", { Ev, Ib }, 0 },
|
||||
{ "rolQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
|
||||
{ "rorQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
|
||||
{ "rclQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
|
||||
{ "rcrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
|
||||
{ "shlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
|
||||
{ "shrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
|
||||
{ "shlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
|
||||
{ "sarQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
|
||||
},
|
||||
/* REG_C6 */
|
||||
{
|
||||
@ -2643,47 +2655,47 @@ static const struct dis386 reg_table[][8] = {
|
||||
},
|
||||
/* REG_D0 */
|
||||
{
|
||||
{ "rolA", { Eb, I1 }, 0 },
|
||||
{ "rorA", { Eb, I1 }, 0 },
|
||||
{ "rclA", { Eb, I1 }, 0 },
|
||||
{ "rcrA", { Eb, I1 }, 0 },
|
||||
{ "shlA", { Eb, I1 }, 0 },
|
||||
{ "shrA", { Eb, I1 }, 0 },
|
||||
{ "shlA", { Eb, I1 }, 0 },
|
||||
{ "sarA", { Eb, I1 }, 0 },
|
||||
{ "rolA", { VexGb, Eb, I1 }, NO_PREFIX },
|
||||
{ "rorA", { VexGb, Eb, I1 }, NO_PREFIX },
|
||||
{ "rclA", { VexGb, Eb, I1 }, NO_PREFIX },
|
||||
{ "rcrA", { VexGb, Eb, I1 }, NO_PREFIX },
|
||||
{ "shlA", { VexGb, Eb, I1 }, NO_PREFIX },
|
||||
{ "shrA", { VexGb, Eb, I1 }, NO_PREFIX },
|
||||
{ "shlA", { VexGb, Eb, I1 }, NO_PREFIX },
|
||||
{ "sarA", { VexGb, Eb, I1 }, NO_PREFIX },
|
||||
},
|
||||
/* REG_D1 */
|
||||
{
|
||||
{ "rolQ", { Ev, I1 }, 0 },
|
||||
{ "rorQ", { Ev, I1 }, 0 },
|
||||
{ "rclQ", { Ev, I1 }, 0 },
|
||||
{ "rcrQ", { Ev, I1 }, 0 },
|
||||
{ "shlQ", { Ev, I1 }, 0 },
|
||||
{ "shrQ", { Ev, I1 }, 0 },
|
||||
{ "shlQ", { Ev, I1 }, 0 },
|
||||
{ "sarQ", { Ev, I1 }, 0 },
|
||||
{ "rolQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
|
||||
{ "rorQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
|
||||
{ "rclQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
|
||||
{ "rcrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
|
||||
{ "shlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
|
||||
{ "shrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
|
||||
{ "shlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
|
||||
{ "sarQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
|
||||
},
|
||||
/* REG_D2 */
|
||||
{
|
||||
{ "rolA", { Eb, CL }, 0 },
|
||||
{ "rorA", { Eb, CL }, 0 },
|
||||
{ "rclA", { Eb, CL }, 0 },
|
||||
{ "rcrA", { Eb, CL }, 0 },
|
||||
{ "shlA", { Eb, CL }, 0 },
|
||||
{ "shrA", { Eb, CL }, 0 },
|
||||
{ "shlA", { Eb, CL }, 0 },
|
||||
{ "sarA", { Eb, CL }, 0 },
|
||||
{ "rolA", { VexGb, Eb, CL }, NO_PREFIX },
|
||||
{ "rorA", { VexGb, Eb, CL }, NO_PREFIX },
|
||||
{ "rclA", { VexGb, Eb, CL }, NO_PREFIX },
|
||||
{ "rcrA", { VexGb, Eb, CL }, NO_PREFIX },
|
||||
{ "shlA", { VexGb, Eb, CL }, NO_PREFIX },
|
||||
{ "shrA", { VexGb, Eb, CL }, NO_PREFIX },
|
||||
{ "shlA", { VexGb, Eb, CL }, NO_PREFIX },
|
||||
{ "sarA", { VexGb, Eb, CL }, NO_PREFIX },
|
||||
},
|
||||
/* REG_D3 */
|
||||
{
|
||||
{ "rolQ", { Ev, CL }, 0 },
|
||||
{ "rorQ", { Ev, CL }, 0 },
|
||||
{ "rclQ", { Ev, CL }, 0 },
|
||||
{ "rcrQ", { Ev, CL }, 0 },
|
||||
{ "shlQ", { Ev, CL }, 0 },
|
||||
{ "shrQ", { Ev, CL }, 0 },
|
||||
{ "shlQ", { Ev, CL }, 0 },
|
||||
{ "sarQ", { Ev, CL }, 0 },
|
||||
{ "rolQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
|
||||
{ "rorQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
|
||||
{ "rclQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
|
||||
{ "rcrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
|
||||
{ "shlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
|
||||
{ "shrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
|
||||
{ "shlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
|
||||
{ "sarQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
|
||||
},
|
||||
/* REG_F6 */
|
||||
{
|
||||
@ -3633,8 +3645,8 @@ static const struct dis386 prefix_table[][4] = {
|
||||
/* PREFIX_0F38F6 */
|
||||
{
|
||||
{ "wrssK", { M, Gdq }, 0 },
|
||||
{ "adoxS", { Gdq, Edq}, 0 },
|
||||
{ "adcxS", { Gdq, Edq}, 0 },
|
||||
{ "adoxS", { VexGdq, Gdq, Edq}, 0 },
|
||||
{ "adcxS", { VexGdq, Gdq, Edq}, 0 },
|
||||
{ Bad_Opcode },
|
||||
},
|
||||
|
||||
@ -9120,6 +9132,12 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
|
||||
ins->rex2 &= ~REX_R;
|
||||
}
|
||||
|
||||
/* EVEX from legacy instructions, when the EVEX.ND bit is 0,
|
||||
all bits of EVEX.vvvv and EVEX.V' must be 1. */
|
||||
if (ins->evex_type == evex_from_legacy && !ins->vex.nd
|
||||
&& (ins->vex.register_specifier || !ins->vex.v))
|
||||
return &bad_opcode;
|
||||
|
||||
ins->need_vex = 4;
|
||||
|
||||
/* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the
|
||||
@ -9137,8 +9155,10 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
|
||||
if (!fetch_modrm (ins))
|
||||
return &err_opcode;
|
||||
|
||||
/* Set vector length. */
|
||||
if (ins->modrm.mod == 3 && ins->vex.b)
|
||||
/* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00,
|
||||
which has the same encoding as vex.length == 128 and they can share
|
||||
the same processing with vex.length in OP_VEX. */
|
||||
if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy)
|
||||
ins->vex.length = 512;
|
||||
else
|
||||
{
|
||||
@ -9605,8 +9625,8 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
|
||||
}
|
||||
|
||||
/* Check whether rounding control was enabled for an insn not
|
||||
supporting it. */
|
||||
if (ins.modrm.mod == 3 && ins.vex.b
|
||||
supporting it, when evex.b is not treated as evex.nd. */
|
||||
if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default
|
||||
&& !(ins.evex_used & EVEX_b_used))
|
||||
{
|
||||
for (i = 0; i < MAX_OPERANDS; ++i)
|
||||
@ -10499,16 +10519,23 @@ putop (instr_info *ins, const char *in_template, int sizeflag)
|
||||
ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
|
||||
break;
|
||||
case 'F':
|
||||
if (ins->intel_syntax)
|
||||
break;
|
||||
if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
|
||||
if (l == 0)
|
||||
{
|
||||
if (sizeflag & AFLAG)
|
||||
*ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
|
||||
else
|
||||
*ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
|
||||
ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
|
||||
if (ins->intel_syntax)
|
||||
break;
|
||||
if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
|
||||
{
|
||||
if (sizeflag & AFLAG)
|
||||
*ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
|
||||
else
|
||||
*ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
|
||||
ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
|
||||
}
|
||||
}
|
||||
else if (l == 1 && last[0] == 'C')
|
||||
break;
|
||||
else
|
||||
abort ();
|
||||
break;
|
||||
case 'G':
|
||||
if (ins->intel_syntax || (ins->obufp[-1] != 's'
|
||||
@ -11072,7 +11099,8 @@ print_displacement (instr_info *ins, bfd_signed_vma val)
|
||||
static void
|
||||
intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
|
||||
{
|
||||
if (ins->vex.b)
|
||||
/* Check if there is a broadcast, when evex.b is not treated as evex.nd. */
|
||||
if (ins->vex.b && ins->evex_type == evex_default)
|
||||
{
|
||||
if (!ins->vex.no_broadcast)
|
||||
switch (bytemode)
|
||||
@ -11569,6 +11597,7 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
|
||||
|
||||
add += (ins->rex2 & REX_B) ? 16 : 0;
|
||||
|
||||
/* Handles EVEX other than APX EVEX-promoted instructions. */
|
||||
if (ins->vex.evex && ins->evex_type == evex_default)
|
||||
{
|
||||
|
||||
@ -12004,7 +12033,7 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
|
||||
print_operand_value (ins, disp & 0xffff, dis_style_text);
|
||||
}
|
||||
}
|
||||
if (ins->vex.b)
|
||||
if (ins->vex.b && ins->evex_type == evex_default)
|
||||
{
|
||||
ins->evex_used |= EVEX_b_used;
|
||||
|
||||
@ -13370,6 +13399,13 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
|
||||
if (!ins->need_vex)
|
||||
return true;
|
||||
|
||||
if (ins->evex_type == evex_from_legacy)
|
||||
{
|
||||
ins->evex_used |= EVEX_b_used;
|
||||
if (!ins->vex.nd)
|
||||
return true;
|
||||
}
|
||||
|
||||
reg = ins->vex.register_specifier;
|
||||
ins->vex.register_specifier = 0;
|
||||
if (ins->address_mode != mode_64bit)
|
||||
@ -13461,12 +13497,19 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
|
||||
names = att_names_xmm;
|
||||
ins->evex_used |= EVEX_len_used;
|
||||
break;
|
||||
case v_mode:
|
||||
case dq_mode:
|
||||
if (ins->rex & REX_W)
|
||||
names = att_names64;
|
||||
else if (bytemode == v_mode
|
||||
&& !(sizeflag & DFLAG))
|
||||
names = att_names16;
|
||||
else
|
||||
names = att_names32;
|
||||
break;
|
||||
case b_mode:
|
||||
names = att_names8rex;
|
||||
break;
|
||||
case mask_bd_mode:
|
||||
case mask_mode:
|
||||
if (reg > 0x7)
|
||||
|
||||
@ -638,8 +638,10 @@ enum
|
||||
Vex,
|
||||
/* How to encode VEX.vvvv:
|
||||
0: VEX.vvvv must be 1111b.
|
||||
1: VEX.vvvv encodes one of the register operands.
|
||||
1: VEX.vvvv encodes one of the src register operands.
|
||||
2: VEX.vvvv encodes the dest register operand.
|
||||
*/
|
||||
#define VexVVVV_DST 2
|
||||
VexVVVV,
|
||||
/* How the VEX.W bit is used:
|
||||
0: Set by the REX.W bit.
|
||||
@ -776,7 +778,7 @@ typedef struct i386_opcode_modifier
|
||||
unsigned int immext:1;
|
||||
unsigned int norex64:1;
|
||||
unsigned int vex:2;
|
||||
unsigned int vexvvvv:1;
|
||||
unsigned int vexvvvv:2;
|
||||
unsigned int vexw:2;
|
||||
unsigned int opcodeprefix:2;
|
||||
unsigned int sib:3;
|
||||
|
||||
@ -140,12 +140,16 @@
|
||||
|
||||
#define Disp8ShiftVL Disp8MemShift=DISP8_SHIFT_VL
|
||||
|
||||
#define DstVVVV VexVVVV=VexVVVV_DST
|
||||
|
||||
// The template supports VEX format for cpuid and EVEX format for cpuid & apx_f.
|
||||
#define APX_F(cpuid) cpuid&(cpuid|APX_F)
|
||||
|
||||
// The EVEX purpose of StaticRounding appears only together with SAE. Re-use
|
||||
// the bit to mark commutative VEX encodings where swapping the source
|
||||
// operands may allow to switch from 3-byte to 2-byte VEX encoding.
|
||||
// And re-use the bit to mark some NDD insns that swapping the source operands
|
||||
// may allow to switch from EVEX encoding to REX2 encoding.
|
||||
#define C StaticRounding
|
||||
|
||||
#define FP 387|287|8087
|
||||
@ -292,26 +296,38 @@ std, 0xfd, 0, NoSuf, {}
|
||||
sti, 0xfb, 0, NoSuf, {}
|
||||
|
||||
// Arithmetic.
|
||||
add, 0x0, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
add, 0x0, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
add, 0x83/0, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
add, 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
|
||||
add, 0x80/0, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64}
|
||||
add, 0x80/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
inc, 0x40, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
|
||||
inc, 0xfe/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, {Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64}
|
||||
inc, 0xfe/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
sub, 0x28, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64, }
|
||||
sub, 0x28, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
sub, 0x83/5, APX_F, Modrm|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
sub, 0x83/5, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
sub, 0x2c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
|
||||
sub, 0x80/5, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
sub, 0x80/5, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
dec, 0x48, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
|
||||
dec, 0xfe/1, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
dec, 0xfe/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
sbb, 0x18, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
sbb, 0x18, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
sbb, 0x83/3, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
sbb, 0x83/3, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
sbb, 0x1c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
|
||||
sbb, 0x80/3, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
sbb, 0x80/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
sbb, 0x80/3, APX_F, W|Modrm|EVexMap4|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
cmp, 0x38, 0, D|W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
cmp, 0x83/7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
@ -322,30 +338,45 @@ test, 0x84, 0, D|W|C|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, R
|
||||
test, 0xa8, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
|
||||
test, 0xf6/0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
and, 0x20, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
and, 0x20, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
and, 0x83/4, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
and, 0x83/4, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock|Optimize, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
and, 0x24, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
|
||||
and, 0x80/4, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
and, 0x80/4, 0, W|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
or, 0x8, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
or, 0x8, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
or, 0x83/1, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
or, 0x83/1, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
or, 0xc, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
|
||||
or, 0x80/1, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
or, 0x80/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
xor, 0x30, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
xor, 0x30, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
xor, 0x83/6, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
xor, 0x83/6, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
xor, 0x34, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
|
||||
xor, 0x80/6, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
xor, 0x80/6, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
// clr with 1 operand is really xor with 2 operands.
|
||||
clr, 0x30, 0, W|Modrm|No_sSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 }
|
||||
|
||||
adc, 0x10, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
adc, 0x10, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
adc, 0x83/2, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
adc, 0x83/2, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
adc, 0x14, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
|
||||
adc, 0x80/2, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
adc, 0x80/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
neg, 0xf6/3, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
neg, 0xf6/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
not, 0xf6/2, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
not, 0xf6/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
aaa, 0x37, No64, NoSuf, {}
|
||||
@ -379,6 +410,7 @@ cqto, 0x99, x64, Size64|NoSuf, {}
|
||||
// These multiplies can only be selected with single operand forms.
|
||||
mul, 0xf6/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
imul, 0xf6/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
imul, 0xaf, APX_F, C|Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
|
||||
imul, 0xfaf, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
imul, 0x6b, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
imul, 0x69, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
@ -393,52 +425,90 @@ div, 0xf6/6, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspe
|
||||
idiv, 0xf6/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
idiv, 0xf6/7, 0, W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
|
||||
|
||||
rol, 0xd0/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rol, 0xc0/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
rol, 0xc0/0, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rol, 0xd2/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
ror, 0xd0/1, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
ror, 0xc0/1, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
ror, 0xc0/1, i186, W|Modrm|No_sSuf, { Imm8|Imm8S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
ror, 0xd2/1, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
ror, 0xd2/1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
rcl, 0xd0/2, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rcl, 0xd0/2, APX_F, W|Modrm|No_sSuf|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rcl, 0xc0/2, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
rcl, 0xc0/2, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rcl, 0xc0/2, APX_F, W|Modrm|No_sSuf|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rcl, 0xd2/2, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
rcl, 0xd2/2, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rcl, 0xd2/2, APX_F, W|Modrm|No_sSuf|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rcl, 0xd0/2, APX_F, W|Modrm|No_sSuf|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
rcr, 0xd0/3, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rcr, 0xd0/3, APX_F, W|Modrm|No_sSuf|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rcr, 0xc0/3, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
rcr, 0xc0/3, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rcr, 0xc0/3, APX_F, W|Modrm|No_sSuf|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rcr, 0xd2/3, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
rcr, 0xd2/3, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rcr, 0xd2/3, APX_F, W|Modrm|No_sSuf|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
rcr, 0xd0/3, APX_F, W|Modrm|No_sSuf|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
sal, 0xd0/4, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
sal, 0xc0/4, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
sal, 0xc0/4, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
sal, 0xd2/4, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
sal, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
shl, 0xd0/4, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
shl, 0xc0/4, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
shl, 0xc0/4, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
shl, 0xd2/4, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
shl, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
shr, 0xd0/5, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
shr, 0xc0/5, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
shr, 0xc0/5, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
shr, 0xd2/5, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
shr, 0xd2/5, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
sar, 0xd0/7, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
sar, 0xc0/7, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
sar, 0xc0/7, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
sar, 0xd2/7, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 }
|
||||
sar, 0xd2/7, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
shld, 0x24, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
shld, 0xfa4, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
shld, 0xa5, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
shld, 0xfa5, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
shld, 0xa5, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
shld, 0xfa5, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
shrd, 0x2c, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
shrd, 0xfac, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
shrd, 0xad, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
shrd, 0xfad, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
shrd, 0xad, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
shrd, 0xfad, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Unspecified|BaseIndex }
|
||||
|
||||
// Control transfer instructions.
|
||||
@ -940,6 +1010,7 @@ ud2b, 0xfb9, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|U
|
||||
// 3rd official undefined instr (older CPUs don't take a ModR/M byte)
|
||||
ud0, 0xfff, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
|
||||
cmov<cc>, 0x4<cc:opc>, CMOV&APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
|
||||
cmov<cc>, 0xf4<cc:opc>, CMOV, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
|
||||
fcmovb, 0xda/0, i687, Modrm|NoSuf, { FloatReg, FloatAcc }
|
||||
@ -2031,8 +2102,12 @@ xcryptofb, 0xf30fa7e8, PadLock, NoSuf|RepPrefixOk, {}
|
||||
xstore, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {}
|
||||
|
||||
// Multy-precision Add Carry, rdseed instructions.
|
||||
adcx, 0x6666, ADX&APX_F, C|Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|DstVVVV|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
|
||||
adcx, 0x660f38f6, ADX, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
adcx, 0x6666, ADX&APX_F, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
adox, 0xf366, ADX&APX_F, C|Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|DstVVVV|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 }
|
||||
adox, 0xf30f38f6, ADX, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
adox, 0xf366, ADX&APX_F, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||
rdseed, 0xfc7/7, RdSeed, Modrm|NoSuf, { Reg16|Reg32|Reg64 }
|
||||
|
||||
// SMAP instructions.
|
||||
|
||||
1633
opcodes/i386-tbl.h
1633
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user