x86: move reg_operands adjustment
Ideally we'd do away with this somewhat questionable adjustment (leaving i.types[] untouched). That's non-trivial though as it looks, so only - move the logic into process_operands(), putting it closer to related logic and eliminating a conditional for operand-less insns, - make it consistent (i.e. also affect %xmm0), eliminating an ugly special case later in the function.
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@ -5317,14 +5317,6 @@ md_assemble (char *line)
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if (i.types[0].bitfield.imm1)
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i.imm_operands = 0; /* kludge for shift insns. */
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/* We only need to check those implicit registers for instructions
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with 3 operands or less. */
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if (i.operands <= 3)
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for (j = 0; j < i.operands; j++)
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if (i.types[j].bitfield.instance != InstanceNone
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&& !i.types[j].bitfield.xmmword)
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i.reg_operands--;
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/* For insns with operands there are more diddles to do to the opcode. */
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if (i.operands)
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{
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@ -7936,6 +7928,13 @@ process_operands (void)
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unnecessary segment overrides. */
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const reg_entry *default_seg = NULL;
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/* We only need to check those implicit registers for instructions
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with 3 operands or less. */
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if (i.operands <= 3)
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for (unsigned int j = 0; j < i.operands; j++)
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if (i.types[j].bitfield.instance != InstanceNone)
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i.reg_operands--;
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if (i.tm.opcode_modifier.sse2avx)
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{
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/* Legacy encoded insns allow explicit REX prefixes, so these prefixes
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@ -7970,6 +7969,7 @@ process_operands (void)
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sources. */
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i.tm.operand_types[0].bitfield.instance = InstanceNone;
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i.tm.operand_types[0].bitfield.class = RegSIMD;
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i.reg_operands++;
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goto duplicate;
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}
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@ -8025,11 +8025,6 @@ process_operands (void)
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{
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unsigned int j;
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/* This needs to account for the adjustment already done ahead of
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calling process_operands(). */
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if (i.tm.operand_types[0].bitfield.xmmword)
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i.reg_operands--;
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for (j = 1; j < i.operands; j++)
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{
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i.op[j - 1] = i.op[j];
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@ -8042,6 +8037,8 @@ process_operands (void)
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i.flags[j - 1] = i.flags[j];
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}
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/* No adjustment to i.reg_operands: This was already done at the top
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of the function. */
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i.operands--;
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i.tm.operands--;
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}
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