gcc-4.5 build fixes
Trying to build binutils with an older gcc currently fails. Working around these gcc bugs is not onerous so let's fix them. bfd/ * elf32-csky.c (csky_elf_size_dynamic_sections): Don't type-pun pointer. * elf32-rl78.c (rl78_compute_complex_reloc): Rename "stat" variable to "status". gas/ * compress-debug.c (compress_finish): Supply all fields in ZSTD_inBuffer initialisation. include/ * xtensa-dynconfig.h (xtensa_isa_internal): Delete unnecessary forward declaration. opcodes/ * loongarch-opc.c: Supply all fields of zero struct initialisation in various opcode tables.
This commit is contained in:
Alan Modra
parent
f5b7a67f8d
commit
3318d80021
@ -1942,8 +1942,7 @@ csky_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
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{
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struct elf_dyn_relocs *p;
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for (p = *((struct elf_dyn_relocs **)
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&elf_section_data (s)->local_dynrel);
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for (p = elf_section_data (s)->local_dynrel;
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p != NULL;
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p = p->next)
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{
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@ -396,18 +396,18 @@ rl78_compute_complex_reloc (unsigned long r_type,
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{
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int32_t tmp1, tmp2;
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bfd_vma relocation = 0;
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bfd_reloc_status_type stat = bfd_reloc_ok;
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bfd_reloc_status_type status = bfd_reloc_ok;
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switch (r_type)
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{
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default:
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stat = bfd_reloc_notsupported;
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status = bfd_reloc_notsupported;
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break;
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case R_RL78_ABS24S_PCREL:
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case R_RL78_ABS16S_PCREL:
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case R_RL78_ABS8S_PCREL:
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relocation = rl78_stack_pop (&stat);
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relocation = rl78_stack_pop (&status);
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relocation -= input_section->output_section->vma + input_section->output_offset;
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break;
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@ -420,141 +420,141 @@ rl78_compute_complex_reloc (unsigned long r_type,
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case R_RL78_ABS8:
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case R_RL78_ABS8U:
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case R_RL78_ABS8S:
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relocation = rl78_stack_pop (&stat);
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relocation = rl78_stack_pop (&status);
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break;
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case R_RL78_ABS16UL:
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case R_RL78_ABS8UL:
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relocation = rl78_stack_pop (&stat) >> 2;
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relocation = rl78_stack_pop (&status) >> 2;
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break;;
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case R_RL78_ABS16UW:
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case R_RL78_ABS8UW:
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relocation = rl78_stack_pop (&stat) >> 1;
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relocation = rl78_stack_pop (&status) >> 1;
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break;
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/* The rest of the relocs compute values and then push them onto the stack. */
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case R_RL78_OPramtop:
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case R_RL78_OPromtop:
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case R_RL78_SYM:
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rl78_stack_push (symval, &stat);
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rl78_stack_push (symval, &status);
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break;
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case R_RL78_OPneg:
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tmp1 = rl78_stack_pop (&stat);
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tmp1 = rl78_stack_pop (&status);
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tmp1 = - tmp1;
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rl78_stack_push (tmp1, &stat);
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rl78_stack_push (tmp1, &status);
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break;
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case R_RL78_OPadd:
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tmp2 = rl78_stack_pop (&stat);
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tmp1 = rl78_stack_pop (&stat);
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tmp2 = rl78_stack_pop (&status);
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tmp1 = rl78_stack_pop (&status);
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tmp1 += tmp2;
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rl78_stack_push (tmp1, &stat);
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rl78_stack_push (tmp1, &status);
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break;
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case R_RL78_OPsub:
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/* For the expression "A - B", the assembler pushes A,
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then B, then OPSUB. So the first op we pop is B, not A. */
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tmp2 = rl78_stack_pop (&stat); /* B */
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tmp1 = rl78_stack_pop (&stat); /* A */
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tmp2 = rl78_stack_pop (&status); /* B */
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tmp1 = rl78_stack_pop (&status); /* A */
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tmp1 -= tmp2; /* A - B */
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rl78_stack_push (tmp1, &stat);
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rl78_stack_push (tmp1, &status);
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break;
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case R_RL78_OPmul:
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tmp2 = rl78_stack_pop (&stat);
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tmp1 = rl78_stack_pop (&stat);
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tmp2 = rl78_stack_pop (&status);
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tmp1 = rl78_stack_pop (&status);
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tmp1 *= tmp2;
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rl78_stack_push (tmp1, &stat);
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rl78_stack_push (tmp1, &status);
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break;
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case R_RL78_OPdiv:
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tmp2 = rl78_stack_pop (&stat);
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tmp1 = rl78_stack_pop (&stat);
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tmp2 = rl78_stack_pop (&status);
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tmp1 = rl78_stack_pop (&status);
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if (tmp2 != 0)
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tmp1 /= tmp2;
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else
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{
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tmp1 = 0;
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stat = bfd_reloc_overflow;
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status = bfd_reloc_overflow;
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}
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rl78_stack_push (tmp1, &stat);
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rl78_stack_push (tmp1, &status);
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break;
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case R_RL78_OPshla:
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tmp2 = rl78_stack_pop (&stat);
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tmp1 = rl78_stack_pop (&stat);
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tmp2 = rl78_stack_pop (&status);
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tmp1 = rl78_stack_pop (&status);
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tmp1 <<= tmp2;
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rl78_stack_push (tmp1, &stat);
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rl78_stack_push (tmp1, &status);
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break;
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case R_RL78_OPshra:
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tmp2 = rl78_stack_pop (&stat);
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tmp1 = rl78_stack_pop (&stat);
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tmp2 = rl78_stack_pop (&status);
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tmp1 = rl78_stack_pop (&status);
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tmp1 >>= tmp2;
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rl78_stack_push (tmp1, &stat);
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rl78_stack_push (tmp1, &status);
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break;
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case R_RL78_OPsctsize:
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rl78_stack_push (input_section->size, &stat);
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rl78_stack_push (input_section->size, &status);
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break;
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case R_RL78_OPscttop:
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rl78_stack_push (input_section->output_section->vma, &stat);
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rl78_stack_push (input_section->output_section->vma, &status);
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break;
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case R_RL78_OPand:
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tmp2 = rl78_stack_pop (&stat);
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tmp1 = rl78_stack_pop (&stat);
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tmp2 = rl78_stack_pop (&status);
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tmp1 = rl78_stack_pop (&status);
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tmp1 &= tmp2;
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rl78_stack_push (tmp1, &stat);
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rl78_stack_push (tmp1, &status);
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break;
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case R_RL78_OPor:
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tmp2 = rl78_stack_pop (&stat);
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tmp1 = rl78_stack_pop (&stat);
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tmp2 = rl78_stack_pop (&status);
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tmp1 = rl78_stack_pop (&status);
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tmp1 |= tmp2;
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rl78_stack_push (tmp1, &stat);
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rl78_stack_push (tmp1, &status);
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break;
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case R_RL78_OPxor:
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tmp2 = rl78_stack_pop (&stat);
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tmp1 = rl78_stack_pop (&stat);
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tmp2 = rl78_stack_pop (&status);
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tmp1 = rl78_stack_pop (&status);
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tmp1 ^= tmp2;
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rl78_stack_push (tmp1, &stat);
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rl78_stack_push (tmp1, &status);
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break;
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case R_RL78_OPnot:
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tmp1 = rl78_stack_pop (&stat);
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tmp1 = rl78_stack_pop (&status);
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tmp1 = ~ tmp1;
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rl78_stack_push (tmp1, &stat);
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rl78_stack_push (tmp1, &status);
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break;
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case R_RL78_OPmod:
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tmp2 = rl78_stack_pop (&stat);
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tmp1 = rl78_stack_pop (&stat);
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tmp2 = rl78_stack_pop (&status);
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tmp1 = rl78_stack_pop (&status);
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if (tmp2 != 0)
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tmp1 %= tmp2;
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else
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{
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tmp1 = 0;
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stat = bfd_reloc_overflow;
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status = bfd_reloc_overflow;
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}
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rl78_stack_push (tmp1, &stat);
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rl78_stack_push (tmp1, &status);
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break;
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}
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if (r)
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{
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if (stat == bfd_reloc_dangerous)
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if (status == bfd_reloc_dangerous)
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*error_message = (_("RL78 reloc stack overflow/underflow"));
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else if (stat == bfd_reloc_overflow)
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else if (status == bfd_reloc_overflow)
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{
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stat = bfd_reloc_dangerous;
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status = bfd_reloc_dangerous;
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*error_message = (_("RL78 reloc divide by zero"));
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}
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*r = stat;
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*r = status;
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}
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return relocation;
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}
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@ -100,7 +100,7 @@ compress_finish (bool use_zstd, void *ctx, char **next_out,
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{
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#if HAVE_ZSTD
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ZSTD_outBuffer ob = { *next_out, *avail_out, 0 };
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ZSTD_inBuffer ib = { 0 };
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ZSTD_inBuffer ib = { 0, 0, 0 };
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size_t ret = ZSTD_compressStream2 (ctx, &ob, &ib, ZSTD_e_end);
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*out_size = ob.pos;
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*next_out += ob.pos;
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@ -104,8 +104,6 @@ struct xtensa_config_v2
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int xtensa_march_earliest;
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};
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typedef struct xtensa_isa_internal_struct xtensa_isa_internal;
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extern const void *xtensa_load_config (const char *name,
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const void *no_plugin_def,
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const void *no_name_def);
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@ -328,7 +328,7 @@ static struct loongarch_opcode loongarch_macro_opcodes[] =
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{ 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64_LARGE_ABS, 0 },
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{ 0, 0, "la.tls.gd", "r,r,l", INSN_LA_TLS_GD64_LARGE_PCREL, 0 },
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{ 0 } /* Terminate the list. */
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{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
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};
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static struct loongarch_opcode loongarch_fix_opcodes[] =
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@ -428,7 +428,7 @@ static struct loongarch_opcode loongarch_fix_opcodes[] =
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{ 0x00608000, 0xffe08000, "bstrpick.w", "r0:5,r5:5,u16:5,u10:5", 0, 0, 0, 0 },
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{ 0x00800000, 0xffc00000, "bstrins.d", "r0:5,r5:5,u16:6,u10:6", 0, 0, 0, 0 },
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{ 0x00c00000, 0xffc00000, "bstrpick.d", "r0:5,r5:5,u16:6,u10:6", 0, 0, 0, 0 },
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{ 0 } /* Terminate the list. */
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{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
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};
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static struct loongarch_opcode loongarch_single_float_opcodes[] =
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@ -475,7 +475,7 @@ static struct loongarch_opcode loongarch_single_float_opcodes[] =
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{ 0x011d1000, 0xfffffc00, "ffint.s.w", "f0:5,f5:5", 0, 0, 0, 0 },
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{ 0x011d1800, 0xfffffc00, "ffint.s.l", "f0:5,f5:5", 0, 0, 0, 0 },
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{ 0x011e4400, 0xfffffc00, "frint.s", "f0:5,f5:5", 0, 0, 0, 0 },
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{ 0 } /* Terminate the list. */
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{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
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};
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static struct loongarch_opcode loongarch_double_float_opcodes[] =
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{
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@ -515,7 +515,7 @@ static struct loongarch_opcode loongarch_double_float_opcodes[] =
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{ 0x011d2000, 0xfffffc00, "ffint.d.w", "f0:5,f5:5", 0, 0, 0, 0 },
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{ 0x011d2800, 0xfffffc00, "ffint.d.l", "f0:5,f5:5", 0, 0, 0, 0 },
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{ 0x011e4800, 0xfffffc00, "frint.d", "f0:5,f5:5", 0, 0, 0, 0 },
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{ 0 } /* Terminate the list. */
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{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
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};
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static struct loongarch_opcode loongarch_imm_opcodes[] =
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@ -537,7 +537,7 @@ static struct loongarch_opcode loongarch_imm_opcodes[] =
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{ 0x1a000000, 0xfe000000, "pcalau12i", "r0:5,s5:20", 0, 0, 0, 0 },
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{ 0x1c000000, 0xfe000000, "pcaddu12i", "r0:5,s5:20", 0, 0, 0, 0 },
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{ 0x1e000000, 0xfe000000, "pcaddu18i", "r0:5,s5:20", 0, 0, 0, 0 },
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{ 0 } /* Terminate the list. */
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{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
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};
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static struct loongarch_opcode loongarch_privilege_opcodes[] =
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@ -566,7 +566,7 @@ static struct loongarch_opcode loongarch_privilege_opcodes[] =
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{ 0x06483800, 0xffffffff, "ertn", "", 0, 0, 0, 0 },
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{ 0x06488000, 0xffff8000, "idle", "u0:15", 0, 0, 0, 0 },
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{ 0x06498000, 0xffff8000, "invtlb", "u0:5,r5:5,r10:5", 0, 0, 0, 0 },
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{ 0 } /* Terminate the list. */
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{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
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};
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static struct loongarch_opcode loongarch_4opt_single_float_opcodes[] =
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@ -603,7 +603,7 @@ static struct loongarch_opcode loongarch_4opt_single_float_opcodes[] =
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{ 0x0c1c0000, 0xffff8018, "fcmp.cune.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 },
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{ 0x0c1c8000, 0xffff8018, "fcmp.sune.s", "c0:3,f5:5,f10:5", 0, 0, 0, 0 },
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{ 0x0d000000, 0xfffc0000, "fsel", "f0:5,f5:5,f10:5,c15:3", 0, 0, 0, 0 },
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{ 0 } /* Terminate the list. */
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{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
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};
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static struct loongarch_opcode loongarch_4opt_double_float_opcodes[] =
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@ -639,7 +639,7 @@ static struct loongarch_opcode loongarch_4opt_double_float_opcodes[] =
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{ 0x0c2a8000, 0xffff8018, "fcmp.sor.d", "c0:3,f5:5,f10:5", 0, 0, 0, 0 },
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{ 0x0c2c0000, 0xffff8018, "fcmp.cune.d", "c0:3,f5:5,f10:5", 0, 0, 0, 0 },
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{ 0x0c2c8000, 0xffff8018, "fcmp.sune.d", "c0:3,f5:5,f10:5", 0, 0, 0, 0 },
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{ 0 } /* Terminate the list. */
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{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
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};
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static struct loongarch_opcode loongarch_load_store_opcodes[] =
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@ -767,7 +767,7 @@ static struct loongarch_opcode loongarch_load_store_opcodes[] =
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{ 0x387e8000, 0xffff8000, "stle.h", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
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{ 0x387f0000, 0xffff8000, "stle.w", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
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{ 0x387f8000, 0xffff8000, "stle.d", "r0:5,r5:5,r10:5", 0, 0, 0, 0 },
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{ 0 } /* Terminate the list. */
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{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
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};
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static struct loongarch_opcode loongarch_single_float_load_store_opcodes[] =
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@ -781,7 +781,7 @@ static struct loongarch_opcode loongarch_single_float_load_store_opcodes[] =
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{ 0x38750000, 0xffff8000, "fldle.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
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{ 0x38760000, 0xffff8000, "fstgt.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
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{ 0x38770000, 0xffff8000, "fstle.s", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
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{ 0 } /* Terminate the list. */
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{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
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};
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static struct loongarch_opcode loongarch_double_float_load_store_opcodes[] =
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@ -795,7 +795,7 @@ static struct loongarch_opcode loongarch_double_float_load_store_opcodes[] =
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{ 0x38758000, 0xffff8000, "fldle.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
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{ 0x38768000, 0xffff8000, "fstgt.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
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{ 0x38778000, 0xffff8000, "fstle.d", "f0:5,r5:5,r10:5", 0, &LARCH_opts.ase_lp64, 0, 0 },
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{ 0 } /* Terminate the list. */
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{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
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};
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static struct loongarch_opcode loongarch_float_jmp_opcodes[] =
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@ -804,7 +804,7 @@ static struct loongarch_opcode loongarch_float_jmp_opcodes[] =
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{ 0x48000000, 0xfc000300, "bceqz", "c5:3,sb0:5|10:16<<2", 0, 0, 0, 0 },
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{ 0x0, 0x0, "bcnez", "c,la", "bcnez %1,%%b21(%2)", 0, 0, 0 },
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{ 0x48000100, 0xfc000300, "bcnez", "c5:3,sb0:5|10:16<<2", 0, 0, 0, 0 },
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{ 0 } /* Terminate the list. */
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{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
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};
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static struct loongarch_opcode loongarch_jmp_opcodes[] =
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@ -842,7 +842,7 @@ static struct loongarch_opcode loongarch_jmp_opcodes[] =
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{ 0x0, 0x0, "bleu", "r,r,la", "bgeu %2,%1,%%b16(%3)", 0, 0, 0 },
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{ 0x0, 0x0, "jr", "r", "jirl $r0,%1,0", 0, 0, 0 },
|
||||
{ 0x0, 0x0, "ret", "", "jirl $r0,$r1,0", 0, 0, 0 },
|
||||
{ 0 } /* Terminate the list. */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0 } /* Terminate the list. */
|
||||
};
|
||||
|
||||
struct loongarch_ase loongarch_ASEs[] =
|
||||
@ -860,5 +860,5 @@ struct loongarch_ase loongarch_ASEs[] =
|
||||
{ &LARCH_opts.ase_df, loongarch_4opt_double_float_opcodes, 0, 0, { 0 }, 0, 0 },
|
||||
{ &LARCH_opts.ase_sf, loongarch_single_float_load_store_opcodes, 0, 0, { 0 }, 0, 0 },
|
||||
{ &LARCH_opts.ase_df, loongarch_double_float_load_store_opcodes, 0, 0, { 0 }, 0, 0 },
|
||||
{ 0 },
|
||||
{ 0, 0, 0, 0, { 0 }, 0, 0 },
|
||||
};
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user