aarch64: Move vectype_to_qualifier further up
This patch just moves vectype_to_qualifier further up, so that a later patch can call it at an earlier point in the file. No behavioural change intended.
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@ -694,6 +694,81 @@ first_error_fmt (const char *format, ...)
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}
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}
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/* Internal helper routine converting a vector_type_el structure *VECTYPE
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to a corresponding operand qualifier. */
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static inline aarch64_opnd_qualifier_t
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vectype_to_qualifier (const struct vector_type_el *vectype)
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{
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/* Element size in bytes indexed by vector_el_type. */
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const unsigned char ele_size[5]
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= {1, 2, 4, 8, 16};
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const unsigned int ele_base [5] =
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{
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AARCH64_OPND_QLF_V_4B,
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AARCH64_OPND_QLF_V_2H,
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AARCH64_OPND_QLF_V_2S,
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AARCH64_OPND_QLF_V_1D,
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AARCH64_OPND_QLF_V_1Q
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};
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if (!vectype->defined || vectype->type == NT_invtype)
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goto vectype_conversion_fail;
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if (vectype->type == NT_zero)
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return AARCH64_OPND_QLF_P_Z;
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if (vectype->type == NT_merge)
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return AARCH64_OPND_QLF_P_M;
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gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
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if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH))
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{
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/* Special case S_4B. */
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if (vectype->type == NT_b && vectype->width == 4)
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return AARCH64_OPND_QLF_S_4B;
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/* Special case S_2H. */
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if (vectype->type == NT_h && vectype->width == 2)
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return AARCH64_OPND_QLF_S_2H;
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/* Vector element register. */
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return AARCH64_OPND_QLF_S_B + vectype->type;
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}
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else
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{
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/* Vector register. */
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int reg_size = ele_size[vectype->type] * vectype->width;
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unsigned offset;
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unsigned shift;
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if (reg_size != 16 && reg_size != 8 && reg_size != 4)
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goto vectype_conversion_fail;
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/* The conversion is by calculating the offset from the base operand
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qualifier for the vector type. The operand qualifiers are regular
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enough that the offset can established by shifting the vector width by
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a vector-type dependent amount. */
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shift = 0;
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if (vectype->type == NT_b)
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shift = 3;
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else if (vectype->type == NT_h || vectype->type == NT_s)
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shift = 2;
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else if (vectype->type >= NT_d)
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shift = 1;
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else
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gas_assert (0);
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offset = ele_base [vectype->type] + (vectype->width >> shift);
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gas_assert (AARCH64_OPND_QLF_V_4B <= offset
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&& offset <= AARCH64_OPND_QLF_V_1Q);
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return offset;
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}
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vectype_conversion_fail:
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first_error (_("bad vector arrangement type"));
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return AARCH64_OPND_QLF_NIL;
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}
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/* Register parsing. */
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/* Generic register parser which is called by other specialized
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@ -5905,81 +5980,6 @@ opcode_lookup (char *base, char *dot, char *end)
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return NULL;
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}
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/* Internal helper routine converting a vector_type_el structure *VECTYPE
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to a corresponding operand qualifier. */
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static inline aarch64_opnd_qualifier_t
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vectype_to_qualifier (const struct vector_type_el *vectype)
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{
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/* Element size in bytes indexed by vector_el_type. */
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const unsigned char ele_size[5]
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= {1, 2, 4, 8, 16};
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const unsigned int ele_base [5] =
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{
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AARCH64_OPND_QLF_V_4B,
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AARCH64_OPND_QLF_V_2H,
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AARCH64_OPND_QLF_V_2S,
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AARCH64_OPND_QLF_V_1D,
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AARCH64_OPND_QLF_V_1Q
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};
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if (!vectype->defined || vectype->type == NT_invtype)
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goto vectype_conversion_fail;
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if (vectype->type == NT_zero)
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return AARCH64_OPND_QLF_P_Z;
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if (vectype->type == NT_merge)
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return AARCH64_OPND_QLF_P_M;
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gas_assert (vectype->type >= NT_b && vectype->type <= NT_q);
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if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH))
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{
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/* Special case S_4B. */
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if (vectype->type == NT_b && vectype->width == 4)
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return AARCH64_OPND_QLF_S_4B;
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/* Special case S_2H. */
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if (vectype->type == NT_h && vectype->width == 2)
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return AARCH64_OPND_QLF_S_2H;
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/* Vector element register. */
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return AARCH64_OPND_QLF_S_B + vectype->type;
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}
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else
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{
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/* Vector register. */
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int reg_size = ele_size[vectype->type] * vectype->width;
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unsigned offset;
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unsigned shift;
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if (reg_size != 16 && reg_size != 8 && reg_size != 4)
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goto vectype_conversion_fail;
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/* The conversion is by calculating the offset from the base operand
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qualifier for the vector type. The operand qualifiers are regular
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enough that the offset can established by shifting the vector width by
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a vector-type dependent amount. */
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shift = 0;
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if (vectype->type == NT_b)
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shift = 3;
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else if (vectype->type == NT_h || vectype->type == NT_s)
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shift = 2;
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else if (vectype->type >= NT_d)
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shift = 1;
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else
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gas_assert (0);
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offset = ele_base [vectype->type] + (vectype->width >> shift);
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gas_assert (AARCH64_OPND_QLF_V_4B <= offset
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&& offset <= AARCH64_OPND_QLF_V_1Q);
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return offset;
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}
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vectype_conversion_fail:
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first_error (_("bad vector arrangement type"));
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return AARCH64_OPND_QLF_NIL;
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}
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/* Process an optional operand that is found omitted from the assembly line.
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Fill *OPERAND for such an operand of type TYPE. OPCODE points to the
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instruction's opcode entry while IDX is the index of this omitted operand.
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