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aarch64: Add +rcpc2 flag for existing instructions

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This commit is contained in:
Andrew Carlotti 2024-01-12 01:44:10 +00:00 committed by Nick Clifton
parent 5329ef9b8e
commit 368910707c
6 changed files with 2254 additions and 14 deletions
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1
gas/config/tc-aarch64.c
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@ -10286,6 +10286,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_FEATURES (2, F16, SIMD)},
{"jscvt", AARCH64_FEATURE (JSCVT), AARCH64_FEATURE (FP)},
{"rcpc", AARCH64_FEATURE (RCPC), AARCH64_NO_FEATURES},
{"rcpc2", AARCH64_FEATURE (RCPC2), AARCH64_FEATURE (RCPC)},
{"dotprod", AARCH64_FEATURE (DOTPROD), AARCH64_FEATURE (SIMD)},
{"sha2", AARCH64_FEATURE (SHA2), AARCH64_FEATURE (FP)},
{"frintts", AARCH64_FEATURE (FRINTTS), AARCH64_FEATURE (SIMD)},

2
gas/testsuite/gas/aarch64/armv8_4-a.d
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@ -2202,4 +2202,4 @@ Disassembly of section \.text:
[^:]+:\s+998033fe ldapursw x30, \[sp, #3\]
[^:]+:\s+998523fe ldapursw x30, \[sp, #82\]
[^:]+:\s+9980d3fe ldapursw x30, \[sp, #13\]
[^:]+:\s+d500401f cfinv
[^:]+:\s+d500401f cfinv

2088
gas/testsuite/gas/aarch64/rcpc2.d Normal file
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File diff suppressed because it is too large Load Diff

143
gas/testsuite/gas/aarch64/rcpc2.s Normal file
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@ -0,0 +1,143 @@
# Print a 4 operand instruction
.macro print_gen4reg op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, w , pw1=, pw2=
.ifnb \d
\op \pd1\d\()\pd2, \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
.else
.ifnb \n
\op \pn1\n\()\pn2, \pm1\m\()\pm2, \pw1\w\()\pw2
.else
\op \pm1\m\()\pm2, \pw1\w\()\pw2
.endif
.endif
.endm
.macro gen4reg_iter_d_offset op, d, pd1=, pd2=, r
.irp m, 03, 82, 13
\op \pd1\d\()\pd2, [\r, \m]
.endr
.endm
.macro gen4reg_iter_d_n_w op, d, pd1=, pd2=, n, pn1=, pn2=, m, pm1=, pm2=, pw1=, pw2=
.irp w, 3, 11, 15
print_gen4reg \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \w, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter_d_n op, d, pd1=, pd2=, n, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp m, 0, 8, 12
gen4reg_iter_d_n_w \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \m, \pm1, \pm2, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter_d op, d, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp n, 2, 15, 30
gen4reg_iter_d_n \op, \d, \pd1, \pd2, \n, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2
.endr
.endm
.macro gen4reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d \op, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2
.endr
.endm
# Print a 3 operand instruction
.macro gen3reg_iter op, pd1=, pd2=, pn1=, pn2=, pm1=, pm2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d \op,,, \d, \pd1, \pd2, \pn1, \pn2, \pm1, \pm2
.endr
.endm
.macro gen3reg_iter_lane op, pn1=, pn2=, pm1=, pm2=, pw1=, pw2=, x:vararg
.irp l, \x
gen4reg_iter_d \op,,,, \pn1, \pn2, \pm1, \pm2, \pw1, \pw2[\l]
.endr
.endm
# Print a 2 operand instruction
.macro gen2reg_iter op, pd1=, pd2=, pn1=, pn2=
.irp d, 0, 7, 16, 30
gen4reg_iter_d_n \op,,,,,, \d, \pd1, \pd2, \pn1, \pn2
.endr
.endm
.macro gen2reg_iter_offset op, pd1=, pd2=, r
.irp d, 0, 7, 16, 30
gen4reg_iter_d_offset \op, \d, \pd1, \pd2, \r,
.endr
.endm
# Print a 1 operand instruction
.macro gen1reg_iter op, pd1=, pd2=
.irp d, 0, 7, 16, 30
\op \pd1\d\()\pd2
.endr
.endm
.text
func:
gen2reg_iter stlurb w,,[x,]
gen1reg_iter stlurb w,", [sp]"
gen3reg_iter stlurb w,, [x,,,]
gen2reg_iter_offset stlurb w,,sp
gen2reg_iter ldapurb w,,[x,]
gen1reg_iter ldapurb w,", [sp]"
gen3reg_iter ldapurb w,, [x,,,]
gen2reg_iter_offset ldapurb w,,sp
gen2reg_iter ldapursb w,,[x,]
gen1reg_iter ldapursb w,", [sp]"
gen3reg_iter ldapursb w,, [x,,,]
gen2reg_iter_offset ldapursb w,,sp
gen2reg_iter ldapursb x,,[x,]
gen1reg_iter ldapursb x,", [sp]"
gen3reg_iter ldapursb x,, [x,,,]
gen2reg_iter_offset ldapursb x,,sp
gen2reg_iter stlurh w,,[x,]
gen1reg_iter stlurh w,", [sp]"
gen3reg_iter stlurh w,, [x,,,]
gen2reg_iter_offset stlurh w,,sp
gen2reg_iter ldapurh w,,[x,]
gen1reg_iter ldapurh w,", [sp]"
gen3reg_iter ldapurh w,, [x,,,]
gen2reg_iter_offset ldapurh w,,sp
gen2reg_iter ldapursh w,,[x,]
gen1reg_iter ldapursh w,", [sp]"
gen3reg_iter ldapursh w,, [x,,,]
gen2reg_iter_offset ldapursh w,,sp
gen2reg_iter ldapursh x,,[x,]
gen1reg_iter ldapursh x,", [sp]"
gen3reg_iter ldapursh x,, [x,,,]
gen2reg_iter_offset ldapursh x,,sp
gen2reg_iter stlur w,,[x,]
gen1reg_iter stlur w,", [sp]"
gen3reg_iter stlur w,, [x,,,]
gen2reg_iter_offset stlur w,,sp
gen2reg_iter stlur x,,[x,]
gen1reg_iter stlur x,", [sp]"
gen3reg_iter stlur x,, [x,,,]
gen2reg_iter_offset stlur x,,sp
gen2reg_iter ldapur w,,[x,]
gen1reg_iter ldapur w,", [sp]"
gen3reg_iter ldapur w,, [x,,,]
gen2reg_iter_offset ldapur w,,sp
gen2reg_iter ldapur x,,[x,]
gen1reg_iter ldapur x,", [sp]"
gen3reg_iter ldapur x,, [x,,,]
gen2reg_iter_offset ldapur x,,sp
gen2reg_iter ldapursw x,,[x,]
gen1reg_iter ldapursw x,", [sp]"
gen3reg_iter ldapursw x,, [x,,,]
gen2reg_iter_offset ldapursw x,,sp

3
include/opcode/aarch64.h
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@ -97,6 +97,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SVE,
/* RCPC instructions. */
AARCH64_FEATURE_RCPC,
/* RCPC2 instructions. */
AARCH64_FEATURE_RCPC2,
/* Complex # instructions. */
AARCH64_FEATURE_COMPNUM,
/* JavaScript conversion instructions. */
@ -251,6 +253,7 @@ enum aarch64_feature_bit {
| AARCH64_FEATBIT (X, COMPNUM) \
| AARCH64_FEATBIT (X, JSCVT))
#define AARCH64_ARCH_V8_4A_FEATURES(X) (AARCH64_FEATBIT (X, V8_4A) \
| AARCH64_FEATBIT (X, RCPC2) \
| AARCH64_FEATBIT (X, DOTPROD) \
| AARCH64_FEATBIT (X, FLAGM) \
| AARCH64_FEATBIT (X, F16_FML))

31
opcodes/aarch64-tbl.h
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@ -2522,6 +2522,8 @@ static const aarch64_feature_set aarch64_feature_jscvt =
AARCH64_FEATURE (JSCVT);
static const aarch64_feature_set aarch64_feature_rcpc =
AARCH64_FEATURE (RCPC);
static const aarch64_feature_set aarch64_feature_rcpc2 =
AARCH64_FEATURE (RCPC2);
static const aarch64_feature_set aarch64_feature_dotprod =
AARCH64_FEATURE (DOTPROD);
static const aarch64_feature_set aarch64_feature_sha2 =
@ -2635,6 +2637,7 @@ static const aarch64_feature_set aarch64_feature_d128_the =
#define COMPNUM &aarch64_feature_compnum
#define JSCVT &aarch64_feature_jscvt
#define RCPC &aarch64_feature_rcpc
#define RCPC2 &aarch64_feature_rcpc2
#define SHA2 &aarch64_feature_sha2
#define AES &aarch64_feature_aes
#define ARMV8_4A &aarch64_feature_v8_4a
@ -2724,6 +2727,8 @@ static const aarch64_feature_set aarch64_feature_d128_the =
{ NAME, OPCODE, MASK, CLASS, 0, JSCVT, OPS, QUALS, FLAGS, 0, 0, NULL }
#define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, 0, NULL }
#define RCPC2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, RCPC2, OPS, QUALS, FLAGS, 0, 0, NULL }
#define SHA2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, SHA2, OPS, QUALS, FLAGS, 0, 0, NULL }
#define AES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@ -6040,19 +6045,19 @@ const struct aarch64_opcode aarch64_opcode_table[] =
FLAGM_INSN ("setf8", 0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
FLAGM_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
/* Memory access instructions ARMv8.4-a. */
V8_4A_INSN ("stlurb" , 0x19000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4A_INSN ("ldapurb", 0x19400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4A_INSN ("ldapursb", 0x19c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4A_INSN ("ldapursb", 0x19800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
V8_4A_INSN ("stlurh", 0x59000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4A_INSN ("ldapurh", 0x59400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4A_INSN ("ldapursh", 0x59c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4A_INSN ("ldapursh", 0x59800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
V8_4A_INSN ("stlur", 0x99000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4A_INSN ("ldapur", 0x99400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
V8_4A_INSN ("ldapursw", 0x99800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
V8_4A_INSN ("stlur", 0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
V8_4A_INSN ("ldapur", 0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
RCPC2_INSN ("stlurb" , 0x19000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
RCPC2_INSN ("ldapurb", 0x19400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
RCPC2_INSN ("ldapursb", 0x19c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
RCPC2_INSN ("ldapursb", 0x19800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
RCPC2_INSN ("stlurh", 0x59000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
RCPC2_INSN ("ldapurh", 0x59400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
RCPC2_INSN ("ldapursh", 0x59c00000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
RCPC2_INSN ("ldapursh", 0x59800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
RCPC2_INSN ("stlur", 0x99000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
RCPC2_INSN ("ldapur", 0x99400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
RCPC2_INSN ("ldapursw", 0x99800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
RCPC2_INSN ("stlur", 0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
RCPC2_INSN ("ldapur", 0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
/* Matrix Multiply instructions. */
INT8MATMUL_SVE_INSNC ("smmla", 0x45009800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),